Re: [PATCH v2] ARM: dts: add reset property for rk3066a-rayeager emac phy

Hi Heiko Thanks :) On 2017??12??17?? 04:11, Heiko Stuebner wrote: Hi Chris, Am Mittwoch, 8. November 2017, 17:50:41 CET schrieb Chris Zhong: The ethernet phy of rk3066a-rayeager has a reset pin, it controlled by GPIO1_D6, this pin should be pull down then pull up to reset the phy. Add

Re: [PATCH v2] ARM: dts: add reset property for rk3066a-rayeager emac phy

Hi Heiko Thanks :) On 2017??12??17?? 04:11, Heiko Stuebner wrote: Hi Chris, Am Mittwoch, 8. November 2017, 17:50:41 CET schrieb Chris Zhong: The ethernet phy of rk3066a-rayeager has a reset pin, it controlled by GPIO1_D6, this pin should be pull down then pull up to reset the phy. Add

Re: [PATCH 0/4] Move DP phy switch to PHY driver

Hi Heiko On 2017??12??02?? 05:58, Heiko Stuebner wrote: Am Freitag, 1. Dezember 2017, 13:42:46 CET schrieb Doug Anderson: Hi, On Wed, Nov 29, 2017 at 6:27 PM, Chris Zhong <z...@rock-chips.com> wrote: Hi Doug Thank you for mentioning this patch. I think the focus of the discussion i

Re: [PATCH 0/4] Move DP phy switch to PHY driver

Hi Heiko On 2017??12??02?? 05:58, Heiko Stuebner wrote: Am Freitag, 1. Dezember 2017, 13:42:46 CET schrieb Doug Anderson: Hi, On Wed, Nov 29, 2017 at 6:27 PM, Chris Zhong wrote: Hi Doug Thank you for mentioning this patch. I think the focus of the discussion is: can we put the grf

Re: [PATCH 0/4] Move DP phy switch to PHY driver

of Type-C phy, these 2 phy have different bits, just similar to other bits (such as "pipe-status"). Put them to DTS file might be a accepted practice. On 2017年11月29日 07:32, Doug Anderson wrote: Hi, On Thu, Feb 9, 2017 at 11:44 PM, Chris Zhong <z...@rock-chips.com> wrote

Re: [PATCH 0/4] Move DP phy switch to PHY driver

of Type-C phy, these 2 phy have different bits, just similar to other bits (such as "pipe-status"). Put them to DTS file might be a accepted practice. On 2017年11月29日 07:32, Doug Anderson wrote: Hi, On Thu, Feb 9, 2017 at 11:44 PM, Chris Zhong wrote: There are 2 Type-c PHYs in

Re: [PATCH] ARM: dts: add phy-reset property for rk3066a-rayeager emac

Hi Florian Fainelli On 2017年11月08日 02:26, Florian Fainelli wrote: On 11/07/2017 01:51 AM, Chris Zhong wrote: On 2017年11月07日 15:54, Vladimir Zapolskiy wrote: Hello Chris, On 11/07/2017 04:49 AM, Chris Zhong wrote: The ethernet phy of rk3066a-rayeager has a reset pin, it controlled

[PATCH v2] ARM: dts: add reset property for rk3066a-rayeager emac phy

The ethernet phy of rk3066a-rayeager has a reset pin, it controlled by GPIO1_D6, this pin should be pull down then pull up to reset the phy. Add a reset-gpios property in phy0, make the phy can be reset when emac power on. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v

Re: [PATCH] ARM: dts: add phy-reset property for rk3066a-rayeager emac

Hi Florian Fainelli On 2017年11月08日 02:26, Florian Fainelli wrote: On 11/07/2017 01:51 AM, Chris Zhong wrote: On 2017年11月07日 15:54, Vladimir Zapolskiy wrote: Hello Chris, On 11/07/2017 04:49 AM, Chris Zhong wrote: The ethernet phy of rk3066a-rayeager has a reset pin, it controlled

[PATCH v2] ARM: dts: add reset property for rk3066a-rayeager emac phy

The ethernet phy of rk3066a-rayeager has a reset pin, it controlled by GPIO1_D6, this pin should be pull down then pull up to reset the phy. Add a reset-gpios property in phy0, make the phy can be reset when emac power on. Signed-off-by: Chris Zhong --- Changes in v2: use a generic property

Re: [PATCH] ARM: dts: add phy-reset property for rk3066a-rayeager emac

On 2017年11月07日 15:54, Vladimir Zapolskiy wrote: Hello Chris, On 11/07/2017 04:49 AM, Chris Zhong wrote: The ethernet phy of rk3066a-rayeager has a reset pin, it controlled by GPIO1_D6, this pin should be pull down then pull up to reset the phy. Add a phy-reset property in emac, make the phy

Re: [PATCH] ARM: dts: add phy-reset property for rk3066a-rayeager emac

On 2017年11月07日 15:54, Vladimir Zapolskiy wrote: Hello Chris, On 11/07/2017 04:49 AM, Chris Zhong wrote: The ethernet phy of rk3066a-rayeager has a reset pin, it controlled by GPIO1_D6, this pin should be pull down then pull up to reset the phy. Add a phy-reset property in emac, make the phy

[PATCH] ARM: dts: add phy-reset property for rk3066a-rayeager emac

The ethernet phy of rk3066a-rayeager has a reset pin, it controlled by GPIO1_D6, this pin should be pull down then pull up to reset the phy. Add a phy-reset property in emac, make the phy can be reset when emac power on. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- arch/arm/bo

[PATCH] ARM: dts: add phy-reset property for rk3066a-rayeager emac

The ethernet phy of rk3066a-rayeager has a reset pin, it controlled by GPIO1_D6, this pin should be pull down then pull up to reset the phy. Add a phy-reset property in emac, make the phy can be reset when emac power on. Signed-off-by: Chris Zhong --- arch/arm/boot/dts/rk3066a-rayeager.dts | 2

Re: [PATCH] ARM: Fix zImage file size not aligned with CONFIG_EFI_STUB enabled

Tested-by: Chris Zhong <z...@rock-chips.com> On Wednesday, October 18, 2017 01:01 PM, Jeffy Chen wrote: The zImage file size should be aligned. Fixes: e4bae4d0b5f3 ("arm/efi: Split zImage code and data into separate PE/COFF sections") Signed-off-by: Jeffy Chen <jeffy.

Re: [PATCH] ARM: Fix zImage file size not aligned with CONFIG_EFI_STUB enabled

Tested-by: Chris Zhong On Wednesday, October 18, 2017 01:01 PM, Jeffy Chen wrote: The zImage file size should be aligned. Fixes: e4bae4d0b5f3 ("arm/efi: Split zImage code and data into separate PE/COFF sections") Signed-off-by: Jeffy Chen --- arch/arm/boot/compressed/vmlinux

[PATCH v3 2/2] drm/rockchip: cdn-dp: send audio infoframe to sink

Some DP/HDMI sink need to receive the audio infoframe to play sound, especially some multi-channel AV receiver, they need the channel_allocation from infoframe to config the speakers. Send the audio infoframe via SDP will make them work properly. Signed-off-by: Chris Zhong <z...@rock-chips.

[PATCH v3 2/2] drm/rockchip: cdn-dp: send audio infoframe to sink

Some DP/HDMI sink need to receive the audio infoframe to play sound, especially some multi-channel AV receiver, they need the channel_allocation from infoframe to config the speakers. Send the audio infoframe via SDP will make them work properly. Signed-off-by: Chris Zhong --- Changes in v3

[PATCH v3 1/2] video/hdmi: Introduce helpers for the HDMI audio infoframe payload

The DP is using the same audio infoframe payload as hdmi, per DP 1.3 spec, but it has a different header. Provide a new interface here, it just packs the payload. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v3: - add size < HDMI_AUDIO_INFOFRAME_SIZE check according

[PATCH v3 1/2] video/hdmi: Introduce helpers for the HDMI audio infoframe payload

The DP is using the same audio infoframe payload as hdmi, per DP 1.3 spec, but it has a different header. Provide a new interface here, it just packs the payload. Signed-off-by: Chris Zhong --- Changes in v3: - add size < HDMI_AUDIO_INFOFRAME_SIZE check according to Doug's advice Changes in

Re: [PATCH v2 1/2] video/hdmi: Introduce helpers for the HDMI audio infoframe payload

Hi Doug On Tuesday, July 18, 2017 11:16 PM, Doug Anderson wrote: Hi, On Tue, Jul 18, 2017 at 4:20 AM, Chris Zhong <z...@rock-chips.com> wrote: The DP is using the same audio infoframe payload as hdmi, per DP 1.3 spec, but it has a different header. Provide a new interface here, it just

Re: [PATCH v2 1/2] video/hdmi: Introduce helpers for the HDMI audio infoframe payload

Hi Doug On Tuesday, July 18, 2017 11:16 PM, Doug Anderson wrote: Hi, On Tue, Jul 18, 2017 at 4:20 AM, Chris Zhong wrote: The DP is using the same audio infoframe payload as hdmi, per DP 1.3 spec, but it has a different header. Provide a new interface here, it just packs the payload. Signed

Re: [PATCH] drm/rockchip: cdn-dp: send audio infoframe to sink

Hi Sean Thanks for your replying. On Tuesday, July 18, 2017 04:23 AM, Sean Paul wrote: On Sat, Jul 15, 2017 at 07:00:18PM +0800, Chris Zhong wrote: Some DP/HDMI sink need to receive the audio infoframe to play sound, especially some multi-channel AV receiver, they need the channel_allocation

Re: [PATCH] drm/rockchip: cdn-dp: send audio infoframe to sink

Hi Sean Thanks for your replying. On Tuesday, July 18, 2017 04:23 AM, Sean Paul wrote: On Sat, Jul 15, 2017 at 07:00:18PM +0800, Chris Zhong wrote: Some DP/HDMI sink need to receive the audio infoframe to play sound, especially some multi-channel AV receiver, they need the channel_allocation

[PATCH v2 1/2] video/hdmi: Introduce helpers for the HDMI audio infoframe payload

The DP is using the same audio infoframe payload as hdmi, per DP 1.3 spec, but it has a different header. Provide a new interface here, it just packs the payload. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v2: None drivers/video/hdmi.

[PATCH v2 2/2] drm/rockchip: cdn-dp: send audio infoframe to sink

Some DP/HDMI sink need to receive the audio infoframe to play sound, especially some multi-channel AV receiver, they need the channel_allocation from infoframe to config the speakers. Send the audio infoframe via SDP will make them work properly. Signed-off-by: Chris Zhong <z...@rock-chips.

[PATCH v2 1/2] video/hdmi: Introduce helpers for the HDMI audio infoframe payload

The DP is using the same audio infoframe payload as hdmi, per DP 1.3 spec, but it has a different header. Provide a new interface here, it just packs the payload. Signed-off-by: Chris Zhong --- Changes in v2: None drivers/video/hdmi.c | 66

[PATCH v2 2/2] drm/rockchip: cdn-dp: send audio infoframe to sink

Some DP/HDMI sink need to receive the audio infoframe to play sound, especially some multi-channel AV receiver, they need the channel_allocation from infoframe to config the speakers. Send the audio infoframe via SDP will make them work properly. Signed-off-by: Chris Zhong --- Changes in v2

[PATCH] drm/rockchip: cdn-dp: send audio infoframe to sink

Some DP/HDMI sink need to receive the audio infoframe to play sound, especially some multi-channel AV receiver, they need the channel_allocation from infoframe to config the speakers. Send the audio infoframe via SDP will make them work properly. Signed-off-by: Chris Zhong <z...@rock-chips.

[PATCH] drm/rockchip: cdn-dp: send audio infoframe to sink

Some DP/HDMI sink need to receive the audio infoframe to play sound, especially some multi-channel AV receiver, they need the channel_allocation from infoframe to config the speakers. Send the audio infoframe via SDP will make them work properly. Signed-off-by: Chris Zhong --- drivers/gpu/drm

[PATCH v4 2/2] drm/panel: add innolux,p079zca panel driver

Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI panel. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> Tested-by: Brian Norris <briannor...@chromium.org> --- Changes in v4: - remove backlight check aft

[PATCH v4 2/2] drm/panel: add innolux,p079zca panel driver

Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI panel. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Tested-by: Brian Norris --- Changes in v4: - remove backlight check after probe - add bpc info Changes in v3: - printk err after regulator_disable(innolux-&g

[PATCH v4 1/2] dt-bindings: Add INNOLUX P079ZCA panel bindings

The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and connected to DSI using four lanes. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Brian Norris <briannor...@chromium.org> --- Changes in v4: None Changes in v3: None Changes in v2: None ...

[PATCH v4 1/2] dt-bindings: Add INNOLUX P079ZCA panel bindings

The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and connected to DSI using four lanes. Signed-off-by: Chris Zhong Reviewed-by: Brian Norris --- Changes in v4: None Changes in v3: None Changes in v2: None .../bindings/display/panel/innolux,p079zca.txt

[PATCH v4 2/4] dt-bindings: add the grf clock for dw-mipi-dsi

For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> --- Changes in v4: - remove "additional" Changes in v3: No

[PATCH v4 2/4] dt-bindings: add the grf clock for dw-mipi-dsi

For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul --- Changes in v4: - remove "additional" Changes in v3: None Changes in v2: None .../devicetree/bindings/displa

[PATCH v4 3/4] drm/rockchip/dsi: enable the grf clk before writing grf registers

For RK3399, the grf clk should be enabled before writing grf registers, otherwise the register value can not be changed. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> --- Changes in v4: - print the err after clk_prepare_enable(

[PATCH v4 3/4] drm/rockchip/dsi: enable the grf clk before writing grf registers

For RK3399, the grf clk should be enabled before writing grf registers, otherwise the register value can not be changed. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul --- Changes in v4: - print the err after clk_prepare_enable(dsi->grf_clk) Changes in v3: - add a DW_MIPI_NEEDS_GRF_

[PATCH v4 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match RK3399. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chr

[PATCH v4 4/4] drm/rockchip/dsi: correct the grf_switch_reg name

For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20, not RK3399_GRF_SOC_CON19. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Brian Norris <briannor...@chromium.org> Reviewed-by: Sean Paul <seanp...@chromium.org> --- Changes in v4: None C

[PATCH v4 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match RK3399. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul --- Changes in v4: None Changes in v3: - add

[PATCH v4 4/4] drm/rockchip/dsi: correct the grf_switch_reg name

For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20, not RK3399_GRF_SOC_CON19. Signed-off-by: Chris Zhong Reviewed-by: Brian Norris Reviewed-by: Sean Paul --- Changes in v4: None Changes in v3: None Changes in v2: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1

[PATCH v4 0/4] RK3399 dw-mipi-dsi patches

in v3: - add a DW_MIPI_NEEDS_PHY_CFG_CLK for RK3399 - add a DW_MIPI_NEEDS_GRF_CLK for RK3399 Changes in v2: - check the grf_clk only for RK3399 Chris Zhong (4): drm/rockchip/dsi: check phy_cfg_clk only for RK3399 dt-bindings: add the grf clock for dw-mipi-dsi drm/rockchip/dsi: enable the grf clk before writing

[PATCH v4 0/4] RK3399 dw-mipi-dsi patches

in v3: - add a DW_MIPI_NEEDS_PHY_CFG_CLK for RK3399 - add a DW_MIPI_NEEDS_GRF_CLK for RK3399 Changes in v2: - check the grf_clk only for RK3399 Chris Zhong (4): drm/rockchip/dsi: check phy_cfg_clk only for RK3399 dt-bindings: add the grf clock for dw-mipi-dsi drm/rockchip/dsi: enable the grf clk before writing

[PATCH v3 1/2] dt-bindings: Add INNOLUX P079ZCA panel bindings

The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and connected to DSI using four lanes. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Brian Norris <briannor...@chromium.org> --- Changes in v3: None Changes in v2: None .../bindings/disp

[PATCH v3 1/2] dt-bindings: Add INNOLUX P079ZCA panel bindings

The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and connected to DSI using four lanes. Signed-off-by: Chris Zhong Reviewed-by: Brian Norris --- Changes in v3: None Changes in v2: None .../bindings/display/panel/innolux,p079zca.txt | 23 ++ 1

[PATCH v3 2/2] drm/panel: add innolux,p079zca panel driver

Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI panel. Signed-off-by: Chris Zhong <z...@rock-chips.com> Reviewed-by: Sean Paul <seanp...@chromium.org> Tested-by: Brian Norris <briannor...@chromium.org> --- Changes in v3: - printk err after regulator_

[PATCH v3 2/2] drm/panel: add innolux,p079zca panel driver

Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI panel. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul Tested-by: Brian Norris --- Changes in v3: - printk err after regulator_disable(innolux->supply) Changes in v2: - add some error check - always use Low po

[PATCH v3 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match RK3399. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v3: - add a DW_MIPI_NEEDS_PHY_C

[PATCH v3 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match RK3399. Signed-off-by: Chris Zhong --- Changes in v3: - add a DW_MIPI_NEEDS_PHY_CFG_CLK for RK3399 Changes

[PATCH v3 0/4] RK3399 dw-mipi-dsi patches

only for RK3399 Chris Zhong (4): drm/rockchip/dsi: check phy_cfg_clk only for RK3399 dt-bindings: add the grf clock for dw-mipi-dsi drm/rockchip/dsi: enable the grf clk before writing grf registers drm/rockchip/dsi: correct the grf_switch_reg name .../display/rockchip

[PATCH v3 0/4] RK3399 dw-mipi-dsi patches

only for RK3399 Chris Zhong (4): drm/rockchip/dsi: check phy_cfg_clk only for RK3399 dt-bindings: add the grf clock for dw-mipi-dsi drm/rockchip/dsi: enable the grf clk before writing grf registers drm/rockchip/dsi: correct the grf_switch_reg name .../display/rockchip

[PATCH v3 3/4] drm/rockchip/dsi: enable the grf clk before writing grf registers

For RK3399, the grf clk should be enabled before writing grf registers, otherwise the register value can not be changed. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v3: - add a DW_MIPI_NEEDS_GRF_CLK for RK3399 Changes in v2: - check the grf_clk only for RK3399 drive

[PATCH v3 3/4] drm/rockchip/dsi: enable the grf clk before writing grf registers

For RK3399, the grf clk should be enabled before writing grf registers, otherwise the register value can not be changed. Signed-off-by: Chris Zhong --- Changes in v3: - add a DW_MIPI_NEEDS_GRF_CLK for RK3399 Changes in v2: - check the grf_clk only for RK3399 drivers/gpu/drm/rockchip/dw-mipi

[PATCH v3 2/4] dt-bindings: add the grf clock for dw-mipi-dsi

For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v3: None Changes in v2: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +- 1 file c

[PATCH v3 4/4] drm/rockchip/dsi: correct the grf_switch_reg name

For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20, not RK3399_GRF_SOC_CON19. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v3: None Changes in v2: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

[PATCH v3 2/4] dt-bindings: add the grf clock for dw-mipi-dsi

For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock. Signed-off-by: Chris Zhong --- Changes in v3: None Changes in v2: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH v3 4/4] drm/rockchip/dsi: correct the grf_switch_reg name

For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20, not RK3399_GRF_SOC_CON19. Signed-off-by: Chris Zhong --- Changes in v3: None Changes in v2: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu

Re: [PATCH v2 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

Hi John On 03/16/2017 06:55 PM, John Keeping wrote: On Thu, 16 Mar 2017 11:31:44 +0800, Chris Zhong wrote: For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match

Re: [PATCH v2 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

Hi John On 03/16/2017 06:55 PM, John Keeping wrote: On Thu, 16 Mar 2017 11:31:44 +0800, Chris Zhong wrote: For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match

[PATCH v2 3/4] drm/rockchip/dsi: enable the grf clk before writing grf registers

For RK3399, the grf clk should be enabled before writing grf registers, otherwise the register value can not be changed. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v2: - check the grf_clk only for RK3399 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 21 ++

[PATCH v2 3/4] drm/rockchip/dsi: enable the grf clk before writing grf registers

For RK3399, the grf clk should be enabled before writing grf registers, otherwise the register value can not be changed. Signed-off-by: Chris Zhong --- Changes in v2: - check the grf_clk only for RK3399 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 21 + 1 file changed, 21

[PATCH v2 4/4] drm/rockchip/dsi: correct the grf_switch_reg name

For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20, not RK3399_GRF_SOC_CON19. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v2: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drive

[PATCH v2 4/4] drm/rockchip/dsi: correct the grf_switch_reg name

For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20, not RK3399_GRF_SOC_CON19. Signed-off-by: Chris Zhong --- Changes in v2: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi

[PATCH v2 0/4] RK3399 dw-mipi-dsi patches

Hi all This series set the phy_cfg_clk to be a required clock for RK3399, and add a grf clock control in dw-mipi-dsi driver. And then correct a register name. Changes in v2: - check the grf_clk only for RK3399 Chris Zhong (4): drm/rockchip/dsi: check phy_cfg_clk only for RK3399 dt-bindings

[PATCH v2 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match RK3399. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v2: None drivers/gpu/drm/rockc

[PATCH v2 2/4] dt-bindings: add the grf clock for dw-mipi-dsi

For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v2: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +- 1 file changed, 1 insertion

[PATCH v2 0/4] RK3399 dw-mipi-dsi patches

Hi all This series set the phy_cfg_clk to be a required clock for RK3399, and add a grf clock control in dw-mipi-dsi driver. And then correct a register name. Changes in v2: - check the grf_clk only for RK3399 Chris Zhong (4): drm/rockchip/dsi: check phy_cfg_clk only for RK3399 dt-bindings

[PATCH v2 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399

For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match RK3399. Signed-off-by: Chris Zhong --- Changes in v2: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10

[PATCH v2 2/4] dt-bindings: add the grf clock for dw-mipi-dsi

For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock. Signed-off-by: Chris Zhong --- Changes in v2: None .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

Re: [PATCH 1/3] dt-bindings: add the grf clock for dw-mipi-dsi

Hi Heiko On 03/15/2017 05:03 PM, Heiko Stübner wrote: Am Mittwoch, 15. März 2017, 16:42:30 CET schrieb Chris Zhong: For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- .../devi

Re: [PATCH 1/3] dt-bindings: add the grf clock for dw-mipi-dsi

Hi Heiko On 03/15/2017 05:03 PM, Heiko Stübner wrote: Am Mittwoch, 15. März 2017, 16:42:30 CET schrieb Chris Zhong: For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock. Signed-off-by: Chris Zhong --- .../devicetree/bindings/display

[PATCH 3/3] drm/rockchip/dsi: correct the grf_switch_reg name

For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20, not RK3399_GRF_SOC_CON19. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/d

[PATCH 2/3] drm/rockchip/dsi: enable the grf clk before writing grf registers

For RK3399, the grf clk should be enabled before writing grf registers, otherwise the register value can not be changed. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 24 1 file changed, 24 insertions(+) diff

[PATCH 1/3] dt-bindings: add the grf clock for dw-mipi-dsi

For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH 3/3] drm/rockchip/dsi: correct the grf_switch_reg name

For the RK3399, the grf_switch_reg name should be RK3399_GRF_SOC_CON20, not RK3399_GRF_SOC_CON19. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu

[PATCH 2/3] drm/rockchip/dsi: enable the grf clk before writing grf registers

For RK3399, the grf clk should be enabled before writing grf registers, otherwise the register value can not be changed. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 24 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/rockchip

[PATCH 1/3] dt-bindings: add the grf clock for dw-mipi-dsi

For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, add the description for this clock. Signed-off-by: Chris Zhong --- .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation

[PATCH v2 2/2] drm/panel: add innolux,p079zca panel driver

Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI panel. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v2: - add some error check - always use Low power mode to send commend - add comments for all the sleep - use DRM_DEV_ERROR instead of dev_er

[PATCH v2 1/2] dt-bindings: Add INNOLUX P079ZCA panel bindings

The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and connected to DSI using four lanes. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- Changes in v2: None .../bindings/display/panel/innolux,p079zca.txt | 23 ++ 1 file changed, 23

[PATCH v2 2/2] drm/panel: add innolux,p079zca panel driver

Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI panel. Signed-off-by: Chris Zhong --- Changes in v2: - add some error check - always use Low power mode to send commend - add comments for all the sleep - use DRM_DEV_ERROR instead of dev_err drivers/gpu/drm/panel/Kc

[PATCH v2 1/2] dt-bindings: Add INNOLUX P079ZCA panel bindings

The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and connected to DSI using four lanes. Signed-off-by: Chris Zhong --- Changes in v2: None .../bindings/display/panel/innolux,p079zca.txt | 23 ++ 1 file changed, 23 insertions(+) create mode 1

Re: [PATCH 3/4] phy: rockchip-typec: support DP phy switch

Hi Heiko and Brain On 03/09/2017 09:02 AM, Heiko Stübner wrote: Am Mittwoch, 8. März 2017, 16:39:23 CET schrieb Brian Norris: On Fri, Feb 10, 2017 at 03:44:13PM +0800, Chris Zhong wrote: There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence only one PHY can connect to DP

Re: [PATCH 3/4] phy: rockchip-typec: support DP phy switch

Hi Heiko and Brain On 03/09/2017 09:02 AM, Heiko Stübner wrote: Am Mittwoch, 8. März 2017, 16:39:23 CET schrieb Brian Norris: On Fri, Feb 10, 2017 at 03:44:13PM +0800, Chris Zhong wrote: There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence only one PHY can connect to DP

[PATCH 2/3] drm/rockchip: cdn-dp: Correct PHY register address

Correct some DP register address for PHY Configuration according to latest datasheet. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/cdn-dp-reg.h | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/cdn-dp

[PATCH 2/3] drm/rockchip: cdn-dp: Correct PHY register address

Correct some DP register address for PHY Configuration according to latest datasheet. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/cdn-dp-reg.h | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.h b/drivers/gpu/drm

Re: [PATCH 0/3] RK3399 cdd-dp patches

Oh, a slip of the finger :(, the headline should be "RK3399 cdn-dp patches" On 03/08/2017 10:27 AM, Chris Zhong wrote: Hi all This series is to correct some mistakes in clk_get_rate and the register address. And in order to better develop, adding more prints. Chris Zhong (3): dr

Re: [PATCH 0/3] RK3399 cdd-dp patches

Oh, a slip of the finger :(, the headline should be "RK3399 cdn-dp patches" On 03/08/2017 10:27 AM, Chris Zhong wrote: Hi all This series is to correct some mistakes in clk_get_rate and the register address. And in order to better develop, adding more prints. Chris Zhong (3): dr

[PATCH 3/3] drm/rockchip: cdn-dp: add more log for video config

In order to analyze some video config failed, add some useful printouts. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/cdn-dp-reg.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c b/drivers/gpu/drm/rockchip/

[PATCH 0/3] RK3399 cdd-dp patches

Hi all This series is to correct some mistakes in clk_get_rate and the register address. And in order to better develop, adding more prints. Chris Zhong (3): drm/rockchip: cdn-dp: return error code when clk_get_rate failed drm/rockchip: cdn-dp: Correct PHY register address drm/rockchip

[PATCH 3/3] drm/rockchip: cdn-dp: add more log for video config

In order to analyze some video config failed, add some useful printouts. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/cdn-dp-reg.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-reg.c b/drivers/gpu/drm/rockchip/cdn-dp-reg.c index 963d8ab

[PATCH 0/3] RK3399 cdd-dp patches

Hi all This series is to correct some mistakes in clk_get_rate and the register address. And in order to better develop, adding more prints. Chris Zhong (3): drm/rockchip: cdn-dp: return error code when clk_get_rate failed drm/rockchip: cdn-dp: Correct PHY register address drm/rockchip

[PATCH 1/3] drm/rockchip: cdn-dp: return error code when clk_get_rate failed

uot; instead of "u32" is better. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/rockchip/cdn-dp-core.c | 5 +++-- drivers/gpu/drm/rockchip/cdn-dp-reg.c | 2 +- drivers/gpu/drm/rockchip/cdn-dp-reg.h | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff

[PATCH 1/3] drm/rockchip: cdn-dp: return error code when clk_get_rate failed

uot; instead of "u32" is better. Signed-off-by: Chris Zhong --- drivers/gpu/drm/rockchip/cdn-dp-core.c | 5 +++-- drivers/gpu/drm/rockchip/cdn-dp-reg.c | 2 +- drivers/gpu/drm/rockchip/cdn-dp-reg.h | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/roc

[PATCH 2/2] drm/panel: add innolux,p079zca panel driver

Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI panel. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + drivers/gpu/drm/panel/panel-innolux-p079

[PATCH 2/2] drm/panel: add innolux,p079zca panel driver

Support Innolux P079ZCA 7.85" 768x1024 TFT LCD panel, it is a MIPI DSI panel. Signed-off-by: Chris Zhong --- drivers/gpu/drm/panel/Kconfig | 11 + drivers/gpu/drm/panel/Makefile| 1 + drivers/gpu/drm/panel/panel-innolux-p079zca.c

[PATCH 1/2] dt-bindings: Add INNOLUX P079ZCA panel bindings

The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and connected to DSI using four lanes. Signed-off-by: Chris Zhong <z...@rock-chips.com> --- .../bindings/display/panel/innolux,p079zca.txt | 22 ++ 1 file changed, 22 insertions(+) create

[PATCH 1/2] dt-bindings: Add INNOLUX P079ZCA panel bindings

The Innolux P079ZCA is a 7.85" panel with a 768X1024 resolution and connected to DSI using four lanes. Signed-off-by: Chris Zhong --- .../bindings/display/panel/innolux,p079zca.txt | 22 ++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devic

Re: [PATCH v4 00/23] drm/rockchip: MIPI fixes & improvements

Hi John I have test this v4 series on my RK3399 board, it works well, thanks. Tested-by: Chris Zhong<z...@rock-chips.com> On 02/24/2017 08:54 PM, John Keeping wrote: This version is mostly small changes in response to review comments from Sean and Chris, the details are in the indi

Re: [PATCH v4 00/23] drm/rockchip: MIPI fixes & improvements

Hi John I have test this v4 series on my RK3399 board, it works well, thanks. Tested-by: Chris Zhong On 02/24/2017 08:54 PM, John Keeping wrote: This version is mostly small changes in response to review comments from Sean and Chris, the details are in the individual patches. I decided

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