On Sat, 2021-04-17 at 10:52 +0200, Hans de Goede wrote:
> Hi David,
>
> On 4/17/21 5:12 AM, David E. Box wrote:
> > From: Gayatri Kammela
> >
> > Platforms that support low power modes (LPM) such as Tiger Lake
> > maintain
> > requirements for ea
On Sat, 2021-04-17 at 11:00 +0200, Hans de Goede wrote:
> Hi,
>
> On 4/17/21 5:12 AM, David E. Box wrote:
> > From: Gayatri Kammela
> >
> > Platforms that support low power modes (LPM) such as Tiger Lake
> > maintain
> > requirements for each sub-state
the global pmc_dev in favor of one that is allocated during probe.
Modify users of the global to obtain the object by argument instead.
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
Reviewed-by: Rajneesh Bhardwaj
---
V2: No change
drivers/platform/x86/intel_pmc_core.c | 41
howing all possible ones. After this
patch, the debugfs file looks like this:
Substate Residency
S0i2.0 0
S0i3.0 0
S0i2.1 9329279
S0i3.1 0
S0i3.2 0
Suggested-by: David E. Box
Signed-off-by: Gayatri Kammela
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
Acked-by
. Clearing the status
registers before testing removes ambiguity around when the current values
were set.
The new file, latch_lpm_mode, looks like this:
[c10] S0i2.0 S0i3.0 S0i2.1 S0i3.1 S0i3.2 clear
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
---
V2: - Rebase on Tamar
the requirements for Tiger Lake using
the _DSM method and store in a buffer.
Signed-off-by: Gayatri Kammela
Co-developed-by: David E. Box
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
---
V2: - Move buffer allocation so that it does not need to be freed
(which was missing anyway) when
| | Required | | Required |
Required | |
Signed-off-by: Gayatri Kammela
Co-developed-by: David E. Box
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
---
V2: No change
drivers/platform/x86/intel_pmc_core.c | 86 +++
1 file changed
Alder PCH-P is based on Tiger Lake PCH.
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
Acked-by: Rajneesh Bhardwaj
---
V2: No change
drivers/platform/x86/intel_pmc_core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers
-by: Gayatri Kammela
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
Acked-by: Rajneesh Bhardwaj
---
V2: No change
drivers/platform/x86/intel_pmc_core.c | 2 ++
drivers/platform/x86/intel_pmc_core.h | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/platform
-by: Gayatri Kammela
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
Reviewed-by: Rajneesh Bhardwaj
---
V2: No change
drivers/platform/x86/intel_pmc_core.c | 14 --
drivers/platform/x86/intel_pmc_core.h | 3 +++
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git
condition is met. This allows removing the global pmc_dev later.
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
Reviewed-by: Rajneesh Bhardwaj
---
V2: No change
drivers/platform/x86/intel_pmc_core.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git
- Patch 9 adds support for ADL-P which is based on TGL
Applied on top of latest hans-review/review-hans
Patches that changed in V2:
Patch 3: Variable name change
Patch 5: Do proper cleanup after fail
Patch 7: Debugfs write function fixes
David E. Box (4):
platform/x86
On Wed, 2021-04-07 at 11:45 -0400, Rajneesh Bhardwaj wrote:
> On Wed, Mar 31, 2021 at 11:06 PM David E. Box
> wrote:
> >
> > From: Gayatri Kammela
> >
> > Add the debugfs file, substate_requirements, to view the low power
> > mode
> > (LPM) requirement
Hi Hans.
Ack on your comments for this series. Questions answered below.
On Wed, 2021-04-07 at 16:37 +0200, Hans de Goede wrote:
> Hi,
>
> On 4/1/21 5:05 AM, David E. Box wrote:
> > By default the Low Power Mode (LPM or sub-state) status registers
> > will
> > latc
7
> > > > > +++++++++++
> > > > > drivers/platform/x86/intel_pmc_core.h | 6 ++
> > > > > 4 files changed, 115 insertions(+)
> > > > > create mode 100644
> > > > > Documentation/ABI/testing/sysfs-pla
ce you're adding the same new register
as I am.
>
> Documentation/ABI/testing/sysfs-platform-intel-pmc
>
> File ?
>
> Regards,
>
> Hans
>
>
>
> >
> > The register in MMIO space is defined for Cannon Lake and newer PCHs.
> >
> > C
Hi Tomas,
I have a patch set that also adds the ETR3 register, although for an
entirely different purpose. It doesn't touch the same bits. But your
patch can be taken as is. I'll rebase on top of this one. Thanks.
Reviewed-by: David E Box
On Fri, 2021-04-02 at 18:21 +0300, Tomas Winkler wrote
-by: Gayatri Kammela
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 14 --
drivers/platform/x86/intel_pmc_core.h | 3 +++
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/platform/x86/intel_pmc_core.c
the requirements for Tiger Lake using
the _DSM method and store in a buffer.
Signed-off-by: Gayatri Kammela
Co-developed-by: David E. Box
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 49 +++
drivers/platform/x86/intel_pmc_core.h | 2 ++
2 files changed, 51
- Patch 9 adds support for ADL-P which is based on TGL
Applied on top of latest 5.12-rc2 based hans-review/review-hans
David E. Box (4):
platform/x86: intel_pmc_core: Don't use global pmcdev in quirks
platform/x86: intel_pmc_core: Remove global struct pmc_dev
platform/x86: intel_pmc_core: Add
howing all possible ones. After this
patch, the debugfs file looks like this:
Substate Residency
S0i2.0 0
S0i3.0 0
S0i2.1 9329279
S0i3.1 0
S0i3.2 0
Suggested-by: David E. Box
Signed-off-by: Gayatri Kammela
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_c
-by: Gayatri Kammela
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 2 ++
drivers/platform/x86/intel_pmc_core.h | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/platform/x86/intel_pmc_core.c
index
. Clearing the status
registers before testing removes ambiguity around when the current values
were set.
The new file, latch_lpm_mode, looks like this:
[c10] S0i2.0 S0i3.0 S0i2.1 S0i3.1 S0i3.2 clear
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 94
Alder PCH-P is based on Tiger Lake PCH.
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/platform/x86/intel_pmc_core.c
index 9168062c927e..88d582df829f 100644
--- a/drivers
condition is met. This allows removing the global pmc_dev later.
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/platform/x86/intel_pmc_core.c
the global pmc_dev in favor of one that is allocated during probe.
Modify users of the global to obtain the object by argument instead.
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 41 ++-
1 file changed, 21 insertions(+), 20 deletions(-)
diff
| | Required | | Required |
Required | |
Signed-off-by: Gayatri Kammela
Co-developed-by: David E. Box
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 86 +++
1 file changed, 86 insertions(+)
diff --git a/drivers/platform
On Tue, 2021-03-16 at 19:44 -0700, David E. Box wrote:
> Initialize the struct resource in intel_pmt_dev_register to zero to
> avoid a
> fault should the char *name field be non-zero.
Hi Hans. Can these 2 patches be pulled as fixes for 5.12? Thanks.
David
>
> Signed-off-b
Fixes off-by-one bugs in the macro assignments for the crashlog control
bits. Was initially tested on emulation but bug revealed after testing on
silicon.
Fixes: 5ef9998c96b0 ("platform/x86: Intel PMT Crashlog capability driver")
Signed-off-by: David E. Box
---
drivers/pl
Initialize the struct resource in intel_pmt_dev_register to zero to avoid a
fault should the char *name field be non-zero.
Signed-off-by: David E. Box
---
Base commit is v5.12-rc3.
drivers/platform/x86/intel_pmt_class.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
capabilities
are found.
Fixes: 4f8217d5b0ca ("mfd: Intel Platform Monitoring Technology support")
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
---
No change from V2
drivers/mfd/intel_pmt.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/d
-by: David E. Box
---
Changes from V2:
- Use declared variable
Changes from V1:
- New patch
drivers/mfd/intel_pmt.c| 101 +++--
drivers/platform/x86/intel_pmt_class.c | 46 ++
drivers/platform/x86/intel_pmt_class.h | 1 +
drivers
On Tue, 2021-03-09 at 16:45 +, Lee Jones wrote:
> On Wed, 24 Feb 2021, David E. Box wrote:
>
> > Adds PMT Telemetry aggregator support for the DG1 graphics PCIe
> > card. The
> > device does not have the DVSEC region in its PCI config space so
> > hard
>
On Mon, 2021-03-08 at 18:02 +, Limonciello, Mario wrote:
>
>
> > -Original Message-
> > From: Rajneesh Bhardwaj
> > Sent: Monday, March 8, 2021 11:32
> > To: Limonciello, Mario
> > Cc: David E. Box; hdego...@redhat.com; mgr...@linux.intel.com;
Hi Rajneesh,
On Mon, 2021-03-08 at 09:04 -0500, Rajneesh Bhardwaj wrote:
> Hi David
>
> Overall, it looks like the right thing to do but i have a few
> comments. See below.
>
> On Fri, Mar 5, 2021 at 2:07 PM David E. Box <
> david.e@linux.intel.com> wrote:
>
Hi Sasha,
On Sun, 2021-03-07 at 10:39 +0200, Neftin, Sasha wrote:
> On 3/5/2021 21:06, David E. Box wrote:
> > Due to a HW limitation, the Latency Tolerance Reporting (LTR) value
> > programmed in the Tiger Lake GBE controller is not large enough to
> > allow
> > the pl
on Tiger Lake. LTR ignore functionality is currently performed solely
by a debugfs write call. Split out the LTR code into its own function that
can be called by both the debugfs writer and by this work around.
Signed-off-by: David E. Box
Reviewed-by: Sasha Neftin
Cc: intel-wired
On Wed, 2021-02-24 at 21:22 +0100, Hans de Goede wrote:
> Hi,
>
> On 2/24/21 9:10 PM, David E. Box wrote:
> > Some products will be available that have PMT capabilities that are
> > not
> > supported. Remove the warnings in this instance to avoid nuisance
>
capabilities
are found.
Fixes: 4f8217d5b0ca ("mfd: Intel Platform Monitoring Technology support")
Signed-off-by: David E. Box
Reviewed-by: Hans de Goede
---
For merge in platform-drivers-x86
Based on 5.11-rc1 review-hans branch:
https://git.kernel.org/pub/scm/linux/kernel/git/pdx8
-by: David E. Box
---
Based on 5.11-rc1 review-hans branch:
https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git/log/?h=review-hans
Changes from V1:
- New patch
drivers/mfd/intel_pmt.c| 101 +++--
drivers/platform/x86
capabilities
are found.
Fixes: 4f8217d5b0ca ("mfd: Intel Platform Monitoring Technology support")
Signed-off-by: David E. Box
---
drivers/mfd/intel_pmt.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/mfd/intel_pmt.c b/drivers/mfd/intel_p
All devices that expose Intel Platform Monitoring Technology (PMT)
crashlog are currently owned by the intel_pmt MFD driver. Therefore make
the crashlog driver depend on the MFD driver for build.
Fixes: 5ef9998c96b0 ("platform/x86: Intel PMT Crashlog capability driver")
Signed-off-b
All devices that expose Intel Platform Monitoring Technology (PMT)
telemetry are currently owned by the intel_pmt MFD driver. Therefore make
the telemetry driver depend on the MFD driver for build.
Fixes: 68fe8e6e2c4b ("platform/x86: Intel PMT Telemetry capability driver")
Signed-off-b
Fix error in Kconfig that exposed INTEL_PMT_CLASS as a user selectable
option. It is already selected by INTEL_PMT_TELEMETRY and
INTEL_PMT_CRASHLOG which are user selectable.
Fixes: e2729113ce66 ("platform/x86: Intel PMT class driver")
Signed-off-by: David E. Box
---
drivers/pl
ar
>
> On 12/9/2020 3:36 AM, David E. Box wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Intel systems that support ACPI Low Power Idle it has been
> > observed
> > that the L1 Substate capability can return disabled afte
-off-by: David E. Box
---
drivers/pci/pci.c | 49 +++
1 file changed, 49 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e578d34095e9..beee3d9952a6 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1539,6 +1539,48 @@ static
-by: Len Brown
Suggested-by: Rafael J. Wysocki
Signed-off-by: David E. Box
---
Changes from V1:
- Add pci_disable_ptm() to ptm.c
- Move ptm disabling from pci_save_ptm_state() to
pci_prepare_to_sleep() and pci_finish_runtime_suspend() as
suggested by Rafael
of
the PTM control register. This saves the PTM Enable, Root Select, and
Effective Granularity bits.
Suggested-by: Rafael J. Wysocki
Signed-off-by: David E. Box
---
Changes from V1:
- Move save/restore functions to ptm.c
- Move pci_add_ext_cap_sve_buffer() to pci_ptm_init in ptm.c
On Thu, 2020-11-19 at 19:13 +0100, Rafael J. Wysocki wrote:
> On Thu, Nov 19, 2020 at 6:45 PM David E. Box
> wrote:
> > On Thu, 2020-11-19 at 13:01 +0100, Rafael J. Wysocki wrote:
> > > On Thu, Nov 19, 2020 at 1:17 AM Davi
On Thu, 2020-11-19 at 13:01 +0100, Rafael J. Wysocki wrote:
> On Thu, Nov 19, 2020 at 1:17 AM David E. Box
> wrote:
> > On Intel client platforms that support suspend-to-idle, like Ice
> > Lake,
> > root ports that have Precision Time Management (PTM) enabled can
>
. This saves the PTM Enable, Root Select, and Effective Granularity
bits.
Suggested-by: Rafael J. Wysocki
Signed-off-by: David E. Box
---
drivers/pci/pci.c | 44
1 file changed, 44 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
the feature. The feature will be returned to its previous state
during restore.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=209361
Reported-by: Len Brown
Suggested-by: Rafael J. Wysocki
Signed-off-by: David E. Box
---
drivers/pci/pci.c | 14 +-
1 file changed, 13
> > > > On Wed, Oct 7, 2020 at 6:49 PM David E. Box <
> > > > david.e@linux.intel.com> wrote:
> > > > > On Intel Platform Controller Hubs (PCH) since Cannon Lake,
> > > > > the Precision
> > > > > Time Measurement (PTM)
Hi Geert,
On Tue, 2020-11-10 at 11:39 +0100, Geert Uytterhoeven wrote:
> Hi David,
>
> On Sat, Oct 3, 2020 at 3:32 AM David E. Box <
> david.e@linux.intel.com> wrote:
> > Intel Platform Monitoring Technology (PMT) is an architecture for
> > enumerating and
Hi Lee,
On Thu, 2020-10-29 at 15:16 +, Lee Jones wrote:
...
> > Changes from V8:
> > - Rebase on 5.10-rc1
> > - Add missing changes in MFD patch from V7 that were
> > accidentally
> > dropped in V8
>
> Which changes are those?
>
> Do I need to re-review?
Should have
On Tue, 2020-10-27 at 12:28 +0100, Hans de Goede wrote:
> Hi,
>
> On 10/3/20 3:31 AM, David E. Box wrote:
> > Intel Platform Monitoring Technology (PMT) is an architecture for
> > enumerating and accessing hardware monitoring capabilities on a
> > device.
> > W
ring fixes
Alexander Duyck (3):
platform/x86: Intel PMT class driver
platform/x86: Intel PMT Telemetry capability driver
platform/x86: Intel PMT Crashlog capability driver
David E. Box (2):
PCI: Add defines for Designated Vendor-Specific Extended Capability
mfd: Intel Platform
Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and defines
for the header offsets. Defined in PCIe r5.0, sec 7.9.6.
Signed-off-by: David E. Box
Acked-by: Bjorn Helgaas
Reviewed-by: Andy Shevchenko
---
Changes from V8:
- None
include/uapi/linux/pci_regs.h | 5
:
https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=209361
Tested-by: Len Brown
Signed-off-by: David E. Box
---
drivers/pci/quirks.c | 57
1 file changed, 57 insertions
On Wed, 2020-10-07 at 07:57 +0100, Lee Jones wrote:
> On Fri, 02 Oct 2020, David E. Box wrote:
>
> > Intel Platform Monitoring Technology (PMT) is an architecture for
> > enumerating and accessing hardware monitoring facilities. PMT
> > supports
> > multiple ty
m/x86: intel_pmc_core: Add an
additional parameter to pmc_core_lpm_display()")
Cc: Srinivas Pandruvada
Cc: Andy Shevchenko
Cc: David E. Box
Signed-off-by: Gayatri Kammela
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 6 +++---
1 file changed, 3 insertions(+), 3
From: Gayatri Kammela
Add RocketLake to the list of the platforms that intel_pmc_core driver
supports for pmc_core device. RocketLake reuses all the TigerLake PCH IPs.
Cc: Srinivas Pandruvada
Cc: Andy Shevchenko
Cc: David E. Box
Cc: Tony Luck
Cc: Rui Zhang
Signed-off-by: Gayatri Kammela
(cnp_pfear_map).
Hence, remove the duplicate comments and reorganize them.
Cc: Srinivas Pandruvada
Cc: Andy Shevchenko
Cc: David E. Box
Cc: Tony Luck
Cc: Rui Zhang
Suggested-by: Dave Hansen
Signed-off-by: Gayatri Kammela
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c
Add RocketLake platform support and other driver maintainance.
Gayatri Kammela (4):
platform/x86: intel_pmc_core: Clean up: Remove the duplicate comments
and reorganize
platform/x86: intel_pmc_core: Add Intel RocketLake (RKL) support
platform/x86: intel_pmc_core: fix: Replace dev_dbg
From: Gayatri Kammela
Update MAINTAINERS file for pmc_core driver to reflect the current
maintainers.
Cc: Vishwanath Somayaji
Cc: Andy Shevchenko
Cc: Srinivas Pandruvada
Cc: David E. Box
Acked-by: David E. Box
Acked-by: Vishwanath Somayaji
Signed-off-by: Gayatri Kammela
Signed-off
On Tue, 2020-10-06 at 19:51 -0500, Bjorn Helgaas wrote:
> On Tue, Oct 06, 2020 at 03:45:54PM -0700, David E. Box wrote:
> > Hi Bjorn,
> >
> > This patch has been acked and unchanged for weeks. Is it possible
> > to
> > get this pulled into next?
TigerLake Lower Power Mode (LPM) registers are grouped by functionality
but were given simple enumerated names in the code (lpm0, lpm1, ...).
Instead, give the register blocks names that describe their usage.
Suggested-by: Andy Shevchenko
Signed-off-by: David E. Box
---
drivers/platform/x86
.
Hence, specify granularity of the tick for each platform, so that the
value of the slp_s0 counter is accurate.
Signed-off-by: Gayatri Kammela
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 10 +++---
drivers/platform/x86/intel_pmc_core.h | 5 -
2 files changed
.
Cc: Srinivas Pandruvada
Cc: Andy Shevchenko
Cc: David E. Box
Signed-off-by: Gayatri Kammela
Signed-off-by: David E. Box
---
drivers/platform/x86/intel_pmc_core.c | 48 +--
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/platform/x86
gating status register for TigerLake.
Patch 3: Fixes the slps0 residency multiplier to use the correct, platform
specific values.
David E. Box (1):
platform/x86: pmc_core: Use descriptive names for LPM registers
Gayatri Kammela (2):
platform/x86: intel_pmc_core: Fix TigerLake
Hi Bjorn,
This patch has been acked and unchanged for weeks. Is it possible to
get this pulled into next? We have SIOV and CXL related work that is
using these definitions. Thanks.
David
On Fri, 2020-10-02 at 18:31 -0700, David E. Box wrote:
> Add PCIe Designated Vendor-Specific Exten
From: Alexander Duyck
Add support for the Intel Platform Monitoring Technology crashlog
interface. This interface provides a few sysfs values to allow for
controlling the crashlog telemetry interface as well as a character
driver to allow for mapping the crashlog memory region so that it can be
ssues.
Co-developed-by: David E. Box
Signed-off-by: David E. Box
Signed-off-by: Alexander Duyck
---
drivers/platform/x86/Kconfig | 11 ++
drivers/platform/x86/Makefile | 1 +
drivers/platform/x86/intel_pmt_telemetry.c | 160 +
3 files changed, 172
Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and defines
for the header offsets. Defined in PCIe r5.0, sec 7.9.6.
Signed-off-by: David E. Box
Acked-by: Bjorn Helgaas
Reviewed-by: Andy Shevchenko
---
include/uapi/linux/pci_regs.h | 5 +
1 file changed, 5 insertions
region in bytes that corresponds to
+ the mapping for the telem file.
diff --git a/MAINTAINERS b/MAINTAINERS
index 0f2663b1d376..47fdb8a6e151 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8950,6 +8950,7 @@ INTEL PMT DRIVER
M: "David E. Box"
S: Maintained
F: d
, spelling, and Makefile/MAINTAINERS ordering fixes
Alexander Duyck (3):
platform/x86: Intel PMT class driver
platform/x86: Intel PMT Telemetry capability driver
platform/x86: Intel PMT Crashlog capability driver
David E. Box (2):
PCI: Add defines for Designated Vendor-Specific Extended Capabi
a quirk to fix the discovery table offset.
Co-developed-by: Alexander Duyck
Signed-off-by: Alexander Duyck
Signed-off-by: David E. Box
Reviewed-by: Andy Shevchenko
---
MAINTAINERS | 5 +
drivers/mfd/Kconfig | 10 ++
drivers/mfd/Makefile| 1 +
drivers/mfd/intel_pmt.c
region in bytes that corresponds to
+ the mapping for the telem file.
diff --git a/MAINTAINERS b/MAINTAINERS
index 0f2663b1d376..47fdb8a6e151 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8950,6 +8950,7 @@ INTEL PMT DRIVER
M: "David E. Box"
S: Maintained
F: d
can be populated with
telem devices. These devices will contain the standard intel_pmt sysfs
data and a "telem" binary sysfs attribute which can be used to access the
telemetry data.
Co-developed-by: David E. Box
Signed-off-by: David E. Box
Signed-off-by: Alexander Duyck
---
driver
Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and defines
for the header offsets. Defined in PCIe r5.0, sec 7.9.6.
Signed-off-by: David E. Box
Acked-by: Bjorn Helgaas
Reviewed-by: Andy Shevchenko
---
include/uapi/linux/pci_regs.h | 5 +
1 file changed, 5 insertions
ring fixes
Alexander Duyck (3):
platform/x86: Intel PMT class driver
platform/x86: Intel PMT Telemetry capability driver
platform/x86: Intel PMT Crashlog capability driver
David E. Box (2):
PCI: Add defines for Designated Vendor-Specific Extended Capability
mfd: Intel Platform Monitoring
From: Alexander Duyck
Add support for the Intel Platform Monitoring Technology crashlog
interface. This interface provides a few sysfs values to allow for
controlling the crashlog telemetry interface as well as a character driver
to allow for mapping the crashlog memory region so that it can be
the discovery table offset.
Co-developed-by: Alexander Duyck
Signed-off-by: Alexander Duyck
Signed-off-by: David E. Box
Reviewed-by: Andy Shevchenko
---
MAINTAINERS | 5 +
drivers/mfd/Kconfig | 10 ++
drivers/mfd/Makefile| 1 +
drivers/mfd/intel_pmt.c | 225
On Wed, 2020-09-30 at 08:12 +0100, Lee Jones wrote:
> On Tue, 29 Sep 2020, David E. Box wrote:
>
> > On Tue, 2020-09-29 at 10:51 +0100, Lee Jones wrote:
> > > On Fri, 11 Sep 2020, David E. Box wrote:
> > >
> > > > Add Out of Band Management Serv
On Tue, 2020-09-29 at 10:51 +0100, Lee Jones wrote:
> On Fri, 11 Sep 2020, David E. Box wrote:
>
> > Add Out of Band Management Services Module device ID to Intel PMT
> > driver.
> >
> > Signed-off-by: Alexander Duyck
> > Signed-off-by: David E. Box
>
the discovery table offset.
Co-developed-by: Alexander Duyck
Signed-off-by: Alexander Duyck
Signed-off-by: David E. Box
Reviewed-by: Andy Shevchenko
---
MAINTAINERS | 5 +
drivers/mfd/Kconfig | 10 ++
drivers/mfd/Makefile| 1 +
drivers/mfd/intel_pmt.c | 226
region in bytes that corresponds to
+ the mapping for the telem file.
diff --git a/MAINTAINERS b/MAINTAINERS
index 0f2663b1d376..47fdb8a6e151 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8950,6 +8950,7 @@ INTEL PMT DRIVER
M: "David E. Box"
S: Maintained
F: d
Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and defines
for the header offsets. Defined in PCIe r5.0, sec 7.9.6.
Signed-off-by: David E. Box
Acked-by: Bjorn Helgaas
Reviewed-by: Andy Shevchenko
---
include/uapi/linux/pci_regs.h | 5 +
1 file changed, 5 insertions
can be populated with
telem devices. These devices will contain the standard intel_pmt sysfs
data and a "telem" binary sysfs attribute which can be used to access the
telemetry data.
Co-developed-by: David E. Box
Signed-off-by: David E. Box
Signed-off-by: Alexander Duyck
---
driver
From: Alexander Duyck
Add support for the Intel Platform Monitoring Technology crashlog
interface. This interface provides a few sysfs values to allow for
controlling the crashlog telemetry interface as well as a character
driver to allow for mapping the crashlog memory region so that it can be
x86: Intel PMT class driver
platform/x86: Intel PMT Telemetry capability driver
platform/x86: Intel PMT Crashlog capability driver
David E. Box (2):
PCI: Add defines for Designated Vendor-Specific Extended Capability
mfd: Intel Platform Monitoring Technology support
.../ABI/testing/s
be accessed
after a crashlog has been recorded.
This driver is meant to only support the server version of the crashlog
which is identified as crash_type 1 with a version of zero. Currently no
other types are supported.
Signed-off-by: Alexander Duyck
Signed-off-by: David E. Box
---
.../ABI
Add Out of Band Management Services Module device ID to Intel PMT driver.
Signed-off-by: Alexander Duyck
Signed-off-by: David E. Box
---
drivers/mfd/intel_pmt.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mfd/intel_pmt.c b/drivers/mfd/intel_pmt.c
index 0e572b105101
://lore.kernel.org/lkml/20200819180255.11770-1-david.e@linux.intel.com/
Alexander Duyck (1):
platform/x86: Intel PMT Crashlog capability driver
David E. Box (2):
mfd: intel_pmt: Add OOBMSM device ID
mfd: intel_pmt: Add Alder Lake (ADL) support
.../ABI/testing/sysfs-class-pmt_crashlog | 66
Add PMT support for Alder Lake (ADL). Use same quirks as Tiger Lake since
the design is the same, meaning no support for Watcher or Crashlog.
Signed-off-by: David E. Box
---
drivers/mfd/intel_pmt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mfd/intel_pmt.c b/drivers/mfd
name
- Move monitor device name defines to common header
- Coding style, spelling, and Makefile/MAINTAINERS ordering fixes
David E. Box (3):
PCI: Add defines for Designated Vendor-Specific Extended Capability
mfd: Intel Platform Monitoring Technology support
platform/x86: Intel
Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and defines
for the header offsets. Defined in PCIe r5.0, sec 7.9.6.
Signed-off-by: David E. Box
Acked-by: Bjorn Helgaas
Reviewed-by: Andy Shevchenko
---
include/uapi/linux/pci_regs.h | 5 +
1 file changed, 5 insertions
--git a/MAINTAINERS b/MAINTAINERS
index f0569cf304ca..b69429c70330 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8845,6 +8845,11 @@ F: drivers/mfd/intel_soc_pmic*
F: include/linux/mfd/intel_msic.h
F: include/linux/mfd/intel_soc_pmic*
+INTEL PMT DRIVER
+M: "David E. Box
issues.
Co-developed-by: Alexander Duyck
Signed-off-by: Alexander Duyck
Signed-off-by: David E. Box
Reviewed-by: Andy Shevchenko
---
.../ABI/testing/sysfs-class-pmt_telemetry | 46 ++
MAINTAINERS | 1 +
drivers/platform/x86/Kconfig | 10
On Tue, 2020-08-11 at 09:04 +0100, Lee Jones wrote:
> On Mon, 10 Aug 2020, David E. Box wrote:
>
> > Friendly ping.
>
> Don't do that. Sending contentless pings is seldom helpful.
>
> If you think your set has been dropped please just send a [RESEND].
>
> This
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