On Nov 3, 2015, at 3:03 PM, Helge Deller wrote:
> Sadly it's nowhere clearly documented how big the L1 cacheline of parisc
> really is.
To which particular PA-RISC processor are you referring? It might not be the
same on all processors.
If openpa.net is to be believed, then:
The 7100LC has
On Nov 3, 2015, at 3:43 PM, Guy Harris wrote:
> To which particular PA-RISC processor are you referring? It might not be the
> same on all processors.
Chapter 3 "Addressing and Access Control" of PA-RISC 2.0 Architecture:
http://h21007.www2.hp.com/portal/downl
On Feb 5, 2015, at 12:01 PM, Willem de Bruijn wrote:
> On Wed, Feb 4, 2015 at 9:58 PM, Alexander Drozdov
> wrote:
>> Don't close an empty block on timeout. Its meaningless to
>> pass it to the user. Moreover, passing empty blocks wastes
>> CPU & buffer space increasing probability of packets
>
On Dec 22, 2014, at 12:41 PM, David Miller wrote:
> From: Dan Collins
> Date: Fri, 19 Dec 2014 16:49:25 +1300
>
>> Make TPACKET_V3 signal poll when block is closed rather than for every
>> packet. Side effect is that poll will be signaled when block retire
>> timer expires which didn't previou
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