ative form: "Fix the code arm64" rather than "This
fixes the code on arm64"
Other than that LGTM.
Reviewed-by: Thomas Hellström (Intel)
Signed-off-by: Zack Rusin
Cc: Andrew Morton
Cc: Thomas Hellström (Intel)
Cc: linux...@kvack.org
Cc: linux-kernel@vger.kernel.org
---
On 3/26/21 12:46 PM, Jason Gunthorpe wrote:
On Fri, Mar 26, 2021 at 10:08:09AM +0100, Thomas Hellström (Intel) wrote:
On 3/25/21 7:24 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 07:13:33PM +0100, Thomas Hellström (Intel) wrote:
On 3/25/21 6:55 PM, Jason Gunthorpe wrote:
On Thu, Mar
On 3/25/21 7:24 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 07:13:33PM +0100, Thomas Hellström (Intel) wrote:
On 3/25/21 6:55 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 06:51:26PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 9:25 PM, Dave Hansen wrote:
On 3/24/21 1:22
On 3/25/21 7:24 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 07:13:33PM +0100, Thomas Hellström (Intel) wrote:
On 3/25/21 6:55 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 06:51:26PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 9:25 PM, Dave Hansen wrote:
On 3/24/21 1:22
On 3/25/21 6:55 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 06:51:26PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 9:25 PM, Dave Hansen wrote:
On 3/24/21 1:22 PM, Thomas Hellström (Intel) wrote:
We also have not been careful at *all* about how _PAGE_BIT_SOFTW* are
used. It&#
On 3/24/21 9:25 PM, Dave Hansen wrote:
On 3/24/21 1:22 PM, Thomas Hellström (Intel) wrote:
We also have not been careful at *all* about how _PAGE_BIT_SOFTW* are
used. It's quite possible we can encode another use even in the
existing bits.
Personally, I'd just try:
#define _PAGE_
Hi,
On 3/25/21 2:02 PM, Christian König wrote:
Am 25.03.21 um 13:36 schrieb Thomas Hellström (Intel):
On 3/25/21 1:09 PM, Christian König wrote:
Am 25.03.21 um 13:01 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 12:53:15PM +0100, Thomas Hellström (Intel)
wrote:
Nope. The point here
On 3/25/21 1:09 PM, Christian König wrote:
Am 25.03.21 um 13:01 schrieb Jason Gunthorpe:
On Thu, Mar 25, 2021 at 12:53:15PM +0100, Thomas Hellström (Intel)
wrote:
Nope. The point here was that in this case, to make sure mmap uses the
correct VA to give us a reasonable chance of alignement
On 3/25/21 12:30 PM, Jason Gunthorpe wrote:
On Thu, Mar 25, 2021 at 10:51:35AM +0100, Thomas Hellström (Intel) wrote:
Please explain that further. Why do we need the mmap lock to insert PMDs
but not when insert PTEs?
We don't. But once you've inserted a PMD directory you can&#
On 3/25/21 9:27 AM, Christian König wrote:
Am 25.03.21 um 08:48 schrieb Thomas Hellström (Intel):
On 3/25/21 12:14 AM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 09:07:53PM +0100, Thomas Hellström (Intel)
wrote:
On 3/24/21 7:31 PM, Christian König wrote:
Am 24.03.21 um 17:38 schrieb
On 3/25/21 12:14 AM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 09:07:53PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 7:31 PM, Christian König wrote:
Am 24.03.21 um 17:38 schrieb Jason Gunthorpe:
On Wed, Mar 24, 2021 at 04:50:14PM +0100, Thomas Hellström (Intel)
wrote:
On 3/24
On 3/24/21 5:34 PM, Dave Hansen wrote:
On 3/24/21 3:05 AM, Thomas Hellström (Intel) wrote:
Yes, I agree. Seems like the special (SW1) is available also for huge
page table entries on x86 AFAICT, although just not implemented.
Otherwise the SW bits appear completely used up.
Although the
On 3/24/21 7:31 PM, Christian König wrote:
Am 24.03.21 um 17:38 schrieb Jason Gunthorpe:
On Wed, Mar 24, 2021 at 04:50:14PM +0100, Thomas Hellström (Intel)
wrote:
On 3/24/21 2:48 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 02:35:38PM +0100, Thomas Hellström (Intel)
wrote:
In an
On 3/24/21 2:48 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 02:35:38PM +0100, Thomas Hellström (Intel) wrote:
In an ideal world the creation/destruction of page table levels would
by dynamic at this point, like THP.
Hmm, but I'm not sure what problem we're trying to solve b
On 3/24/21 1:41 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 01:35:17PM +0100, Thomas Hellström (Intel) wrote:
On 3/24/21 1:24 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 10:56:43AM +0100, Daniel Vetter wrote:
On Tue, Mar 23, 2021 at 06:06:53PM +0100, Thomas Hellström (Intel
On 3/24/21 1:24 PM, Jason Gunthorpe wrote:
On Wed, Mar 24, 2021 at 10:56:43AM +0100, Daniel Vetter wrote:
On Tue, Mar 23, 2021 at 06:06:53PM +0100, Thomas Hellström (Intel) wrote:
On 3/23/21 5:37 PM, Jason Gunthorpe wrote:
On Tue, Mar 23, 2021 at 05:34:51PM +0100, Thomas Hellström (Intel
On 3/24/21 10:58 AM, Daniel Vetter wrote:
On Tue, Mar 23, 2021 at 09:42:18PM +0100, Thomas Hellström (Intel) wrote:
On 3/23/21 8:52 PM, Williams, Dan J wrote:
On Sun, 2021-03-21 at 19:45 +0100, Thomas Hellström (Intel) wrote:
TTM sets up huge page-table-entries both to system- and device
On 3/23/21 8:52 PM, Williams, Dan J wrote:
On Sun, 2021-03-21 at 19:45 +0100, Thomas Hellström (Intel) wrote:
TTM sets up huge page-table-entries both to system- and device
memory,
and we don't want gup to assume there are always valid backing struct
pages for these. For PTEs this is ha
On 3/23/21 5:37 PM, Jason Gunthorpe wrote:
On Tue, Mar 23, 2021 at 05:34:51PM +0100, Thomas Hellström (Intel) wrote:
@@ -210,6 +211,20 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault
*vmf,
if ((pfn & (fault_page_size - 1)) != 0)
goto out_fall
Hi,
On 3/23/21 12:34 PM, Daniel Vetter wrote:
On Sun, Mar 21, 2021 at 07:45:28PM +0100, Thomas Hellström (Intel) wrote:
TTM sets up huge page-table-entries both to system- and device memory,
and we don't want gup to assume there are always valid backing struct
pages for these. For PTEs th
On 3/23/21 3:04 PM, Jason Gunthorpe wrote:
On Tue, Mar 23, 2021 at 12:47:24PM +0100, Daniel Vetter wrote:
+static inline bool is_cow_mapping(vm_flags_t flags)
Bit a bikeshed, but I wonder whether the public interface shouldn't be
vma_is_cow_mapping. Or whether this shouldn't be rejected some
On 3/23/21 3:00 PM, Jason Gunthorpe wrote:
On Sun, Mar 21, 2021 at 07:45:29PM +0100, Thomas Hellström (Intel) wrote:
To block fast gup we need to make sure TTM ptes are always special.
With MIXEDMAP we, on architectures that don't support pte_special,
insert normal ptes, but OTOH on
On 3/23/21 2:52 PM, Jason Gunthorpe wrote:
On Sun, Mar 21, 2021 at 07:45:28PM +0100, Thomas Hellström (Intel) wrote:
diff --git a/mm/gup.c b/mm/gup.c
index e40579624f10..1b6a127f0bdd 100644
+++ b/mm/gup.c
@@ -1993,6 +1993,17 @@ static void __maybe_unused undo_dev_pagemap(int *nr, int
Hi!
On 3/22/21 8:47 AM, Christian König wrote:
Am 21.03.21 um 19:45 schrieb Thomas Hellström (Intel):
To block fast gup we need to make sure TTM ptes are always special.
With MIXEDMAP we, on architectures that don't support pte_special,
insert normal ptes, but OTOH on those architectures,
patch makes sure we block normal gup by setting VM_PFNMAP
Cc: Christian Koenig
Cc: David Airlie
Cc: Daniel Vetter
Cc: Andrew Morton
Cc: Jason Gunthorpe
Cc: linux...@kvack.org
Cc: dri-de...@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Thomas Hellström (Intel)
Cc: Jason Gunthorpe
Cc: linux...@kvack.org
Cc: dri-de...@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Thomas Hellström (Intel)
---
drivers/gpu/drm/ttm/ttm_bo_vm.c | 17 -
mm/gup.c| 21 +++--
mm/memremap.c
Cc: Jason Gunthorpe
Cc: linux...@kvack.org
Cc: dri-de...@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Thomas Hellström (Intel)
---
drivers/gpu/drm/ttm/ttm_bo_vm.c | 22 --
include/linux/mm.h | 5 +
mm/internal.h | 5 -
The following commit has been merged into the sched/core branch of tip:
Commit-ID: b965f1ddb47daa5b8b2e2bc9c921431236830367
Gitweb:
https://git.kernel.org/tip/b965f1ddb47daa5b8b2e2bc9c921431236830367
Author:Peter Zijlstra (Intel)
AuthorDate:Mon, 18 Jan 2021 15:12:20 +01
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 826bfeb37bb4302ee6042f330c4c0c757152bdb8
Gitweb:
https://git.kernel.org/tip/826bfeb37bb4302ee6042f330c4c0c757152bdb8
Author:Peter Zijlstra (Intel)
AuthorDate:Mon, 18 Jan 2021 15:12:23 +01
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 2c9a98d3bc808717ab63ad928a2b568967775388
Gitweb:
https://git.kernel.org/tip/2c9a98d3bc808717ab63ad928a2b568967775388
Author:Peter Zijlstra (Intel)
AuthorDate:Mon, 18 Jan 2021 15:12:21 +01
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 40607ee97e4eec5655cc0f76a720bdc4c63a6434
Gitweb:
https://git.kernel.org/tip/40607ee97e4eec5655cc0f76a720bdc4c63a6434
Author:Peter Zijlstra (Intel)
AuthorDate:Mon, 18 Jan 2021 15:12:22 +01
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 0e79823f55de3cff95894fbb40440b17910e7378
Gitweb:
https://git.kernel.org/tip/0e79823f55de3cff95894fbb40440b17910e7378
Author:Peter Zijlstra (Intel)
AuthorDate:Mon, 18 Jan 2021 15:12:23 +01
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 74345075999752a7a9c805fe5e2ec770345cd1ca
Gitweb:
https://git.kernel.org/tip/74345075999752a7a9c805fe5e2ec770345cd1ca
Author:Peter Zijlstra (Intel)
AuthorDate:Mon, 18 Jan 2021 15:12:22 +01
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 4f8a0041162ab74ba5f89ee58f8aad59c4c85d22
Gitweb:
https://git.kernel.org/tip/4f8a0041162ab74ba5f89ee58f8aad59c4c85d22
Author:Peter Zijlstra (Intel)
AuthorDate:Mon, 18 Jan 2021 15:12:23 +01
The following commit has been merged into the sched/core branch of tip:
Commit-ID: bf3054bb801cf566e65e5f3d060435dbfa4a2f36
Gitweb:
https://git.kernel.org/tip/bf3054bb801cf566e65e5f3d060435dbfa4a2f36
Author:Peter Zijlstra (Intel)
AuthorDate:Mon, 18 Jan 2021 15:12:20 +01
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 8c98e8cf723c3ab2ac924b0942dd3b8074f874e5
Gitweb:
https://git.kernel.org/tip/8c98e8cf723c3ab2ac924b0942dd3b8074f874e5
Author:Peter Zijlstra (Intel)
AuthorDate:Mon, 18 Jan 2021 15:12:21 +01
ro.org
Cc: linux-r...@vger.kernel.org
Cc: amd-...@lists.freedesktop.org
Cc: intel-...@lists.freedesktop.org
Cc: Chris Wilson
Cc: Maarten Lankhorst
Cc: Christian König
Signed-off-by: Daniel Vetter
---
Documentation/driver-api/dma-buf.rst | 6
drivers/dma-buf/dma-fence.c | 41
On 6/4/20 10:12 AM, Daniel Vetter wrote:
Just some tiny edits:
- fix link to struct dma_fence
- give slightly more meaningful title - the polling here is about
implicit fences, explicit fences (in sync_file or drm_syncobj) also
have their own polling
Signed-off-by: Daniel Vetter
Revie
Hi, Daniel,
Please see below.
On 6/4/20 10:12 AM, Daniel Vetter wrote:
fs_reclaim_acquire/release nicely catch recursion issues when
allocating GFP_KERNEL memory against shrinkers (which gpu drivers tend
to use to keep the excessive caches in check). For mmu notifier
recursions we do have lockd
detail why cross-release isn't
the solution.
Cc: Mika Kuoppala
Cc: Thomas Hellstrom
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-r...@vger.kernel.org
Cc: amd-...@lists.freedesktop.org
Cc: intel-...@lists.freedesktop.org
Cc: Chris Wilson
Cc: Maarten
oppala
Cc: Thomas Hellstrom
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-r...@vger.kernel.org
Cc: amd-...@lists.freedesktop.org
Cc: intel-...@lists.freedesktop.org
Cc: Chris Wilson
Cc: Maarten Lankhorst
Cc: Christian König
Signed-off-by: Daniel Vetter
---
Documentat
.@vger.kernel.org
Cc: amd-...@lists.freedesktop.org
Cc: intel-...@lists.freedesktop.org
Cc: Chris Wilson
Cc: Maarten Lankhorst
Cc: Christian König
Signed-off-by: Daniel Vetter
LGTM. Perhaps some in-code documentation on how to use the new functions
are called.
Otherwise for patch 2 and 3,
Reviewed-by: Thomas Hellstrom
The following commit has been merged into the sched/core branch of tip:
Commit-ID: 90b5363acd4739769c3f38c1aff16171bd133e8c
Gitweb:
https://git.kernel.org/tip/90b5363acd4739769c3f38c1aff16171bd133e8c
Author:Peter Zijlstra (Intel)
AuthorDate:Fri, 27 Mar 2020 11:44:56 +01
Commit-ID: c5511d03ec090980732e929c318a7a6374b5550e
Gitweb: https://git.kernel.org/tip/c5511d03ec090980732e929c318a7a6374b5550e
Author: Peter Zijlstra (Intel)
AuthorDate: Sun, 25 Nov 2018 19:33:36 +0100
Committer: Thomas Gleixner
CommitDate: Wed, 28 Nov 2018 11:57:06 +0100
sched/smt
Commit-ID: 9d94e8b1d4f94a3c4cee5ad11a1be460cd070839
Gitweb: https://git.kernel.org/tip/9d94e8b1d4f94a3c4cee5ad11a1be460cd070839
Author: Peter Zijlstra (Intel)
AuthorDate: Wed, 3 Oct 2018 14:41:27 +0200
Committer: Borislav Petkov
CommitDate: Tue, 9 Oct 2018 12:30:25 +0200
x86/kaslr
The MIPS definition of termbits.h is almost identical to the generic
one, so use the generic one and only redefine a handful of constants.
Move TIOCSER_TEMT to ioctls.h where it lives for all other
architectures.
Signed-off-by: H. Peter Anvin (Intel)
Cc: Ralf Baechle
Cc: Paul Burton
Cc: James
Some architectures, in this case MIPS, need a couple of legacy alias
constants for bits. There really is no reason why we can't define them
generically for all architectures.
Signed-off-by: H. Peter Anvin (Intel)
Cc: Arnd Bergmann
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
linux-k
The Xtensa definition of termbits.h is identical to the generic one.
Signed-off-by: H. Peter Anvin (Intel)
Cc: Chris Zankel
Cc: Max Filippov
Cc: Thomas Gleixner
Cc: Greg Kroah-Hartman
Cc: Philippe Ombredanne
Cc: Kate Stewart
Cc:
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
---
arch/xtensa
changed, 27 insertions(+), 824 deletions(-)
Signed-off-by: H. Peter Anvin (Intel)
Cc: "James E.J. Bottomley"
Cc: Arnd Bergmann
Cc: Chris Zankel
Cc: Fenghua Yu
Cc: Greg Kroah-Hartman
Cc: Helge Deller
Cc: James Hogan
Cc: Jiri Slaby
Cc: Kate Stewart
Cc: Max Filippov
Cc: Paul
The IA64 definition of termbits.h is identical to the generic.
Signed-off-by: H. Peter Anvin (Intel)
Cc: Tony Luck
Cc: Fenghua Yu
Cc: Kate Stewart
Cc: Philippe Ombredanne
Cc: Greg Kroah-Hartman
Cc: Thomas Gleixner
Cc:
Cc: Greg Kroah-Hartman
CC: Jiri Slaby
---
arch/ia64/include/uapi/asm
The PARISC definition of termbits.h is almost identical to the generic
one, so use the generic one and only redefine a handful of constants.
Signed-off-by: H. Peter Anvin (Intel)
Cc: "James E.J. Bottomley"
Cc: Helge Deller
Cc: Kate Stewart
Cc: Thomas Gleixner
Cc: Philippe Ombr
Commit-ID: 3a387c6d96e69f1710a3804eb68e1253263298f2
Gitweb: https://git.kernel.org/tip/3a387c6d96e69f1710a3804eb68e1253263298f2
Author: Peter Zijlstra (Intel)
AuthorDate: Wed, 3 Oct 2018 14:41:27 +0200
Committer: Borislav Petkov
CommitDate: Wed, 3 Oct 2018 16:15:49 +0200
x86/kaslr
h.
Signed-off-by: H. Peter Anvin (Intel)
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Chang S. Bae
Cc: Markus T. Metzger
---
arch/x86/kernel/ldt.c | 70 +++
1 file changed, 54 insertions(+), 16 deletions(-)
diff --git a/arch/x86/ker
which is the larger of the
two.
Signed-off-by: H. Peter Anvin (Intel)
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Chang S. Bae
Cc: Markus T. Metzger
---
arch/x86/kernel/ldt.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kernel/ldt.c b/a
From: "H. Peter Anvin"
This is generic code which is potentially useful in other contexts.
Unfortunately modify_ldt() is kind of stupid in that it returns a
descriptor in CPU format but takes a different format, but regsets
*have* to operate differently.
Signed-off-by: H. Peter An
From: "H. Peter Anvin"
Give a debugger access to the visible part of the GDT and LDT. This
allows a debugger to find out what a particular segment descriptor
corresponds to; e.g. if %cs is 16, 32, or 64 bits.
v3:
Requalify LDT segments for selectors that have actually changed.
v2:
From: "H. Peter Anvin"
Provide ptrace/regset access to the LDT, if one exists. This
interface provides both read and write access. The write code is
unified with modify_ldt(); the read code doesn't have enough
similarity so it has been kept made separate.
Signed-off-by: H. Pet
From: "H. Peter Anvin"
We don't want to advertise to user space how many slots the kernel
GDT has, but user space can trivially find out what the last
user-accessible GDT slot is. Add a #define for that so we can use
that in sizing a regset.
Signed-off-by: H. Peter Anvin (I
From: "H. Peter Anvin"
Instead of using X86_32 || IA32_EMULATION, which is really rather ugly
in the Makefile especially, create a dedicated config symbol for the
TLS area. This will be further used in subsequent patches.
Signed-off-by: H. Peter Anvin (Intel)
Cc: Ingo Molnar
rea is the only
user-modifiable part of the GDT.
Signed-off-by: H. Peter Anvin (Intel)
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: Andy Lutomirski
Cc: Chang S. Bae
Cc: Markus T. Metzger
---
arch/x86/kernel/ptrace.c | 83 ++--
arch/x86/kernel/tls
Commit-ID: 641693094ee1568502280f95900f374b2226b51d
Gitweb: http://git.kernel.org/tip/641693094ee1568502280f95900f374b2226b51d
Author: Peter Zijlstra (Intel)
AuthorDate: Tue, 18 Apr 2017 19:05:05 +0200
Committer: Thomas Gleixner
CommitDate: Thu, 20 Apr 2017 13:08:57 +0200
perf: Avoid
Commit-ID: f5efc6fad63f5533a6083e95286920d5753e52bf
Gitweb: http://git.kernel.org/tip/f5efc6fad63f5533a6083e95286920d5753e52bf
Author: Peter Zijlstra (Intel)
AuthorDate: Tue, 18 Apr 2017 19:05:04 +0200
Committer: Thomas Gleixner
CommitDate: Thu, 20 Apr 2017 13:08:57 +0200
jump_label
Commit-ID: 82947f31231157d8ab70fa8961f23fd3887a3327
Gitweb: http://git.kernel.org/tip/82947f31231157d8ab70fa8961f23fd3887a3327
Author: Peter Zijlstra (Intel)
AuthorDate: Tue, 18 Apr 2017 19:05:03 +0200
Committer: Thomas Gleixner
CommitDate: Thu, 20 Apr 2017 13:08:57 +0200
jump_label
Commit-ID: 135cce1bf12bd30d7d66360022f9dac6ea3a07cd
Gitweb: http://git.kernel.org/tip/135cce1bf12bd30d7d66360022f9dac6ea3a07cd
Author: Peter Zijlstra (Intel)
AuthorDate: Thu, 30 Jun 2016 10:29:55 +0200
Committer: Arnaldo Carvalho de Melo
CommitDate: Thu, 30 Jun 2016 18:27:42 -0300
Commit-ID: 53dd9b5f95dda95bcadda1b4680be42dfe1f9e5e
Gitweb: http://git.kernel.org/tip/53dd9b5f95dda95bcadda1b4680be42dfe1f9e5e
Author: Peter Zijlstra (Intel)
AuthorDate: Thu, 30 Jun 2016 09:17:26 -0300
Committer: Arnaldo Carvalho de Melo
CommitDate: Thu, 30 Jun 2016 09:21:03 -0300
Commit-ID: e9d867a67fd03ccc07248ca4e9c2f74fed494d5b
Gitweb: http://git.kernel.org/tip/e9d867a67fd03ccc07248ca4e9c2f74fed494d5b
Author: Peter Zijlstra (Intel)
AuthorDate: Thu, 10 Mar 2016 12:54:08 +0100
Committer: Thomas Gleixner
CommitDate: Fri, 6 May 2016 14:58:22 +0200
sched: Allow
Commit-ID: 618d6e31623149c6203b46850e2e76ee0f29e577
Gitweb: http://git.kernel.org/tip/618d6e31623149c6203b46850e2e76ee0f29e577
Author: Peter Zijlstra (Intel)
AuthorDate: Thu, 10 Mar 2016 12:54:08 +0100
Committer: Thomas Gleixner
CommitDate: Thu, 5 May 2016 13:17:52 +0200
sched: Allow
Commit-ID: 13b35686e8b934ff78f59cef0c65fa3a43f8eeaf
Gitweb: http://git.kernel.org/tip/13b35686e8b934ff78f59cef0c65fa3a43f8eeaf
Author: Peter Zijlstra (Intel)
AuthorDate: Fri, 19 Feb 2016 09:46:37 +0100
Committer: Thomas Gleixner
CommitDate: Thu, 25 Feb 2016 11:27:16 +0100
wait.[ch
Commit-ID: b15f495b4e9295cf21065d8569835a2f18cfe41b
Gitweb: http://git.kernel.org/tip/b15f495b4e9295cf21065d8569835a2f18cfe41b
Author: Peter Zijlstra (Intel)
AuthorDate: Thu, 3 Sep 2015 20:07:47 -0700
Committer: Ingo Molnar
CommitDate: Sun, 13 Sep 2015 11:27:26 +0200
perf/core: Rename
Commit-ID: f233f7f1581e78fd9b4023f2e7d8c1ed89020cc9
Gitweb: http://git.kernel.org/tip/f233f7f1581e78fd9b4023f2e7d8c1ed89020cc9
Author: Peter Zijlstra (Intel)
AuthorDate: Fri, 24 Apr 2015 14:56:38 -0400
Committer: Ingo Molnar
CommitDate: Fri, 8 May 2015 12:37:09 +0200
locking
Commit-ID: 69f9cae90907e09af95fb991ed384670cef8dd32
Gitweb: http://git.kernel.org/tip/69f9cae90907e09af95fb991ed384670cef8dd32
Author: Peter Zijlstra (Intel)
AuthorDate: Fri, 24 Apr 2015 14:56:34 -0400
Committer: Ingo Molnar
CommitDate: Fri, 8 May 2015 12:36:48 +0200
locking/qspinlock
Commit-ID: 2aa79af64263190eec610422b07f60e99a7d230a
Gitweb: http://git.kernel.org/tip/2aa79af64263190eec610422b07f60e99a7d230a
Author: Peter Zijlstra (Intel)
AuthorDate: Fri, 24 Apr 2015 14:56:36 -0400
Committer: Ingo Molnar
CommitDate: Fri, 8 May 2015 12:36:58 +0200
locking/qspinlock
Commit-ID: c1fb159db9f2e50e0f4025bed92a67a6a7bfa7b7
Gitweb: http://git.kernel.org/tip/c1fb159db9f2e50e0f4025bed92a67a6a7bfa7b7
Author: Peter Zijlstra (Intel)
AuthorDate: Fri, 24 Apr 2015 14:56:32 -0400
Committer: Ingo Molnar
CommitDate: Fri, 8 May 2015 12:36:32 +0200
locking/qspinlock
Commit-ID: 8f95b435b62522aed3381aaea920de8d09ccabf3
Gitweb: http://git.kernel.org/tip/8f95b435b62522aed3381aaea920de8d09ccabf3
Author: Peter Zijlstra (Intel)
AuthorDate: Tue, 27 Jan 2015 11:53:12 +0100
Committer: Ingo Molnar
CommitDate: Wed, 4 Feb 2015 08:07:11 +0100
perf: Fix
Commit-ID: 86038c5ea81b519a8a1fcfcd5e4599aab0cdd119
Gitweb: http://git.kernel.org/tip/86038c5ea81b519a8a1fcfcd5e4599aab0cdd119
Author: Peter Zijlstra (Intel)
AuthorDate: Tue, 16 Dec 2014 12:47:34 +0100
Committer: Ingo Molnar
CommitDate: Wed, 14 Jan 2015 15:11:45 +0100
perf: Avoid
Commit-ID: ce5686d4ed12158599d2042a6c8659254ed263ce
Gitweb: http://git.kernel.org/tip/ce5686d4ed12158599d2042a6c8659254ed263ce
Author: Peter Zijlstra (Intel)
AuthorDate: Wed, 29 Oct 2014 11:17:04 +0100
Committer: Ingo Molnar
CommitDate: Tue, 4 Nov 2014 07:06:58 +0100
perf/x86: Fix
Commit-ID: 65d71fe1375b973083733294795bf2b09d45b3c2
Gitweb: http://git.kernel.org/tip/65d71fe1375b973083733294795bf2b09d45b3c2
Author: Peter Zijlstra (Intel)
AuthorDate: Tue, 7 Oct 2014 19:07:33 +0200
Committer: Ingo Molnar
CommitDate: Tue, 28 Oct 2014 10:51:01 +0100
perf: Fix bogus
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