[tip:perf/urgent] perf/x86/intel: Add support/quirk for the MISPREDICT bit on Knights Landing CPUs

Commit-ID: 16160c1946b702dcfa95ef63389a56deb2f1c7cb Gitweb: https://git.kernel.org/tip/16160c1946b702dcfa95ef63389a56deb2f1c7cb Author: Jacek Tomaka AuthorDate: Thu, 2 Aug 2018 09:38:30 +0800 Committer: Ingo Molnar CommitDate: Mon, 10 Sep 2018 10:03:01 +0200 perf/x86/intel: Add

Hugepages mixed with stacks in process address space

ation correctly, as having these pieces of information in place would greatly simplify my investigation. Regards. Jacek Tomaka

[tip:x86/microcode] x86/microcode: Make revision and processor flags world-readable

Commit-ID: f4661d293eb2d01dfc742982761a36fafe456d46 Gitweb: https://git.kernel.org/tip/f4661d293eb2d01dfc742982761a36fafe456d46 Author: Jacek Tomaka AuthorDate: Sat, 25 Aug 2018 11:50:39 +0800 Committer: Thomas Gleixner CommitDate: Sun, 2 Sep 2018 14:09:13 +0200 x86/microcode: Make

Re: [PATCH v4] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

> On 2 Aug 2018, at 6:07 pm, Thomas Gleixner wrote: > > The actiual purpose of sending V4 which is identical to V3 is? > >> >> Signed-off-by: Jacek Tomaka >> --- Yes, thanks. I missed it initially, sorry. > It's good practice to add a > >

Re: [PATCH] x86/microcode: allow non-root reading of microcode version and processor flags

On Mon, Aug 27, 2018 at 3:52 PM, Borislav Petkov wrote: > Your From: is Jacek Tomaka and your SOB is different. > Which one should I use? Please use my SOB: Jacek Tomaka > (Having a single email address for both is easier...) Sorry about the trouble. Regards. Jacek Tomaka

Re: [PATCH] x86/microcode: allow non-root reading of microcode version and processor flags

> On 26 Aug 2018, at 7:52 pm, Boris Petkov wrote: > >> On August 25, 2018 6:50:39 AM GMT+03:00, Jacek Tomaka >> wrote: >> /sys/devices/system/cpu/cpuX/microcode >> >> Before: >> -r processor_flags >> -r version >>

[PATCH] x86/microcode: allow non-root reading of microcode version and processor flags

/microcode/version Reported-by: Tim Burgess Signed-off-by: Jacek Tomaka --- arch/x86/kernel/cpu/microcode/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index b9bc8a1a58..2637ff09d6

[PATCH v4] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

From: Jacek Tomaka Problem: perf did not show branch predicted/mispredicted bit in brstack. Output of perf -F brstack for profile collected Before: 0x4fdbcd/0x4fdc03/-/-/-/0 0x45f4c1/0x4fdba0/-/-/-/0 0x45f544/0x45f4bb/-/-/-/0 0x45f555/0x45f53c/-/-/-/0 0x7f66901cc24b/0x45f555/-/-/-/0

[PATCH v3] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

From: Jacek Tomaka Problem: perf did not show branch predicted/mispredicted bit in brstack. Output of perf -F brstack for profile collected Before: 0x4fdbcd/0x4fdc03/-/-/-/0 0x45f4c1/0x4fdba0/-/-/-/0 0x45f544/0x45f4bb/-/-/-/0 0x45f555/0x45f53c/-/-/-/0 0x7f66901cc24b/0x45f555/-/-/-/0

Re: [PATCH v2] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

Ah, right: /* * Due to lack of segmentation in Linux the effective address (offset) * is the same as the linear address, allowing us to merge the LIP and EIP * LBR formats. */ Yeah, LBR_FORMAT_EIP_FLAGS is ok as well. Would it be preffered? On Tue, Jul 31, 2018 at 12:29 AM, Jacek Tomaka

Re: [PATCH v2] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

I do not understand the difference between linear address vs effective address but LBR_FORMAT_EIP_FLAGS implies effective address, no? On Tue, Jul 31, 2018 at 12:17 AM, Peter Zijlstra wrote: > On Mon, Jul 30, 2018 at 10:28:13PM +0800, Jacek Tomaka wrote: > > From: Jacek Tomaka > &

[PATCH v2] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

From: Jacek Tomaka Problem: perf did not show branch predicted/mispredicted bit in brstack. Output of perf -F brstack for profile collected Before: 0x4fdbcd/0x4fdc03/-/-/-/0 0x45f4c1/0x4fdba0/-/-/-/0 0x45f544/0x45f4bb/-/-/-/0 0x45f555/0x45f53c/-/-/-/0 0x7f66901cc24b/0x45f555/-/-/-/0

[PATCH] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

From: Jacek Tomaka Knights Landing supports half baked LBR_FORMAT_TIME format. The addresses are linear but it does have MISPREDICT bit but nothing else. Unfortunately IA32_PERF_CAPABILITIES[5:0] will report LBR_FORMAT_LIP. This change teaches LBR about this Knights Landing quirk. --- arch

[PATCH] x86/cpuid: Add missing TLB cpuid values

official Intel's documentation but the type column there is incorrect (states "Cache" where it should read "TLB") https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-vol-2a-manual.html Signed-off-by: Jacek Tomaka --- ar

Re: NO_HZ_FULL and tick running within a reasonable amount of time

742] R10: R11: 0018 R12: ffff91c5c7d18000 [ 134.800609] R13: 91c5c7d2 R14: R15: 91c8ebe65e30 [ 134.887477] FS: () GS:91c8eb20() knlGS: [ 134.985988] CS: 0010 DS: ES: CR0: 80050033 [ 135.055930] CR2: 7f8cd5352f70 CR3: 00036f40a000 CR4: 001406f0 [ 135.142801] Call Trace: [ 135.172563] process_one_work+0x152/0x350 [ 135.221345] worker_thread+0x47/0x3e0 [ 135.265903] kthread+0xf5/0x130 [ 135.304109] ? max_active_store+0x80/0x80 [ 135.352893] ? kthread_bind+0x10/0x10 [ 135.397458] ret_from_fork+0x35/0x40 [ 135.440953] Code: 83 40 0b 00 00 48 85 c0 0f 85 5f ff ff ff e9 63 ff ff ff 80 3d dd ef 12 01 00 75 a0 48 89 34 24 e8 5e 55 00 00 48 8b 34 24 eb 91 <0f> 0b eb a5 0f 1f 80 00 00 00 00 0f 1f 44 00 00 41 56 41 55 41 [ 135.670765] ---[ end trace 7031db6a8ce43506 ]-- Regards. -- Jacek Tomaka