Hi Linus,
The following changes since commit 16ae16c6e5616c084168740990fc508bda6655d4:
Merge tag 'mmc-v4.9-rc5' of
git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc (2016-11-24
10:51:18 -0800)
are available in the git repository at:
Hi Linus,
The following changes since commit 16ae16c6e5616c084168740990fc508bda6655d4:
Merge tag 'mmc-v4.9-rc5' of
git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc (2016-11-24
10:51:18 -0800)
are available in the git repository at:
gt;
>> This patch implements the poll and fasync file operation callback for
>> the test mailbox device.
>>
>> Cc: Lee Jones <lee.jo...@linaro.org>
>> Cc: Jassi Brar <jaswinder.si...@linaro.org>
>> Signed-off-by: Sudeep Holla <sudeep.ho...@arm.com>
>
> Gentle Ping!
>
Would be good to have Lee's ack.
is patch implements the poll and fasync file operation callback for
>> the test mailbox device.
>>
>> Cc: Lee Jones
>> Cc: Jassi Brar
>> Signed-off-by: Sudeep Holla
>
> Gentle Ping!
>
Would be good to have Lee's ack.
synchronization
> mechanism.
>
> Based on work by Joseph Lo <jose...@nvidia.com>.
>
> Signed-off-by: Thierry Reding <tred...@nvidia.com>
Acked-by: Jassi Brar <jaswinder.si...@linaro.org>
seph Lo .
>
> Signed-off-by: Thierry Reding
Acked-by: Jassi Brar
On Wed, Nov 16, 2016 at 8:38 PM, Thierry Reding
<thierry.red...@gmail.com> wrote:
> On Wed, Nov 16, 2016 at 10:58:07AM +0530, Jassi Brar wrote:
>> On Tue, Nov 15, 2016 at 9:18 PM, Thierry Reding
>> <thierry.red...@gmail.com> wrote:
>>
>>
>> >
On Wed, Nov 16, 2016 at 8:38 PM, Thierry Reding
wrote:
> On Wed, Nov 16, 2016 at 10:58:07AM +0530, Jassi Brar wrote:
>> On Tue, Nov 15, 2016 at 9:18 PM, Thierry Reding
>> wrote:
>>
>>
>> > +
>> > +struct tegra_hsp_channel;
>> > +struc
On Tue, Nov 15, 2016 at 9:18 PM, Thierry Reding
wrote:
> +
> +struct tegra_hsp_channel;
> +struct tegra_hsp;
> +
> +struct tegra_hsp_channel_ops {
> + int (*send_data)(struct tegra_hsp_channel *channel, void *data);
> + int (*startup)(struct
On Tue, Nov 15, 2016 at 9:18 PM, Thierry Reding
wrote:
> +
> +struct tegra_hsp_channel;
> +struct tegra_hsp;
> +
> +struct tegra_hsp_channel_ops {
> + int (*send_data)(struct tegra_hsp_channel *channel, void *data);
> + int (*startup)(struct tegra_hsp_channel *channel);
> +
On 11 November 2016 at 15:04, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
> On Fri, 2016-11-11 at 11:15 +0530, Jassi Brar wrote:
>> On Thu, Nov 10, 2016 at 4:45 PM, Horng-Shyang Liao <hs.l...@mediatek.com>
>> wrote:
>> > On Tue, 2016-11-01 at
On 11 November 2016 at 15:04, Horng-Shyang Liao wrote:
> On Fri, 2016-11-11 at 11:15 +0530, Jassi Brar wrote:
>> On Thu, Nov 10, 2016 at 4:45 PM, Horng-Shyang Liao
>> wrote:
>> > On Tue, 2016-11-01 at 19:28 +0800, HS Liao wrote:
>> >> Hi,
>> >>
On Thu, Nov 10, 2016 at 4:45 PM, Horng-Shyang Liao wrote:
> On Tue, 2016-11-01 at 19:28 +0800, HS Liao wrote:
>> Hi,
>>
>> This is Mediatek MT8173 Command Queue(CMDQ) driver. The CMDQ is used
>> to help write registers with critical time limitation, such as
>> updating
On Thu, Nov 10, 2016 at 4:45 PM, Horng-Shyang Liao wrote:
> On Tue, 2016-11-01 at 19:28 +0800, HS Liao wrote:
>> Hi,
>>
>> This is Mediatek MT8173 Command Queue(CMDQ) driver. The CMDQ is used
>> to help write registers with critical time limitation, such as
>> updating display configuration
On 11 October 2016 at 08:10, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
> On Thu, 2016-10-06 at 18:40 +0530, Jassi Brar wrote:
>> On 6 October 2016 at 18:31, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
>>
>> > Back to our original statement, we need to
On 11 October 2016 at 08:10, Horng-Shyang Liao wrote:
> On Thu, 2016-10-06 at 18:40 +0530, Jassi Brar wrote:
>> On 6 October 2016 at 18:31, Horng-Shyang Liao wrote:
>>
>> > Back to our original statement, we need to flush all tasks to queue
>> > in GCE HW; i.e.
On 6 October 2016 at 18:31, Horng-Shyang Liao wrote:
> Back to our original statement, we need to flush all tasks to queue
> in GCE HW; i.e. we need to use mbox_client_txdone after
> mbox_send_message, or send tx_done once mailbox controller receive
> message (task).
On 6 October 2016 at 18:31, Horng-Shyang Liao wrote:
> Back to our original statement, we need to flush all tasks to queue
> in GCE HW; i.e. we need to use mbox_client_txdone after
> mbox_send_message, or send tx_done once mailbox controller receive
> message (task). However, we still need a way
Hi Linus,
The following changes since commit d060e0f603a4156087813d221d818bb39ec91429:
Merge tag 'for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
(2016-09-06 12:33:12 -0700)
are available in the git repository at:
Hi Linus,
The following changes since commit d060e0f603a4156087813d221d818bb39ec91429:
Merge tag 'for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
(2016-09-06 12:33:12 -0700)
are available in the git repository at:
On 5 October 2016 at 18:01, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
> On Wed, 2016-10-05 at 09:07 +0530, Jassi Brar wrote:
>> On 5 October 2016 at 08:24, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
>> > On Fri, 2016-09-30 at 17:47 +0800, Horng-Shyang Lia
On 5 October 2016 at 18:01, Horng-Shyang Liao wrote:
> On Wed, 2016-10-05 at 09:07 +0530, Jassi Brar wrote:
>> On 5 October 2016 at 08:24, Horng-Shyang Liao wrote:
>> > On Fri, 2016-09-30 at 17:47 +0800, Horng-Shyang Liao wrote:
>> >> On Fri, 2016-09-
On 5 October 2016 at 08:24, Horng-Shyang Liao wrote:
> On Fri, 2016-09-30 at 17:47 +0800, Horng-Shyang Liao wrote:
>> On Fri, 2016-09-30 at 17:11 +0800, CK Hu wrote:
>
> After I trace mailbox driver, I realize that CMDQ driver cannot use
> tx_done.
>
> CMDQ clients will
On 5 October 2016 at 08:24, Horng-Shyang Liao wrote:
> On Fri, 2016-09-30 at 17:47 +0800, Horng-Shyang Liao wrote:
>> On Fri, 2016-09-30 at 17:11 +0800, CK Hu wrote:
>
> After I trace mailbox driver, I realize that CMDQ driver cannot use
> tx_done.
>
> CMDQ clients will flush many tasks into
On Mon, Sep 5, 2016 at 7:14 AM, HS Liao wrote:
> This patch is first version of Mediatek Command Queue(CMDQ) driver. The
> CMDQ is used to help write registers with critical time limitation,
> such as updating display configuration during the vblank. It controls
> Global
On Mon, Sep 5, 2016 at 7:14 AM, HS Liao wrote:
> This patch is first version of Mediatek Command Queue(CMDQ) driver. The
> CMDQ is used to help write registers with critical time limitation,
> such as updating display configuration during the vblank. It controls
> Global Command Engine (GCE)
On Mon, Sep 5, 2016 at 7:14 AM, HS Liao wrote:
> Use clk_disable_unprepare instead of clk_disable to save more energy
> when CMDQ is idle.
>
> Signed-off-by: HS Liao
> ---
> drivers/mailbox/mtk-cmdq.c | 54
>
On Mon, Sep 5, 2016 at 7:14 AM, HS Liao wrote:
> Use clk_disable_unprepare instead of clk_disable to save more energy
> when CMDQ is idle.
>
> Signed-off-by: HS Liao
> ---
> drivers/mailbox/mtk-cmdq.c | 54
> +++---
The driver is introduced by second
Hi Linus,
The following changes since commit 5e608a027082ae426e100a582031e0ff40becc83:
Merge branch 'akpm' (patches from Andrew) (2016-08-26 23:12:12 -0700)
are available in the git repository at:
git://git.linaro.org/landing-teams/working/fujitsu/integration.git
mailbox-devel
for you to
Hi Linus,
The following changes since commit 5e608a027082ae426e100a582031e0ff40becc83:
Merge branch 'akpm' (patches from Andrew) (2016-08-26 23:12:12 -0700)
are available in the git repository at:
git://git.linaro.org/landing-teams/working/fujitsu/integration.git
mailbox-devel
for you to
On Sun, Sep 4, 2016 at 2:15 AM, Kevin Hilman <khil...@baylibre.com> wrote:
> On Fri, Sep 2, 2016 at 10:33 PM, Jassi Brar <jassisinghb...@gmail.com> wrote:
>> On Sat, Sep 3, 2016 at 5:04 AM, Kevin Hilman <khil...@baylibre.com> wrote:
>>> Hi Jassi,
>>>
On Sun, Sep 4, 2016 at 2:15 AM, Kevin Hilman wrote:
> On Fri, Sep 2, 2016 at 10:33 PM, Jassi Brar wrote:
>> On Sat, Sep 3, 2016 at 5:04 AM, Kevin Hilman wrote:
>>> Hi Jassi,
>>>
>>> Neil Armstrong writes:
>>>
>>>> In order to supp
On Sat, Sep 3, 2016 at 5:04 AM, Kevin Hilman wrote:
> Hi Jassi,
>
> Neil Armstrong writes:
>
>> In order to support Mailbox links for the Amlogic GXBB SoC, add a generic
>> platform MHU driver based on arm_mhu.c.
>>
>> This patchset follows a RFC
On Sat, Sep 3, 2016 at 5:04 AM, Kevin Hilman wrote:
> Hi Jassi,
>
> Neil Armstrong writes:
>
>> In order to support Mailbox links for the Amlogic GXBB SoC, add a generic
>> platform MHU driver based on arm_mhu.c.
>>
>> This patchset follows a RFC thread along the GXBB SCPI support at :
>>
On Wed, Aug 31, 2016 at 1:43 PM, Horng-Shyang Liao wrote:
>> >> The driver uses the mailbox framework, so it should live in the
>> >> drivers/mailbox folder.
>> >
>> > As you know, the maximum number of gce threads is 16.
>> > However, we plan to support more clients in the
On Wed, Aug 31, 2016 at 1:43 PM, Horng-Shyang Liao wrote:
>> >> The driver uses the mailbox framework, so it should live in the
>> >> drivers/mailbox folder.
>> >
>> > As you know, the maximum number of gce threads is 16.
>> > However, we plan to support more clients in the future,
>> > and they
On Thu, Aug 25, 2016 at 7:07 PM, Horng-Shyang Liao wrote:
> Hi Matthias,
>
> On Wed, 2016-08-24 at 13:00 +0200, Matthias Brugger wrote:
>> On 24/08/16 05:27, HS Liao wrote:
> [...]
>> > Changes since v12:
>> > - remove mediatek,gce from device tree
>>
>> Why? The binding
On Thu, Aug 25, 2016 at 7:07 PM, Horng-Shyang Liao wrote:
> Hi Matthias,
>
> On Wed, 2016-08-24 at 13:00 +0200, Matthias Brugger wrote:
>> On 24/08/16 05:27, HS Liao wrote:
> [...]
>> > Changes since v12:
>> > - remove mediatek,gce from device tree
>>
>> Why? The binding got accepted by Rob.
>
>
Hi Linus,
The following changes since commit 8714f8f5fe396ca513ccaaac2304497439c181fb:
Merge branch 'for-linus' of git://git.kernel.dk/linux-block
(2016-06-11 18:42:59 -0700)
are available in the git repository at:
git://git.linaro.org/landing-teams/working/fujitsu/integration.git
Hi Linus,
The following changes since commit 8714f8f5fe396ca513ccaaac2304497439c181fb:
Merge branch 'for-linus' of git://git.kernel.dk/linux-block
(2016-06-11 18:42:59 -0700)
are available in the git repository at:
git://git.linaro.org/landing-teams/working/fujitsu/integration.git
On Tue, Jul 26, 2016 at 7:01 AM, Ruslan Bilovol
wrote:
> On Fri, Jul 15, 2016 at 10:43 AM, Clemens Ladisch wrote:
On Tue, May 24, 2016 at 2:50 AM, Ruslan Bilovol
wrote:
> it may break current usecase for some
On Tue, Jul 26, 2016 at 7:01 AM, Ruslan Bilovol
wrote:
> On Fri, Jul 15, 2016 at 10:43 AM, Clemens Ladisch wrote:
On Tue, May 24, 2016 at 2:50 AM, Ruslan Bilovol
wrote:
> it may break current usecase for some people
>>
>> And what are the benefits that justify breaking the kernel
On Wed, Jul 6, 2016 at 6:47 PM, Neil Armstrong <narmstr...@baylibre.com> wrote:
> 2016-07-04 17:38 GMT+02:00 Jassi Brar <jassisinghb...@gmail.com>:
>> On Tue, Jun 21, 2016 at 3:32 PM, Neil Armstrong <narmstr...@baylibre.com>
>> wrote:
>>> Add Amlogic M
On Wed, Jul 6, 2016 at 6:47 PM, Neil Armstrong wrote:
> 2016-07-04 17:38 GMT+02:00 Jassi Brar :
>> On Tue, Jun 21, 2016 at 3:32 PM, Neil Armstrong
>> wrote:
>>> Add Amlogic Meson SoCs Message-Handling-Unit as mailbox controller
>>> with 2 independent channels/l
mstrong <narmstr...@baylibre.com>
> + * Heavily based on meson_mhu.c from :
> + * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
> + * Copyright (C) 2015 Linaro Ltd.
> + * Author: Jassi Brar <jaswinder.si...@linaro.org>
> + *
> + * This program is free software: y
opyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
> + * Copyright (C) 2015 Linaro Ltd.
> + * Author: Jassi Brar
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
On Tue, Jun 28, 2016 at 8:36 PM, Jassi Brar <jassisinghb...@gmail.com> wrote:
> On Tue, Jun 28, 2016 at 7:30 PM, Neil Armstrong <narmstr...@baylibre.com>
> wrote:
>>
>> My main question is : do you really want to transform this simple driver into
>> a di
On Tue, Jun 28, 2016 at 8:36 PM, Jassi Brar wrote:
> On Tue, Jun 28, 2016 at 7:30 PM, Neil Armstrong
> wrote:
>>
>> My main question is : do you really want to transform this simple driver into
>> a dirty multi-bus generic mailbox driver ?
>> The meson_mhu is only
On Tue, Jun 28, 2016 at 7:06 PM, Rob Rice wrote:
>>> drivers/mailbox/Kconfig |9 +
>>> drivers/mailbox/Makefile|2 +
>>> drivers/mailbox/mailbox-pdc/Makefile|8 +
>>> drivers/mailbox/mailbox-pdc/pdc.c | 1181
>>>
On Tue, Jun 28, 2016 at 7:06 PM, Rob Rice wrote:
>>> drivers/mailbox/Kconfig |9 +
>>> drivers/mailbox/Makefile|2 +
>>> drivers/mailbox/mailbox-pdc/Makefile|8 +
>>> drivers/mailbox/mailbox-pdc/pdc.c | 1181
>>>
On Tue, Jun 28, 2016 at 7:30 PM, Neil Armstrong <narmstr...@baylibre.com> wrote:
> On 06/25/2016 07:50 PM, Jassi Brar wrote:
>> -#define INTR_STAT_OFS 0x0
>> -#define INTR_SET_OFS 0x8
>> -#define INTR_CLR_OFS 0x10
>> -
>> -#define MHU_LP_OFFSET 0x0
>
On Tue, Jun 28, 2016 at 7:30 PM, Neil Armstrong wrote:
> On 06/25/2016 07:50 PM, Jassi Brar wrote:
>> -#define INTR_STAT_OFS 0x0
>> -#define INTR_SET_OFS 0x8
>> -#define INTR_CLR_OFS 0x10
>> -
>> -#define MHU_LP_OFFSET 0x0
>> -#define MHU_HP_OFFSET
On Tue, May 24, 2016 at 11:37 PM, Rob Rice wrote:
> From: Rob Rice
>
> The Broadcom PDC mailbox driver is a mailbox controller that
> manages data transfers to and from one or more offload engines.
>
> Signed-off-by: Rob Rice
>
On Tue, May 24, 2016 at 11:37 PM, Rob Rice wrote:
> From: Rob Rice
>
> The Broadcom PDC mailbox driver is a mailbox controller that
> manages data transfers to and from one or more offload engines.
>
> Signed-off-by: Rob Rice
> Reviewed-by: Scott Branden
> Reviewed-by: Ray Jui
> ---
>
-#define INTR_STAT_OFS 0x0
-#define INTR_SET_OFS 0x8
-#define INTR_CLR_OFS 0x10
-
-#define MHU_LP_OFFSET 0x0
-#define MHU_HP_OFFSET 0x20
-#define MHU_SEC_OFFSET 0x200
-#define TX_REG_OFFSET 0x100
+#define INTR_SET_OFS 0x0
+#define INTR_STAT_OFS 0x4
+#define INTR_CLR_OFS 0x8
-#define
-#define INTR_STAT_OFS 0x0
-#define INTR_SET_OFS 0x8
-#define INTR_CLR_OFS 0x10
-
-#define MHU_LP_OFFSET 0x0
-#define MHU_HP_OFFSET 0x20
-#define MHU_SEC_OFFSET 0x200
-#define TX_REG_OFFSET 0x100
+#define INTR_SET_OFS 0x0
+#define INTR_STAT_OFS 0x4
+#define INTR_CLR_OFS 0x8
-#define
.
> + * Copyright (C) 2015 Linaro Ltd.
> + * Author: Jassi Brar <jaswinder.si...@linaro.org>
.
> +
> +#define INTR_SET_OFS 0x0
> +#define INTR_STAT_OFS 0x4
> +#define INTR_CLR_OFS 0x8
> +
> +#define MHU_LP_OFFSET 0x10
> +#define MHU_HP_OFFSET 0x1c
>
gt; @@ -0,0 +1,199 @@
> +/*
> + * Copyright (C) 2016 BayLibre SAS.
> + * Author: Neil Armstrong
> + * Heavily based on meson_mhu.c from :
> + * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
> + * Copyright (C) 2015 Linaro Ltd.
> + * Author: Jassi Brar
.
>
On Tue, May 24, 2016 at 6:31 AM, Hoan Tran wrote:
> Hi Rob,
>
> Thanks for your review !
>
> On Mon, May 23, 2016 at 1:30 PM, Rob Herring wrote:
>>
>> On Mon, May 16, 2016 at 09:17:25AM -0700, Hoan Tran wrote:
>> > This patch adds the APM X-Gene hwmon device tree
On Tue, May 24, 2016 at 6:31 AM, Hoan Tran wrote:
> Hi Rob,
>
> Thanks for your review !
>
> On Mon, May 23, 2016 at 1:30 PM, Rob Herring wrote:
>>
>> On Mon, May 16, 2016 at 09:17:25AM -0700, Hoan Tran wrote:
>> > This patch adds the APM X-Gene hwmon device tree node documentation.
>> >
>> >
On Fri, Jun 3, 2016 at 4:48 PM, Matthias Brugger wrote:
> On 03/06/16 08:12, Horng-Shyang Liao wrote:
>> On Thu, 2016-06-02 at 10:46 +0200, Matthias Brugger wrote:
>>> I keep thinking about how to get rid of the two data structures,
>>> task_busy_list and the
On Fri, Jun 3, 2016 at 4:48 PM, Matthias Brugger wrote:
> On 03/06/16 08:12, Horng-Shyang Liao wrote:
>> On Thu, 2016-06-02 at 10:46 +0200, Matthias Brugger wrote:
>>> I keep thinking about how to get rid of the two data structures,
>>> task_busy_list and the task_release_wq. We need the latter
Hi Linus,
The following changes since commit c3b46c73264b03000d1e18b22f5caf63332547c9:
Linux 4.6-rc4 (2016-04-17 19:13:32 -0700)
are available in the git repository at:
git://git.linaro.org/landing-teams/working/fujitsu/integration.git
mailbox-for-next
for you to fetch changes up to
Hi Linus,
The following changes since commit c3b46c73264b03000d1e18b22f5caf63332547c9:
Linux 4.6-rc4 (2016-04-17 19:13:32 -0700)
are available in the git repository at:
git://git.linaro.org/landing-teams/working/fujitsu/integration.git
mailbox-for-next
for you to fetch changes up to
On Tue, May 10, 2016 at 9:26 PM, Stephen Warren <swar...@wwwdotorg.org> wrote:
> On 05/09/2016 09:29 PM, Jassi Brar wrote:
>
>> Some controllers need a mask/list of destination cpus, to which the
>> irq is raised, written to some 'data' register. You too probably need
>&
On Tue, May 10, 2016 at 9:26 PM, Stephen Warren wrote:
> On 05/09/2016 09:29 PM, Jassi Brar wrote:
>
>> Some controllers need a mask/list of destination cpus, to which the
>> irq is raised, written to some 'data' register. You too probably need
>> to program the destinatio
On Tue, May 10, 2016 at 5:15 AM, Stephen Warren wrote:
> Jassi,
>
> Does the HW described below sound like something that should be represented
> using the Linux kernel's mailbox subsystem, and related DT bindings? I think
> the existing drivers/mailbox/pcc.c is similar,
On Tue, May 10, 2016 at 5:15 AM, Stephen Warren wrote:
> Jassi,
>
> Does the HW described below sound like something that should be represented
> using the Linux kernel's mailbox subsystem, and related DT bindings? I think
> the existing drivers/mailbox/pcc.c is similar, but wanted to
On 27 April 2016 at 19:17, Robin Murphy wrote:
>> Instead of churning the code, I would suggest either check in a loop
>> that we have a desc OR allocate 2 or NR_DEFAULT_DESC descriptors
>> there. Probably we get more descriptors at the same cost of memory.
>
>
> Having had
On 27 April 2016 at 19:17, Robin Murphy wrote:
>> Instead of churning the code, I would suggest either check in a loop
>> that we have a desc OR allocate 2 or NR_DEFAULT_DESC descriptors
>> there. Probably we get more descriptors at the same cost of memory.
>
>
> Having had a quick look into how
On Tue, Apr 26, 2016 at 10:00 PM, Robin Murphy wrote:
> The current logic in pl330_get_desc() contains a clear race condition,
> whereby if the descriptor pool is empty, we will create a new
> descriptor, add it to the pool with the lock held, *release the lock*,
> then try
On Tue, Apr 26, 2016 at 10:00 PM, Robin Murphy wrote:
> The current logic in pl330_get_desc() contains a clear race condition,
> whereby if the descriptor pool is empty, we will create a new
> descriptor, add it to the pool with the lock held, *release the lock*,
> then try to remove it from the
On Wed, Apr 6, 2016 at 6:37 PM, Suman Anna wrote:
> Hi Jassi,
>
> This series cleans up the OMAP Mailbox driver dropping the
> support for legacy non-DT platform devices. The infrastructure
> for creating any such devices has all been cleaned up from the
> mach-omap2 layers.
>
>
On Wed, Apr 6, 2016 at 6:37 PM, Suman Anna wrote:
> Hi Jassi,
>
> This series cleans up the OMAP Mailbox driver dropping the
> support for legacy non-DT platform devices. The infrastructure
> for creating any such devices has all been cleaned up from the
> mach-omap2 layers.
>
> The removal from
Hi Linus,
The following changes since commit 3c9688876ace9ca4cd8630e5fbba8bb28235990a:
Revert "ib_srpt: Convert to percpu_ida tag allocation" (2016-04-07
18:16:20 -0700)
are available in the git repository at:
git://git.linaro.org/landing-teams/working/fujitsu/integration.git
mailbox-devel
Hi Linus,
The following changes since commit 3c9688876ace9ca4cd8630e5fbba8bb28235990a:
Revert "ib_srpt: Convert to percpu_ida tag allocation" (2016-04-07
18:16:20 -0700)
are available in the git repository at:
git://git.linaro.org/landing-teams/working/fujitsu/integration.git
mailbox-devel
On Tue, Apr 12, 2016 at 12:57 PM, Lee Jones wrote:
> On Wed, 23 Mar 2016, Lee Jones wrote:
>
>> Hi Jassi,
>>
>> Resending these with patches 1 and 2 merged, as requested.
>
> Jassi,
>
> Not heard anything from you in quite some time now.
>
Please feel free to call as soon as
On Tue, Apr 12, 2016 at 12:57 PM, Lee Jones wrote:
> On Wed, 23 Mar 2016, Lee Jones wrote:
>
>> Hi Jassi,
>>
>> Resending these with patches 1 and 2 merged, as requested.
>
> Jassi,
>
> Not heard anything from you in quite some time now.
>
Please feel free to call as soon as it goes beyond
Hi Linus,
Due to some last minute cosmetic changes, the driver was not included
in the first pull request, otherwise the driver has been reviewed
twice. Could you please consider pulling it, so it doesn't get delayed
for another cycle?
The following changes since commit
Hi Linus,
Due to some last minute cosmetic changes, the driver was not included
in the first pull request, otherwise the driver has been reviewed
twice. Could you please consider pulling it, so it doesn't get delayed
for another cycle?
The following changes since commit
Hi Linus,
The following changes since commit 1926e54f115725a9248d0c4c65c22acaf94de4c4:
MAINTAINERS: Update mailing list for Renesas ARM64 SoC Development
(2016-02-14 18:38:15 -0800)
are available in the git repository at:
git://git.linaro.org/landing-teams/working/fujitsu/integration.git
Hi Linus,
The following changes since commit 1926e54f115725a9248d0c4c65c22acaf94de4c4:
MAINTAINERS: Update mailing list for Renesas ARM64 SoC Development
(2016-02-14 18:38:15 -0800)
are available in the git repository at:
git://git.linaro.org/landing-teams/working/fujitsu/integration.git
On Tue, Mar 15, 2016 at 10:35 PM, Nishanth Menon <n...@ti.com> wrote:
> On Tue, Mar 15, 2016 at 12:31 AM, Jassi Brar <jassisinghb...@gmail.com> wrote:
>> On Tue, Mar 8, 2016 at 8:07 PM, Nishanth Menon <n...@ti.com> wrote:
>>> Jassi,
>>>
>>> O
On Tue, Mar 15, 2016 at 10:35 PM, Nishanth Menon wrote:
> On Tue, Mar 15, 2016 at 12:31 AM, Jassi Brar wrote:
>> On Tue, Mar 8, 2016 at 8:07 PM, Nishanth Menon wrote:
>>> Jassi,
>>>
>>> On Tue, Mar 8, 2016 at 1:10 AM, Jassi Brar wrote:
>>>> On Tu
On Tue, Mar 8, 2016 at 8:07 PM, Nishanth Menon <n...@ti.com> wrote:
> Jassi,
>
> On Tue, Mar 8, 2016 at 1:10 AM, Jassi Brar <jassisinghb...@gmail.com> wrote:
>> On Tue, Mar 8, 2016 at 2:18 AM, Nishanth Menon <n...@ti.com> wrote:
>>> On 03/07/2016 12:3
On Tue, Mar 8, 2016 at 8:07 PM, Nishanth Menon wrote:
> Jassi,
>
> On Tue, Mar 8, 2016 at 1:10 AM, Jassi Brar wrote:
>> On Tue, Mar 8, 2016 at 2:18 AM, Nishanth Menon wrote:
>>> On 03/07/2016 12:31 PM, Jassi Brar wrote:
>>>> On Fri, Mar 4, 20
On Tue, Mar 8, 2016 at 1:48 AM, Heiko Stübner wrote:
> Hi Jassi,
>
> Am Dienstag, 27. Oktober 2015, 15:31:45 schrieb Caesar Wang:
>> This driver is found on RK3368 SoCs.
>>
>> The Mailbox module is a simple APB peripheral that allows both
>> the Cortex-A53 MCU system to
On Tue, Mar 8, 2016 at 1:48 AM, Heiko Stübner wrote:
> Hi Jassi,
>
> Am Dienstag, 27. Oktober 2015, 15:31:45 schrieb Caesar Wang:
>> This driver is found on RK3368 SoCs.
>>
>> The Mailbox module is a simple APB peripheral that allows both
>> the Cortex-A53 MCU system to communicate by writing
On Tue, Mar 8, 2016 at 2:18 AM, Nishanth Menon <n...@ti.com> wrote:
> On 03/07/2016 12:31 PM, Jassi Brar wrote:
>> On Fri, Mar 4, 2016 at 8:05 PM, Nishanth Menon <n...@ti.com> wrote:
>>>>
>>>>> +static int ti_msgmgr_send_data(struct mbox_chan *chan,
On Tue, Mar 8, 2016 at 2:18 AM, Nishanth Menon wrote:
> On 03/07/2016 12:31 PM, Jassi Brar wrote:
>> On Fri, Mar 4, 2016 at 8:05 PM, Nishanth Menon wrote:
>>>>
>>>>> +static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data)
>>>>> +{
On Fri, Mar 4, 2016 at 8:05 PM, Nishanth Menon <n...@ti.com> wrote:
> Hi Jassi,
>
> Thanks for reviewing the patch.
> On 03/03/2016 11:18 PM, Jassi Brar wrote:
>
> [...]
>
>>>
>>> drivers/mailbox/Kconfig | 11 +
>>> drivers/mailbox/Make
On Fri, Mar 4, 2016 at 8:05 PM, Nishanth Menon wrote:
> Hi Jassi,
>
> Thanks for reviewing the patch.
> On 03/03/2016 11:18 PM, Jassi Brar wrote:
>
> [...]
>
>>>
>>> drivers/mailbox/Kconfig | 11 +
>>> drivers/mailbox/Makefile| 2 +
&g
On Sat, Feb 27, 2016 at 3:54 AM, Nishanth Menon wrote:
> Support for TI Message Manager Module. This hardware block manages a
> bunch of hardware queues meant for communication between processor
> entities.
>
> Clients sitting on top of this would manage the required protocol
> for
On Sat, Feb 27, 2016 at 3:54 AM, Nishanth Menon wrote:
> Support for TI Message Manager Module. This hardware block manages a
> bunch of hardware queues meant for communication between processor
> entities.
>
> Clients sitting on top of this would manage the required protocol
> for communicating
On 2 March 2016 at 00:30, Stephen Boyd <sb...@codeaurora.org> wrote:
> This flag is a no-op now. Remove usage of the flag.
>
> Cc: Jassi Brar <jaswinder.si...@linaro.org>
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
Acked-by: Jassi Brar <jaswinder.si...@linaro.org>
On 2 March 2016 at 00:30, Stephen Boyd wrote:
> This flag is a no-op now. Remove usage of the flag.
>
> Cc: Jassi Brar
> Signed-off-by: Stephen Boyd
Acked-by: Jassi Brar
On Thu, Feb 11, 2016 at 10:33 AM, Nishanth Menon <n...@ti.com> wrote:
> Hi Jassi,
>
> On 02/10/2016 10:23 PM, Jassi Brar wrote:
> [...]
>
>
> Thanks for taking the time and checking the TRM, I apologize that the
> actual details of the hardware block which was supp
On Thu, Feb 11, 2016 at 10:33 AM, Nishanth Menon wrote:
> Hi Jassi,
>
> On 02/10/2016 10:23 PM, Jassi Brar wrote:
> [...]
>
>
> Thanks for taking the time and checking the TRM, I apologize that the
> actual details of the hardware block which was supposed to be in
> s
On Mon, Feb 15, 2016 at 7:20 PM, Leo Yan wrote:
> Hi6220 mailbox supports up to 32 channels. Each channel is unidirectional
> with a maximum message size of 8 words. I/O is performed using register
> access (there is no DMA) and the cell raises an interrupt when messages
> are
On Mon, Feb 15, 2016 at 7:20 PM, Leo Yan wrote:
> Hi6220 mailbox supports up to 32 channels. Each channel is unidirectional
> with a maximum message size of 8 words. I/O is performed using register
> access (there is no DMA) and the cell raises an interrupt when messages
> are received.
>
> This
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