Add the compatible and clock ids of the sm1 audio clock controller
Reviewed-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
.../bindings/clock/amlogic,axg-audio-clkc.txt | 3 ++-
include/dt-bindings/clock/axg-audio-clkc.h | 10 ++
2 files changed, 12
for
* sm1_clk81_en
* sm1_sysclk_a_en
* sm1_sysclk_b_en
Changes since v1 [0]:
- Fix newline in the last patch
[0]: https://lkml.kernel.org/r/20190924153356.24103-1-jbru...@baylibre.com
[1]: https://lkml.kernel.org/r/20191001115511.17357-1-jbru...@baylibre.com>
Jerome Brunet (7):
dt-bindi
ss-through to
the audio peripheral clock provided by the main controller.
Reviewed-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 18 +++---
drivers/clk/meson/axg-audio.h | 3 ++-
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/d
Since the addition of the g12a, the last register is
AUDIO_CLK_SPDIFOUT_B_CTRL.
Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support")
Acked-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
On Tue 01 Oct 2019 at 20:53, Martin Blumenstingl
wrote:
>
> [...]
>> > +static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = {
>> > + .hws = {
>> > + [DDR_CLKID_DDR_PLL_DCO] = _ddr_pll_dco.hw,
>> > + [DDR_CLKID_DDR_PLL] =
side calls clk_core_get_rate() and
clk_core_get_accuracy(). Both are taking the prepare_lock.
So I don't get why clk_get_phase() should do thing differently from the
others, and not take the lock ?
>
> Cc: Douglas Anderson
> Cc: Heiko Stuebner
> Cc: Jerome Brunet
> Signed-off-by:
On Mon 23 Sep 2019 at 22:49, Martin Blumenstingl
wrote:
> Hi Jerome,
>
> On Mon, Sep 23, 2019 at 12:06 PM Jerome Brunet wrote:
>>
>> On Sat 21 Sep 2019 at 17:18, Martin Blumenstingl
>> wrote:
>>
>> > Meson8 and Meson8b SoCs embed a DDR clock
On Sat 21 Sep 2019 at 17:18, Martin Blumenstingl
wrote:
> The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the
> MMCBUS registers. There is no public documentation, but the u-boot GPL
> sources from the Amlogic BSP show that the DDR clock controller is
> identical on all three
On Sat 21 Sep 2019 at 17:04, Martin Blumenstingl
wrote:
> The meson-saradc driver manually sets the input clock for
> sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
> GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
> to sar_adc_clk_sel which will
On Thu 19 Sep 2019 at 11:36, Neil Armstrong wrote:
> This is the first serie of fixes for DVFS support on G12a:
> - Patch 1 fixes a rebase issue where a CLK_SET_RATE_NO_REPARENT
> appeared on the wrong clock and a SET_RATE_PARENT went missing
> - Patch 2 helps CCF use the right clock tree
Defining the number of each input type is no longer necessary since
we are not using the clk-input hack anymore
Fixes: 282420eed23f ("clk: meson: axg-audio: migrate to the new parent
description method")
Acked-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/a
Since the addition of the g12a, the last register is
AUDIO_CLK_SPDIFOUT_B_CTRL.
Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support")
Acked-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
Add the reset id of the sm1 audio clock controller
Reviewed-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
.../reset/amlogic,meson-g12a-audio-reset.h| 15 +++
1 file changed, 15 insertions(+)
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
b
Add the compatible and clock ids of the sm1 audio clock controller
Reviewed-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
.../bindings/clock/amlogic,axg-audio-clkc.txt | 3 ++-
include/dt-bindings/clock/axg-audio-clkc.h | 10 ++
2 files changed, 12
ss-through to
the audio peripheral clock provided by the main controller.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 18 +++---
drivers/clk/meson/axg-audio.h | 3 ++-
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/meson/axg-audio.c b/d
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 582 --
drivers/clk/meson/axg-audio.h | 22 +-
2 files changed, 574 insertions(+), 30 deletions(-)
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 1a4c50a29ad7
-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 1467 ++---
1 file changed, 782 insertions(+), 685 deletions(-)
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 4b34601342bb..ce8836776d1c 100644
patch
[0]: https://lkml.kernel.org/r/20190924153356.24103-1-jbru...@baylibre.com
Jerome Brunet (7):
dt-bindings: clk: axg-audio: add sm1 bindings
dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
clk: meson: axg-audio: remove useless defines
clk: meson: axg-audio: fix
On Thu 05 Sep 2019 at 16:26, Philipp Zabel wrote:
> Hi Jerome,
>
> On Thu, 2019-09-05 at 15:50 +0200, Jerome Brunet wrote:
>> This patchset adds the new arb reset lines for the sm1 SoC family
>> It has been tested on the sei610 platform.
>>
>> Changes s
On Fri 27 Sep 2019 at 08:40, Neil Armstrong wrote:
> On 27/09/2019 02:14, Stephen Boyd wrote:
>> Quoting Neil Armstrong (2019-09-19 03:25:17)
>>> This introduces the clk_invalidate_rate() call used to recalculate the
>>> rate and parent tree of a particular clock if it's known that the
>>>
On Fri 27 Sep 2019 at 11:36, Neil Armstrong wrote:
>>
>> static struct clk_regmap spdifout_clk_sel =
>> AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
>> @@ -502,7 +522,6 @@ static struct clk_regmap tdmout_c_lrclk =
>> AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
>>
On Fri 27 Sep 2019 at 11:37, Neil Armstrong wrote:
> On 27/09/2019 11:14, Neil Armstrong wrote:
>> On 24/09/2019 17:33, Jerome Brunet wrote:
>>
[...]
>> AUD_CLKID_TOP seems to be missing here
>
> Oh, yes it was exposed, do you need to it to be exposed
On Fri 27 Sep 2019 at 11:52, Jian Hu wrote:
> Hi, Jerome
>
> Thank you for review.
>
> On 2019/9/25 23:09, Jerome Brunet wrote:
>> On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
>>
>>> The Amlogic A1 clock includes three parts:
>>> peripheral clocks
On Fri 27 Sep 2019 at 05:11, Jian Hu wrote:
> Hi, Stephen
>
> Thank you for review
>
> On 2019/9/25 21:12, Stephen Boyd wrote:
>> Quoting Jian Hu (2019-09-25 04:44:48)
>>> The Amlogic A1 clock includes three parts:
>>> peripheral clocks, pll clocks, CPU clocks.
>>> sys pll and CPU clocks will
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
> The Amlogic A1 clock includes three parts:
> peripheral clocks, pll clocks, CPU clocks.
> sys pll and CPU clocks will be sent in next patch.
>
> Unlike the previous series, there is no EE/AO domain
> in A1 CLK controllers.
>
> Signed-off-by: Jian Hu
c,a1-clkc.yaml#;
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> +
> +title: Amlogic Meson A1 Clock Control Unit Device Tree Bindings
> +
> +maintainers:
> + - Neil Armstrong
> + - Jerome Brunet
> + - Jian Hu
> +
> +properties:
&
Provide the reset lines coming from the audio clock controller to
the audio devices of the g12 family
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 28 +-
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts
Add the compatible and clock ids of the sm1 audio clock controller
Signed-off-by: Jerome Brunet
---
.../bindings/clock/amlogic,axg-audio-clkc.txt | 3 ++-
include/dt-bindings/clock/axg-audio-clkc.h | 10 ++
2 files changed, 12 insertions(+), 1 deletion(-)
diff
-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 1467 ++---
1 file changed, 782 insertions(+), 685 deletions(-)
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 4b34601342bb..ce8836776d1c 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b
register
immediately after the original one, at the beginning of the register
space, shifting all the master clock register offsets.
The sm1 also introduce a few mux and divider on the top clock path,
possibly to lower the peripheral clocks of the audio blocks if
necessary.
Signed-off-by: Jerome Brunet
Since the addition of the g12a, the last register is
AUDIO_CLK_SPDIFOUT_B_CTRL.
Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support")
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
ss-through to
the audio peripheral clock provided by the main controller.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 19 ---
drivers/clk/meson/axg-audio.h | 3 ++-
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/meson/axg-audio.c b/d
Defining the number of each input type is no longer necessary since
we are not using the clk-input hack anymore
Fixes: 282420eed23f ("clk: meson: axg-audio: migrate to the new parent
description method")
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 4
1 file
if running on sm1 but the end
result did not save much lines and would have been a pain to maintain and
scale in the future
Instead I choose to re-arrange the driver to share the macros and declare
separate clocks for the clock which have changed.
Jerome Brunet (7):
dt-bindings: clk: axg-audio
Add the reset id of the sm1 audio clock controller
Signed-off-by: Jerome Brunet
---
.../reset/amlogic,meson-g12a-audio-reset.h| 15 +++
1 file changed, 15 insertions(+)
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
b/include/dt-bindings/reset
On Tue 24 Sep 2019 at 13:38, Ankur Tyagi wrote:
> Hi,
>
> I am no expert here but just looked at the patch and found few
> discrepancy that I have mentioned inline.
>
[...]
>
> Aren't all functions returning 0 always?
>
Yes, on purpose. This patch is an API conversion to let the init()
__clk_init_parent() will call the .get_parent() callback of the clock
so .init() must run before.
Fixes: 541debae0adf ("clk: call the clock init() callback before any other ops
callback")
Signed-off-by: Jerome Brunet
---
drivers/clk/clk.c | 26 +++---
1 file c
Add a terminate callback to the clk_ops to release the resources
claimed in .init()
Signed-off-by: Jerome Brunet
---
drivers/clk/clk.c| 7 ++-
include/linux/clk-provider.h | 3 +++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk.c b/drivers/clk
If the init callback is allowed to request resources, it needs a return
value to report the outcome of such a request.
Signed-off-by: Jerome Brunet
---
Sorry about the spam.
This patch change quite a few files so I have tried to Cc the
relevant people. Stephen, You may notice that I have
-...@mail.gmail.com
[1]: https://lkml.kernel.org/r/20190828102012.4493-1-jbru...@baylibre.com
Jerome Brunet (3):
clk: actually call the clock init before any other callback of the
clock
clk: let init callback return an error code
clk: add terminate callback to clk_ops
drivers/clk/clk.c
On Sat 21 Sep 2019 at 17:18, Martin Blumenstingl
wrote:
> Meson8 and Meson8b SoCs embed a DDR clock controller in their MMCBUS
> registers. This series:
> - adds support for this DDR clock controller (patches 0 and 1)
> - wires up the DDR PLL as input for two audio clocks (patches 2 and 3)
On Sat 21 Sep 2019 at 17:12, Martin Blumenstingl
wrote:
> The XTAL clock is an actual crystal on the PCB. Thus the meson8b clock
> driver should not register the XTAL clock - instead it should be
> provided via .dts and then passed to the clock controller.
>
> Skip the registration of the XTAL
On Sat 21 Sep 2019 at 17:12, Martin Blumenstingl
wrote:
> So far the HHI clock controller has been providing the XTAL clock on
> Amlogic Meson8/Meson8b/Meson8m2 SoCs.
> This is not correct because the XTAL is actually a crystal on the
> boards and the SoC has a dedicated input for it.
>
> This
On Sat 21 Sep 2019 at 17:04, Martin Blumenstingl
wrote:
> The meson-saradc driver manually sets the input clock for
> sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
> GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
> to sar_adc_clk_sel which will
On Sun 22 Sep 2019 at 14:41, Sasha Levin wrote:
> From: Jerome Brunet
>
> [ Upstream commit 2c4956bc1e9062e5e3c5ea7612294f24e6d4fbdd ]
>
> So far, forwarding the hw_params of the input to output relied on the
> .hw_params() callback of the cpu side of the codec2codec link to
On Wed 18 Sep 2019 at 14:36, Qianggui Song wrote:
> On 2019/9/17 22:07, Jerome Brunet wrote:
>>
>> On Tue 17 Sep 2019 at 13:51, Qianggui Song wrote:
>>>>> diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
>>>>> b/drivers/pinctrl/meson/pinctr
On Thu 19 Sep 2019 at 11:38, Neil Armstrong wrote:
> Make sure we always enable a PLL on a set_rate() when the PLL is
> flagged as critical.
>
> This fixes the case when the Amlogic G12A SYS_PLL gets disabled by the
> PSCI firmware when resuming from suspend-to-memory, in the case
> where the
On Tue 17 Sep 2019 at 13:51, Qianggui Song wrote:
>>> diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
>>> b/drivers/pinctrl/meson/pinctrl-meson.c
>>> index 8bba9d0..885b89d 100644
>>> --- a/drivers/pinctrl/meson/pinctrl-meson.c
>>> +++ b/drivers/pinctrl/meson/pinctrl-meson.c
>>> @@ -688,8
On Tue 17 Sep 2019 at 08:07, Qianggui Song wrote:
> Add pinctrl driver for Meson A1 Soc which share the same register layout of
> pinmux with previous Meson-G12A, however there is difference for gpio
> and pin config register in A1. The register layout is as below:
>
> /* first bank */
On Sat 07 Sep 2019 at 17:02, Martin Blumenstingl wrote:
> Hi Jianxin,
>
> On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote:
> [...]
>> > also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...)
>> > here
>> > aren't there any busses defined in the A1 SoC implementation or
The following commit has been merged into the irq/core branch of tip:
Commit-ID: abc08aac82af0c71e30b446575f5810c9cc11640
Gitweb:
https://git.kernel.org/tip/abc08aac82af0c71e30b446575f5810c9cc11640
Author:Jerome Brunet
AuthorDate:Thu, 29 Aug 2019 18:16:34 +02:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: b2fb4b77994abc1107c35547f3e123dce8e9f67d
Gitweb:
https://git.kernel.org/tip/b2fb4b77994abc1107c35547f3e123dce8e9f67d
Author:Jerome Brunet
AuthorDate:Thu, 29 Aug 2019 18:16:35 +02:00
Committer
On Thu 05 Sep 2019 at 13:40, Kevin Hilman wrote:
> Jerome Brunet writes:
>
>> Set the appropriate gpio interrupt controller compatible for the
>> sm1 SoC family. This newer version of the controller can now
>> trig irq on both edge of the input signal
>>
&
SM1 SoC family adds two new audio FIFOs with the related arb reset lines
Reviewed-by: Rob Herring
Signed-off-by: Jerome Brunet
---
.../devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt | 3 ++-
include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h| 2 ++
2 files changed, 4
This patchset adds the new arb reset lines for the sm1 SoC family
It has been tested on the sei610 platform.
Changes since v1 [0]:
* Fix the mistake on the number of reset as reported by Phililpp (thx)
[0]: https://lkml.kernel.org/r/20190820094625.13455-1-jbru...@baylibre.com
Jerome Brunet (2
Add the new arb reset lines of the SM1 SoC family
Signed-off-by: Jerome Brunet
---
drivers/reset/reset-meson-audio-arb.c | 43 +--
1 file changed, 40 insertions(+), 3 deletions(-)
diff --git a/drivers/reset/reset-meson-audio-arb.c
b/drivers/reset/reset-meson-audio
The register region size initially is too small to access all
the fifo registers.
Fixes: c59b7fe5aafd ("arm64: dts: meson: g12a: add audio fifos")
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6
on.
Signed-off-by: Jerome Brunet
---
.../boot/dts/amlogic/meson-g12-common.dtsi| 320 -
arch/arm64/boot/dts/amlogic/meson-g12.dtsi| 324 ++
2 files changed, 324 insertions(+), 320 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
b/arch
While the sm1 is very close to the g12a/b family, somethings apply
differently on the g12a/b and not the sm1. This introduce a new layer
of dtsi for part which apply to the g12a and g12b but not the sm1.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 7
The power domain declared in the g12a and g12b dtsi are the same.
Move the declaration of these power domains in the g12 common dtsi.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12.dtsi | 13 +
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 13
The register region size initially is too small to access all
the fifo registers.
Fixes: f2b8f6a93357 ("arm64: dts: meson-axg: add audio fifos")
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletion
the audio bus, which was at 0xff642000 on g12, has
moved 0xff66 on sm1. Overwriting the reg property was option but it
would have left confusing node names on the sm1.
Jerome Brunet (5):
arm64: dts: meson: axg: fix audio fifo reg size
arm64: dts: meson: g12: fix audio fifo reg size
arm64: dts
On sm1, the output routing bits have moved to CTRL2 register
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-fifo.c | 2 +-
sound/soc/meson/axg-fifo.h | 1 +
sound/soc/meson/axg-frddr.c | 73 +
3 files changed, 75 insertions(+), 1 deletion(-)
diff
The TODDR component, as it, has a maximum of 8 input. Depending on
the SoC, these may not all be connected or some input components may
not be supported
Instead of decribing only the connected inputs, describe them all
and let ASoC routing do the rest.
Signed-off-by: Jerome Brunet
---
sound
On sm1, the maximum number TODDR inputs is extended to 16.
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-toddr.c | 68 +
1 file changed, 68 insertions(+)
diff --git a/sound/soc/meson/axg-toddr.c b/sound/soc/meson/axg-toddr.c
index 2e9a2e5862ce
devices. Let's add the reset binding for the other
components, so we can describe this in DT. We'll use it later on
in the driver when/if needed.
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt | 5 -
Documentation/devicetree/bindings/sound/amlogic
Document the compatible strings of the audio devices of the sm1 SoC
family
Signed-off-by: Jerome Brunet
---
Documentation/devicetree/bindings/sound/amlogic,axg-fifo.txt | 4 +++-
Documentation/devicetree/bindings/sound/amlogic,axg-pdm.txt | 3 ++-
.../devicetree/bindings/sound/amlogic,axg
The FRDDR component, as it, has a maximum of 8 outputs. Depending on
the SoC, these may not all be connected.
Instead of decribing only the connected outputs of each SoC, describe
them all and let ASoC routing do the rest.
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-frddr.c | 32
The TDMIN component, as it, has a maximum of 16 input. Depending on
the SoC, these may not all be connected.
Instead of decribing only the connected inputs of each SoC, describe
them all and let ASoC routing do the rest.
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-tdmin.c | 47
On the sm1, the TDMOUT number of input is extended and the
the gain enable bit moved to accommodate this extension
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-tdmout.c | 103 ---
1 file changed, 84 insertions(+), 19 deletions(-)
diff --git a/sound/soc
This patchset prepare then add the audio support on the amlogic sm1
SoC family in ASoC.
This has been tested on sei610 platform. Since this platform does
not have spdif, this patchset does not include the change necessary
to support spdif input or output on the sm1.
Jerome Brunet (8):
ASoC
ce_type = "cpu";
> + compatible = "arm,cortex-a35";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <>;
> + };
> +
> + cpu1: cpu
Set the appropriate gpio interrupt controller compatible for the
sm1 SoC family. This newer version of the controller can now
trig irq on both edge of the input signal
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 5 +
1 file changed, 5 insertions(+)
diff
families
Signed-off-by: Jerome Brunet
---
drivers/irqchip/irq-meson-gpio.c | 52 +++-
1 file changed, 38 insertions(+), 14 deletions(-)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index dcdc23b9dce6..829084b568fa 100644
--- a/drivers
This patchset adds support for the new sm1 SoC family in the Amlogic gpio
interrupt controller.
Jerome Brunet (2):
dt-bindings: interrupt-controller: new binding for the meson sm1 SoCs
irqchip/meson-gpio: Add support for meson sm1 SoCs
.../amlogic,meson-gpio-intc.txt | 1
Update the dt-binding to add support for the sm1 SoC family in the
amlogic GPIO interrupt controller driver.
Signed-off-by: Jerome Brunet
---
.../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt| 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings
On Wed 28 Aug 2019 at 08:05, Kevin Hilman wrote:
> Jerome Brunet writes:
>
>> On Tue 27 Aug 2019 at 16:42, Kevin Hilman wrote:
>>
>>> Jerome Brunet writes:
>>>
>>>> This patchset adds the dedicated reset of the tdm formatters which
>>>&
On Tue 27 Aug 2019 at 15:35, Kevin Hilman wrote:
> Kevin Hilman writes:
>
>> Jerome Brunet writes:
>>
>>> On Mon 26 Aug 2019 at 09:25, Neil Armstrong wrote:
>>>
>>>> Following DVFS support for the Amlogic G12A and G12B SoCs, this serie
>&
On Tue 27 Aug 2019 at 16:42, Kevin Hilman wrote:
> Jerome Brunet writes:
>
>> This patchset adds the dedicated reset of the tdm formatters which
>> have been added on the g12a SoC family. Using these help with the channel
>> mapping when the formatter uses more than 1
On Mon 26 Aug 2019 at 09:25, Neil Armstrong wrote:
> Following DVFS support for the Amlogic G12A and G12B SoCs, this serie
> enables DVFS on the SM1 SoC for the SEI610 board.
>
> The SM1 Clock structure is slightly different because of the Cortex-A55
> core used, having the capability for each
On Thu 22 Aug 2019 at 16:24, Neil Armstrong wrote:
> Following DVFS support for the Amlogic G12A and G12B SoCs, this serie
> enables DVFS on the SM1 SoC for the SEI610 board.
>
> The SM1 Clock structure is slightly different because of the Cortex-A55
> core used, having the capability for each
Add the reset to the TDM formatters of the g12a. This helps
with channel mapping when a playback/capture uses more than 1 lane.
Reviewed-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 8
1 file changed, 8 insertions(+)
diff
/20190820121551.18398-1-jbru...@baylibre.com
Jerome Brunet (2):
arm64: dts: meson: g12a: audio clock controller provides resets
arm64: dts: meson: g12a: add reset to tdm formatters
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 9 +
1 file changed, 9 insertions(+)
--
2.21.0
The clock controller dedicated to audio clocks also provides reset lines
on the g12 SoC family
Reviewed-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson
On Tue 20 Aug 2019 at 17:39, Philipp Zabel wrote:
> Hi Jerome,
>
> thank you for the patch. Just one nitpick and one real issue below:
>
> On Tue, 2019-08-20 at 11:46 +0200, Jerome Brunet wrote:
>> Add the new arb reset lines of the SM1 SoC family
>>
>
The tohdmitx glue uses regmap MMIO so it should require it.
Fixes: c8609f3870f7 ("ASoC: meson: add g12a tohdmitx control")
Signed-off-by: Jerome Brunet
---
sound/soc/meson/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kco
Use the devm variant to get the formatter reset so it is properly freed
on device removal
Fixes: 751bd5db5260 ("ASoC: meson: axg-tdm-formatter: add reset")
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-tdm-formatter.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
The clock controller dedicated to audio clocks also provides reset lines
on the g12 SoC family
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
b/arch/arm64/boot/dts
controller. I've prepared a tag for you [0]
[0]: git://github.com/BayLibre/clk-meson.git - clk-meson-dt-v5.4-2
Jerome Brunet (2):
arm64: dts: meson: g12a: audio clock controller provides resets
arm64: dts: meson: g12a: add reset to tdm formatters
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
Add the reset to the TDM formatters of the g12a. This helps
with channel mapping when a playback/capture uses more than 1 lane.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic
On Mon 12 Aug 2019 at 14:32, Jerome Brunet wrote:
> This patchset adds support for the reset provided in the register space
> of the g12a audio clock controller
>
> Changes since v1 [0]:
> * Fix typo reported by Stephen
>
> [0]: https://lkml.kernel.org/r/20190
Add the new arb reset lines of the SM1 SoC family
Signed-off-by: Jerome Brunet
---
drivers/reset/reset-meson-audio-arb.c | 28 ---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/reset/reset-meson-audio-arb.c
b/drivers/reset/reset-meson-audio
SM1 SoC family adds two new audio FIFOs with the related arb reset lines
Signed-off-by: Jerome Brunet
---
.../devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt | 3 ++-
include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h| 2 ++
2 files changed, 4 insertions(+), 1 deletion
This patchset adds the new arb reset lines for the sm1 SoC family
Jerome Brunet (2):
reset: dt-bindings: meson: update arb bindings for sm1
reset: meson-audio-arb: add sm1 support
.../reset/amlogic,meson-axg-audio-arb.txt | 3 +-
drivers/reset/reset-meson-audio-arb.c | 28
On Mon 12 Aug 2019 at 14:19, Neil Armstrong wrote:
> Hi,
>
> On 12/08/2019 14:07, Jerome Brunet wrote:
>> The purpose of this patchset is to improve the support of the i2s
>> interface of the synopsys hdmi controller.
>>
>> Once applied, the interface sho
Add the documentation and bindings for the resets provided by the g12a
audio clock controller
Signed-off-by: Jerome Brunet
---
.../bindings/clock/amlogic,axg-audio-clkc.txt | 1 +
.../reset/amlogic,meson-g12a-audio-reset.h| 38 +++
2 files changed, 39 insertions(+)
create
On the g12a, the register space dedicated to the audio clock also
provides some resets. Let the clock controller register a reset
provider as well for this SoC family.
the axg SoC family does not appear to provide this feature.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c
This patchset adds support for the reset provided in the register space
of the g12a audio clock controller
Changes since v1 [0]:
* Fix typo reported by Stephen
[0]: https://lkml.kernel.org/r/20190703122614.3579-1-jbru...@baylibre.com
Jerome Brunet (2):
dt-bindings: clock: meson: add resets
setup the channel allocation provided by the generic hdmi-codec driver
Reviewed-by: Jonas Karlman
Signed-off-by: Jerome Brunet
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
b
When changing the audio hw params, reset the audio fifo to make sure
any old remaining data is flushed.
The databook mentions that such reset should be followed by a reset of
the i2s block to make sure the samples stay aligned
Reviewed-by: Jonas Karlman
Signed-off-by: Jerome Brunet
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