XCOMP_BV_COMPACTED_FORMAT defined by kernel.
Signed-off-by: Jing Liu
---
arch/x86/kvm/x86.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 1b404e4d7dd8..f115493f577d 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -4435,8 +4435,6
Bit 63 of the XCOMP_BV field indicates that the save area is in the
compacted format and the remaining bits indicate the states that have
space allocated in the save area, not only user states. Since
fpstate_init() has initialized xcomp_bv, let's just use that.
Signed-off-by: Jing Liu
---
arch
are the first to use 64B alignment.
Revise the runtime cpuid modification for this rule.
Signed-off-by: Jing Liu
---
arch/x86/kvm/cpuid.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 04a73c395c71..ee1fac0a865e 100644
--- a/arch/x86/kvm
Two XCR0 bits are defined for AMX to support XSAVE mechanism.
Bit 17 is for tilecfg and bit 18 is for tiledata.
Signed-off-by: Jing Liu
---
arch/x86/kvm/x86.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index bfbde877221e
the whole xstate using struct
kvm_xsave_extension buffer containing both static and dynamic
xfeatures. Reuse fill_xsave and load_xsave for both cases.
Signed-off-by: Jing Liu
---
arch/x86/include/uapi/asm/kvm.h | 5 +++
arch/x86/kvm/x86.c | 70
Intel introduces AMX architecture in SPR platform, which includes
AMX_TILE, AMX_INT8 and AMX_BF16 support.
Exposes these features to KVM guest.
Signed-off-by: Jing Liu
---
arch/x86/kvm/cpuid.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm
Intel's Extended Feature Disable (XFD) feature is an extension
to the XSAVE feature that allows an operating system to enable
a feature while preventing specific user threads from using
the feature. A processor that supports XFD enumerates
CPUID.(EAX=0DH,ECX=1):EAX[4] as 1.
Signed-off-by: Jing
.
For "current->thread.fpu", since host and guest probably have different
state and mask, it also need be switched to the right context when fpu
load and put.
Signed-off-by: Jing Liu
---
arch/x86/include/asm/kvm_host.h | 3 ++
arch/x86/kernel/fpu/init.c | 1 +
arch/x86/kern
and write without
vmexit. Add two slots for XFD MSRs as desired passthrough MSRs.
Signed-off-by: Jing Liu
---
arch/x86/kvm/vmx/vmx.c | 38 ++
arch/x86/kvm/vmx/vmx.h | 6 +-
arch/x86/kvm/x86.c | 6 ++
3 files changed, 49 insertions(+), 1 deletion
.intel.com/content/dam/develop/external/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf
[2]: AMX kernel series v3 https://lkml.org/lkml/2020/12/23/464
Jing Liu (7):
kvm: x86: Expose XFD CPUID to guest
kvm: x86: Introduce XFD MSRs as passthrough to guest
kvm: x8
On 7/15/2019 2:06 PM, Wanpeng Li wrote:
On Sat, 13 Jul 2019 at 18:40, Paolo Bonzini wrote:
On 11/07/19 07:49, Jing Liu wrote:
AVX512 BFLOAT16 instructions support 16-bit BFLOAT16 floating-point
format (BF16) for deep learning optimization.
Intel adds AVX512 BFLOAT16 feature in CooperLake
Hi Paolo,
Thanks for your reviewing! There also has Qemu patch sent here,
https://www.mail-archive.com/qemu-devel@nongnu.org/msg630359.html
Could you please review that? Thanks very much!
Jing
On 7/13/2019 6:37 PM, Paolo Bonzini wrote:
On 11/07/19 07:49, Jing Liu wrote:
AVX512 BFLOAT16
/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf.
Signed-off-by: Jing Liu
---
This patch depends on kernel patch https://lkml.org/lkml/2019/6/19/912
and Paolo's patch set https://lkml.org/lkml/2019/7/4/468.
arch/x86/kvm/cpuid.c | 12 +++-
1 file changed
On 7/10/2019 2:30 PM, Paolo Bonzini wrote:
On 08/07/19 09:07, Jing Liu wrote:
And when adding subleaf 1, plan to add codes,
case 1:
entry->eax |= kvm_cpuid_7_1_eax_x86_features;
entry->ebx = entry->ecx = entry->edx =0;
break;
What do you think?
Hi Paolo,
On 7/4/2019 10:07 PM, Paolo Bonzini wrote:
The has_leaf_count member was originally added for KVM's paravirtualization
CPUID leaves. However, since then the leaf count _has_ been added to those
leaves as well, so we can drop that special case.
Signed-off-by: Paolo Bonzini
[...]
Hi Paolo,
Thank you for refining the cpuid codes especially for case 7! It looks
much clear now!
On 7/4/2019 10:07 PM, Paolo Bonzini wrote:
CPUID function 7 has multiple subleafs. Instead of having nested
switch statements, move the logic to filter supported features to
a separate function,
Hi Paolo,
On 7/4/2019 10:07 PM, Paolo Bonzini wrote:
Rename it as well as __do_cpuid_ent and __do_cpuid_ent_emulated to have
"func" in its name, and drop the index parameter which is always 0.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/cpuid.c | 89
Hi Paolo,
On 6/24/2019 4:33 PM, Paolo Bonzini wrote:
On 24/06/19 05:10, Jing Liu wrote:
What do you think about @index in current function? Does it mean, we
need put cpuid from index to max subleaf to @entry[i]? If so, the logic
seems as follows,
if (index == 0) {
// Put subleaf 0
AG_SIGNIFCANT_INDEX;
+ ++*nent;
+ }
break;
}
Or you prefer that I update this into another version later?
Thanks!
Jing
On 6/20/2019 11:09 PM, Liu, Jing2 wrote:
Hi Paolo,
On 6/20/2019 8:16 PM, Paolo Bonzini wrote:
On 20/06/19 13:21,
/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf.
Signed-off-by: Jing Liu
---
arch/x86/kvm/cpuid.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index e18a9f9..10be53f 100644
/\
architecture-instruction-set-extensions-programming-reference.pdf
[2] https://lkml.org/lkml/2019/6/19/912
Jing Liu (1):
kvm: x86: Expose AVX512_BF16 feature to guest
arch/x86/kvm/cpuid.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
--
1.8.3.1
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