On Tue, Aug 30, 2016 at 03:01:51PM -0700, Andy Lutomirski wrote:
> On Wed, Aug 24, 2016 at 9:51 AM, Josh Cartwright wrote:
[..]
> >> diff --git a/kernel/fork.c b/kernel/fork.c
> >> index 52e725d4a866..05f7ef796fb4 100644
> >> --- a/kernel/fork.c
> >> +++
Hey Andy-
Small non-critical/potential future optimization comment below:
On Thu, Aug 11, 2016 at 02:35:21AM -0700, Andy Lutomirski wrote:
> If CONFIG_VMAP_STACK is selected, kernel stacks are allocated with
> vmalloc_node.
>
> grsecurity has had a similar feature (called
> GRKERNSEC_KSTACKOVERF
On Mon, May 02, 2016 at 12:08:50PM -0700, Florian Fainelli wrote:
> On 02/05/16 11:36, Josh Cartwright wrote:
> > On Fri, Apr 29, 2016 at 02:40:53PM +0200, Nicolas Ferre wrote:
> > [..]
> >>> static int macb_mii_init(struct macb *bp)
> >>> {
&
On Fri, Apr 29, 2016 at 02:40:53PM +0200, Nicolas Ferre wrote:
[..]
> > static int macb_mii_init(struct macb *bp)
> > {
> > struct macb_platform_data *pdata;
> > struct device_node *np;
> > - int err = -ENXIO, i;
> > + int err = -ENXIO;
> >
> > /* Enable management port */
> >
On Thu, Apr 28, 2016 at 07:34:59PM -0500, Josh Cartwright wrote:
> On Thu, Apr 28, 2016 at 11:23:15PM +0200, Andrew Lunn wrote:
> > On Thu, Apr 28, 2016 at 04:03:57PM -0500, Josh Cartwright wrote:
> > > On Thu, Apr 28, 2016 at 08:59:32PM +0200, Andrew Lunn wrote:
> > > &
On Thu, Apr 28, 2016 at 11:23:15PM +0200, Andrew Lunn wrote:
> On Thu, Apr 28, 2016 at 04:03:57PM -0500, Josh Cartwright wrote:
> > On Thu, Apr 28, 2016 at 08:59:32PM +0200, Andrew Lunn wrote:
> > > On Thu, Apr 28, 2016 at 01:55:27PM -0500, Nathan Sullivan wrote:
> > > &
On Thu, Apr 28, 2016 at 08:59:32PM +0200, Andrew Lunn wrote:
> On Thu, Apr 28, 2016 at 01:55:27PM -0500, Nathan Sullivan wrote:
> > On Thu, Apr 28, 2016 at 08:43:03PM +0200, Andrew Lunn wrote:
> > > > I agree that is a valid fix for AT91, however it won't solve our
> > > > problem, since
> > > > w
On Thu, Apr 28, 2016 at 09:19:47AM -0500, Nathan Sullivan wrote:
> Since of_mdiobus_register and mdiobus_register will scan automatically,
This is only partially true. of_mdiobus_register() only scans for PHYs
with device tree presence (starting with nodes which specify an address,
then continuin
On Fri, Apr 01, 2016 at 01:13:06AM +0530, punnaiah choudary kalluri wrote:
> Hi,
>
> We are using the pl353 smc controller for interfacing the nand in our zynq
> SOC.
> The driver for this controller is currently under mainline review.
> Recently we are moved to 4.4 kernel and observing issues wi
On Tue, Mar 15, 2016 at 10:50:31PM -0400, Paul Gortmaker wrote:
> On Tue, Mar 15, 2016 at 7:25 PM, Paul Gortmaker
> wrote:
> > On Tue, Mar 15, 2016 at 5:45 PM, Paul Gortmaker
> > wrote:
> >> On Mon, Mar 14, 2016 at 11:49 AM, Steven Rostedt
> >> wrote:
> >>>
> >>> Dear RT Folks,
> >>>
> >>> 3.14
Hey Kyle-
On Mon, Mar 14, 2016 at 04:55:08PM -0500, Kyle Roeschley wrote:
> From: Gratian Crisan
From what I understand, this was mostly Aaron's work, so he should get
authorship. I could be wrong, though, but you'll want to check.
> These changes add support for PIEs (physical interface eleme
On Mon, Mar 14, 2016 at 03:05:59PM -0700, Greg KH wrote:
> On Mon, Mar 14, 2016 at 04:54:32PM -0500, Kyle Roeschley wrote:
> > From: Jeff Westfahl
> >
> > This driver introduces support for hardware features of National
> > Instruments real-time controllers. This is an ACPI device that exposes
>
On Tue, Mar 08, 2016 at 06:52:06PM +0100, Sebastian Andrzej Siewior wrote:
> * Daniel Wagner | 2016-03-08 16:59:13 [+0100]:
>
> >Hi,
> Hi,
>
> >As Peter correctly pointed out in [1] a simple conversion from
> >wait to swait in completion.c wont work. I played a bit around and
> >came up with this
)
(kthread_worker_fn) from (kthread+0xd0/0xe8)
(kthread) from (ret_from_fork+0x14/0x2c)
Reported-by: Sean Nyekjaer
Fixes: 9e6f4ca3e567 ("sc16is7xx: use kthread_worker for tx_work and irq")
Cc: sta...@vger.kernel.org # v4.1+
Signed-off-by: Josh Cartwright
---
drivers/tty/serial/sc16is7xx.c | 2
Hey Alan-
First off, thanks for all of your (and others') work on this.
On Fri, Feb 05, 2016 at 03:29:58PM -0600, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> New bindings document for FPGA Region to support programming
> FPGA's under Device Tree control
>
> Signed-off-by: Alan Tul
ously reserved. It is added
in the Zynq-7000 AP SoC Technical Reference Manual (TRM) v1.5 as
"Reserved".
Thanks to Jaeden Amero for initial debugging and triage efforts.
Signed-off-by: Josh Cartwright
---
arch/arm/mach-zynq/slcr.c | 4
1 file changed, 4 insertions(+)
diff --git a/arc
zing it to the proper value prior to bringing up L2.
You can find more information about this bug in AR#54190[1].
1: http://www.xilinx.com/support/answers/54190.html
Josh Cartwright (2):
ARM: zynq: initialize slcr mapping earlier
ARM: zynq: address L2 cache data corruption
arch/arm/mach-zyn
In preparation for performing additional configuration prior to bringing
up L2, move the slcr initialization earlier in the boot process.
Signed-off-by: Josh Cartwright
---
arch/arm/mach-zynq/common.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-zynq
On Mon, Dec 07, 2015 at 11:58:33AM +0100, Neil Armstrong wrote:
> On some platforms, the macb integration does not use the USRIO
> register to configure the (R)MII port and clocks.
> When the register is not implemented and the MACB error signal
> is connected to the bus error, reading or writing t
On Wed, Nov 18, 2015 at 11:05:44PM +0200, Ioan-Adrian Ratiu wrote:
> On Wed, 18 Nov 2015 21:37:42 +0100 (CET)
> Jiri Kosina wrote:
>
> > On Wed, 18 Nov 2015, Ioan-Adrian Ratiu wrote:
> >
> > > The critical section protected by usbhid->lock in hid_ctrl() is too
> > > big and in rare cases causes
On Wed, Oct 28, 2015 at 12:59:16PM -0500, Josh Cartwright wrote:
> On Wed, Oct 28, 2015 at 12:03:41PM -0500, atull wrote:
> > On Wed, 28 Oct 2015, Moritz Fischer wrote:
> >
> > > On Wed, Oct 28, 2015 at 9:18 AM, Josh Cartwright wrote:
> > > > On Wed, Oct
On Wed, Oct 28, 2015 at 12:03:41PM -0500, atull wrote:
> On Wed, 28 Oct 2015, Moritz Fischer wrote:
>
> > On Wed, Oct 28, 2015 at 9:18 AM, Josh Cartwright wrote:
> > > On Wed, Oct 28, 2015 at 08:37:51AM -0700, Moritz Fischer wrote:
> > >> On Wed, Oct 28, 2015 a
On Wed, Oct 28, 2015 at 08:37:51AM -0700, Moritz Fischer wrote:
> On Wed, Oct 28, 2015 at 3:07 AM, Josh Cartwright wrote:
> > On Tue, Oct 27, 2015 at 05:09:12PM -0500, at...@opensource.altera.com wrote:
> >> From: Alan Tull
> >>
> >> The Simple FPGA bus use
On Tue, Oct 27, 2015 at 05:09:12PM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> The Simple FPGA bus uses the FPGA Manager Framework and the
> FPGA Bridge Framework to provide a manufactorer-agnostic
> interface for reprogramming FPGAs that is Device Tree
> Overlays-based.
Do y
On Tue, Oct 27, 2015 at 04:15:59PM -0700, Paul E. McKenney wrote:
> On Tue, Oct 27, 2015 at 08:27:53AM -0700, Eric Dumazet wrote:
> > On Tue, 2015-10-27 at 12:02 -0300, Arnaldo Carvalho de Melo wrote:
[..]
> > > The first suggestion, with it disabled by default seems to be the most
> > > flexible t
On Mon, Oct 26, 2015 at 05:44:22PM -0700, Paul E. McKenney wrote:
> On Mon, Oct 26, 2015 at 02:14:55PM -0500, Josh Cartwright wrote:
> > This reverts commit be3fc413da9eb17cce0991f214ab019d16c88c41.
> >
> > While the use of synchronize_rcu_expedited() might make
> > syn
op_machine() mechanism).
Without be3fc413da9e reverted, we can observe a latency spike up to 30us
with cyclictest by rapidly unplugging/reestablishing an ethernet link.
Cc: Eric Dumazet
Cc: Paul E. McKenney
Cc: David S. Miller
Signed-off-by: Josh Cartwright
---
net/core/dev.c | 5 +
1 file
proper resend
would likely be the easiest way for him to pick it up.
Feel free to add by Reviewed-by as well:
Reviewed-by: Josh Cartwright
Thanks,
Josh
> > ---
> > drivers/fpga/socfpga.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --g
On Tue, Oct 20, 2015 at 10:19:56AM -0700, Moritz Fischer wrote:
> This gets rid of the code to strip away the header and byteswap,
> as well as the check for the sync word.
>
> Signed-off-by: Moritz Fischer
Simpler is better.
Reviewed-by: Josh Cartwright
Josh
--
To unsubscri
On Mon, Oct 19, 2015 at 04:09:09PM +0200, Michal Simek wrote:
> On 10/18/2015 07:53 PM, Josh Cartwright wrote:
> > On Fri, Oct 16, 2015 at 03:42:29PM -0700, Moritz Fischer wrote:
[..]
> >> @@ -294,6 +294,11 @@
> >>devcfg: devcfg@f8007000 {
> >>
On Fri, Oct 16, 2015 at 03:42:27PM -0700, Moritz Fischer wrote:
> Hi all,
>
> I've tried to address most of the feedback that was brought up,
> the one thing I haven't looked at was the firmware format part,
> since that was still in discussion.
> So I'm still open to suggestions on how to handle
Hey Moritz-
On Fri, Oct 16, 2015 at 03:42:30PM -0700, Moritz Fischer wrote:
> This commit adds FPGA Manager support for the Xilinx Zynq chip.
> The code borrows some from the xdevcfg driver in Xilinx'
> vendor tree.
>
> Signed-off-by: Moritz Fischer
> ---
>
> v2:
> - Replaced locking error fla
On Fri, Oct 16, 2015 at 03:42:29PM -0700, Moritz Fischer wrote:
> Added addtional nodes required for FPGA Manager operation
> of the Xilinx Zynq Devc configuration interface.
>
> Reviewed-by: Sören Brinkmann
> Signed-off-by: Moritz Fischer
> ---
>
> v2: No changes
>
> ---
> arch/arm/boot/dts/
ain "xlnx,zynq-devcfg-1.0"
> +- reg: base address and size for memory mapped io
> +- interrupts:interrupt for the FPGA manager device
> +- clocks:phandle for clocks required operation
Technically a "clock specifier", but
Hello,
I've got a few comments below.
On Sat, Oct 17, 2015 at 12:52:18PM +0530, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada
> Signed-off-by: Ravi Kiran Gummaluri
> ---
> Added MSI domain implementation for hand
On Wed, Oct 07, 2015 at 03:33:50AM +, Anup Patel wrote:
> From: Florian Fainelli [mailto:f.faine...@gmail.com]
> > On 06/10/15 15:25, Scott Branden wrote:
[..]
> > Then instead of adding a "reset flag" to Device Tree, another approach
> > could be
> > to put the desired or currently configured
Hey Moritz-
On Fri, Oct 09, 2015 at 12:45:07AM +0200, Moritz Fischer wrote:
> This commit adds FPGA Manager support for the Xilinx Zynq chip.
> The code heavily borrows from the xdevcfg driver in Xilinx'
> vendor tree.
>
> Signed-off-by: Moritz Fischer
[..]
> +++ b/drivers/fpga/zynq-fpga.c
[..]
On Fri, Oct 09, 2015 at 12:45:05AM +0200, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer
> ---
> .../bindings/fpga/xilinx-zynq-fpga-mgr.txt | 26
> ++
> 1 file changed, 26 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/fpga/xilinx-zynq
On Fri, Oct 02, 2015 at 09:45:37AM +0200, Maciek Borzecki wrote:
> On 10/01 09:47, Josh Cartwright wrote:
> > On Thu, Oct 01, 2015 at 04:04:31PM +0200, Maciek Borzecki wrote:
> > > The patch adds LED triggers for indicating an activity on a selected
> > > device. The
Hello Maciek-
Some architectural questions below:
On Thu, Oct 01, 2015 at 04:04:31PM +0200, Maciek Borzecki wrote:
> The patch adds LED triggers for indicating an activity on a selected
> device. The drivers that intend to use triggers need to register
> respective devices using ledtrig_dev_add()
On Tue, Sep 29, 2015 at 01:00:45PM -0700, Brian Norris wrote:
> On Tue, Sep 29, 2015 at 12:55:39PM -0700, Brian Norris wrote:
>
> ...
>
> Seems Ben Shelton has moved on to other things...
He has, but there are others paying attention who want this feature :).
Josh
signature.asc
Description:
Hello Alexandre-
Few comments below.
On Sat, Sep 26, 2015 at 03:54:39PM +0200, Alexandre Belloni wrote:
> This driver supports the following functions:
> - reading and settings time
> - alarms when connected to an IRQ
> - reading and clearing the voltage low flags
> - nvram
>
> Signed-off-by
On Wed, Sep 23, 2015 at 12:10:13PM -0500, atull wrote:
> On Tue, 22 Sep 2015, Josh Cartwright wrote:
[..]
> > > +struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
> > > +{
> > > + struct fpga_manager *mgr;
> > > + struct device *dev;
> >
On Tue, Sep 22, 2015 at 10:21:11AM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Add driver to fpga manager framework to allow configuration
> of FPGA in Altera SoCFPGA parts.
>
> Signed-off-by: Alan Tull
> Acked-by: Michal Simek
> Acked-by: Moritz Fischer
[..]
> +++ b/drive
On Tue, Sep 22, 2015 at 10:21:10AM -0500, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> API to support programming FPGA's.
>
> The following functions are exported as GPL:
> * fpga_mgr_buf_load
>Load fpga from image in buffer
>
> * fpga_mgr_firmware_load
>Request firmware and
On Thu, Aug 20, 2015 at 10:48:38AM +0800, Dongsheng Yang wrote:
> On 08/20/2015 04:35 AM, Richard Weinberger wrote:
> >This is a partial revert of commit d7f0b70d30ffb9bbe6b8a3e1035cf0b79965ef53
> >("UBIFS: Add security.* XATTR support for the UBIFS").
>
> Hi Richard,
> What about a full rev
On Fri, Jul 10, 2015 at 07:06:23PM -0400, Chris Metcalf wrote:
> On 7/10/2015 6:45 PM, Josh Cartwright wrote:
> >>+static inline const struct cpumask *housekeeping_cpumask(void)
> >>>+{
> >>>+#ifdef CONFIG_NO_HZ_FULL
> >>>+ if (tick_nohz_full_ena
On Fri, Jul 10, 2015 at 03:37:25PM -0400, Chris Metcalf wrote:
> Normally the tilegx networking shim sends irqs to all the cores
> to distribute the load of processing incoming-packet interrupts,
> so that you can get to multiple Gb's of traffic inbound.
>
> However, in nohz_full mode we don't wan
On Mon, Jun 08, 2015 at 11:38:35PM +0530, Punnaiah Choudary Kalluri wrote:
> The following patches add arm pl353 static memory controller driver for
> xilinx zynq soc. The arm pl353 smc supports two interfaces i.e nand and
> nor/sram memory interfaces. The current implementation supports only a
> s
On Wed, Jul 08, 2015 at 01:54:34PM +0200, Richard Cochran wrote:
> On Mon, Jul 06, 2015 at 03:44:58PM -0500, Josh Cartwright wrote:
> > It's difficult to make too many judgements without seeing how a driver
> > might implement this; is there another patchset that shows how a d
On Thu, Jul 02, 2015 at 06:14:48PM -0700, Christopher Hall wrote:
> * getsynctime64()
Hello Christopher-
A couple comments below.
>
> This takes 2 arguments referring to system and device time
>
> With this callback drivers may provide both system time and device time
> to ensure precise corre
Hey Moritz-
Just a couple more nits, nothing big. Looks pretty clean!
On Tue, Jun 23, 2015 at 11:00:02AM -0700, Moritz Fischer wrote:
> The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
> interprocessor communication via AXI4 memory mapped / AXI4 stream
> interfaces.
>
> It is singl
On Mon, Jun 01, 2015 at 09:18:26AM -0700, Moritz Fischer wrote:
> Changes from v3:
> - Changed reg size to 0x100
>
> Changes from v2:
> - Addressed Michal's stylistic comments
> - Fixed typo in compatible string
>
> Changes from v1:
> - Added common clock framework support
>
> Changes from v0:
>
Hey Moritz-
A few comments below:
On Mon, Jun 01, 2015 at 09:18:27AM -0700, Moritz Fischer wrote:
[..]
> +++ b/drivers/mailbox/mailbox-xilinx.c
> @@ -0,0 +1,352 @@
> +/*
> + * Copyright (c) 2015, National Instruments Corp. All rights reserved.
> + *
> + * Driver for the Xilinx LogiCORE mailbox IP
Something tells me that Russell's patch system won't like to accept a
patch with a duplicate ID (although, I could be wrong).
On Tue, May 12, 2015 at 08:22:01AM +0200, Michal Simek wrote:
> From: Thomas Betker
>
> This patch is based on the
> commit 1a8e41cd672f ("ARM: 6395/1: VExpress: Set bit
On Tue, Apr 28, 2015 at 09:14:26AM +0530, punnaiah choudary kalluri wrote:
> On Tue, Apr 28, 2015 at 8:52 AM, Brian Norris
> wrote:
> > On Tue, Apr 28, 2015 at 08:18:12AM +0530, punnaiah choudary kalluri wrote:
> >> On Tue, Apr 28, 2015 at 4:53 AM, Brian Norris
> >> wrote:
[..]
> >> Agree that
Hey Punnaiah-
A few nitpicks here, in case you'll be spinning up a new version of your
patchset.
On Mon, Apr 13, 2015 at 09:41:51PM +0530, Punnaiah Choudary Kalluri wrote:
> Add pl353 static memory controller devicetree binding information.
>
> Signed-off-by: Punnaiah Choudary Kalluri
[..]
> @@
+Richard, who, when not being trolled on IRC, has been working on
UBI(FS) stuff.
On Thu, Apr 23, 2015 at 12:48:53PM +1000, Iwo Mergler wrote:
> On Thu, 23 Apr 2015 03:29:44 +1000
> Ben Shelton wrote:
> > We'd like to upstream our patch, but my concern is that UBIFS behaves
> > differently when it
On Wed, Apr 22, 2015 at 11:11:34AM +0800, Pi-Cheng Chen wrote:
[..]
> >> +config ARM_MT8173_CPUFREQ
> >> + bool "Mediatek MT8173 CPUFreq support"
> >> + depends on ARCH_MEDIATEK && REGULATOR
> >
> > I think you want to 'select REGULATOR' here; because REGULATOR isn't
> > a user-visible opti
On Mon, Apr 20, 2015 at 05:27:26PM +0800, pi-cheng.chen wrote:
> This patch implements MT8173 specific cpufreq driver with OPP table defined
> in the driver code.
>
> Signed-off-by: pi-cheng.chen
> ---
> drivers/cpufreq/Kconfig.arm | 6 +
> drivers/cpufreq/Makefile | 1 +
> driv
By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.
Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: Josh Cartwright
---
v3 -> v4: Document rest
On Thu, Mar 19, 2015 at 03:01:13PM +0100, Michal Simek wrote:
> On 03/19/2015 02:33 PM, Josh Cartwright wrote:
[..]
> > /**
> > - * zynq_slcr_system_reset - Reset the entire system.
> > + * zynq_slcr_system_restart - Restart the entire system.
> > */
> >
Ugh.
On Thu, Mar 19, 2015 at 08:33:53AM -0500, Josh Cartwright wrote:
> The SLCR is unconditionally unlocked early on boot in zynq_slcr_init()
> and not unlocked. As such, it is not necessary to explicitly unlock in
^ever re-locked.
Can you fix this up when you apply?
Thanks,
On Thu, Mar 19, 2015 at 02:19:01PM +0100, Michal Simek wrote:
> On 03/19/2015 01:44 PM, Josh Cartwright wrote:
> > On Thu, Mar 19, 2015 at 11:44:23AM +0100, Michal Simek wrote:
> >> On 02/27/2015 04:09 PM, Josh Cartwright wrote:
> > [..]
> >>> +++ b/arch/arm/m
The SLCR is unconditionally unlocked early on boot in zynq_slcr_init()
and not unlocked. As such, it is not necessary to explicitly unlock in
the restart codepath.
Signed-off-by: Josh Cartwright
---
arch/arm/mach-zynq/slcr.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/arm
By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.
Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: Josh Cartwright
---
v2 -> v3: Don't
On Thu, Mar 19, 2015 at 11:44:23AM +0100, Michal Simek wrote:
> On 02/27/2015 04:09 PM, Josh Cartwright wrote:
[..]
> > +++ b/arch/arm/mach-zynq/slcr.c
> > @@ -15,6 +15,7 @@
> > */
> >
> > #include
> > +#include
> > #include
> >
On Fri, Feb 27, 2015 at 09:09:29AM -0600, Josh Cartwright wrote:
> By making use of the restart_handler chain mechanism, the SLCR-based
> reset mechanism can be prioritized amongst other mechanisms available on
> a particular board.
Have either of you had a chance to look at this yet
On Tue, Mar 10, 2015 at 07:46:23PM +0530, Punnaiah Choudary Kalluri wrote:
> Device-tree binding documentation for Xilinx ZDMA Engine
>
> Signed-off-by: Punnaiah Choudary Kalluri
> ---
Hey Punnaiah-
Was this intended to be sent out with a driver?
> .../devicetree/bindings/dma/xilinx/zdma.txt
The configurations are not modified by the driver. Make them 'const' so
that they may be placed in a read-only section.
Signed-off-by: Josh Cartwright
---
drivers/net/ethernet/cadence/macb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ne
Hey Michal-
I've got a few comments on this.
On Mon, Feb 23, 2015 at 12:37:26PM +0100, Michal Simek wrote:
> Xilinx Microblaze is placed in programmable logic on Xilinx
> Zynq architecture. Driver requires specific HW setting
> described in DT binding.
>
> Signed-off-by: Michal Simek
[..]
> +++
Hello!
I looked through your driver and have some comments.
On Mon, Mar 02, 2015 at 11:25:11PM +0530, Kedareswara rao Appana wrote:
> This is the driver for the AXI Direct Memory Access (AXI DMA)
> core, which is a soft Xilinx IP core that provides high-
> bandwidth direct memory access between m
By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.
Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: Josh Cartwright
---
v1 -> v2: Also d
By making use of the restart_handler chain mechanism, the SLCR-based
reset mechanism can be prioritized amongst other mechanisms available on
a particular board.
Choose a default high-ish priority of 192 for this restart mechanism.
Signed-off-by: Josh Cartwright
---
arch/arm/mach-zynq/common.c
On Tue, Feb 17, 2015 at 04:52:45PM -0800, Bryan Wu wrote:
> On Tue, Feb 17, 2015 at 4:32 PM, Ricardo Ribalda Delgado
[..]
> > Then we have TWO gpios chip. Each of them have a led named red. When
> > the second gpio-led is probed we have an error. Everything else
> > (address offset, phandle, device
From: Kalle Valo
commit 31b9cc9a873dcab161999622314f98a75d838975 upstream.
Jason noticed that with Yocto GCC 4.8.1 ath6kl crashes with this iperf command:
iperf -c $TARGET_IP -i 5 -t 50 -w 1M
The crash was:
Unable to handle kernel paging request at virtual address 1a48
pgd = 80004000
[1a4
us
justification.
Therefore,
Acked-by: Josh Cartwright
Josh
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Hey Gilad-
On Mon, Feb 09, 2015 at 03:51:12PM -0700, Gilad Avidov wrote:
> Qualcomm PMIC Arbiter version-2 changes from version-1 are:
>
> - Some different register offsets.
> - New channel register space, one per PMIC peripheral (ppid).
> All tx traffic uses these channels.
> - New observer re
On Thu, Feb 12, 2015 at 10:26:16AM +, Mark Rutland wrote:
> On Thu, Feb 12, 2015 at 10:22:07AM +, Michal Simek wrote:
> > Add OCM node for all zynq boards. OCM location
> > can changed but for all current boards this
> > is the location where OCM is.`
> >
> > Signed-off-by: Michal Simek
>
The IPQ8064 also includes an RPM following the same message structure as
other chips. In addition, it supports a few new resource types to
support the NSS fabric clocks and the SMB208/SMB209 regulators found on
the reference boards.
Signed-off-by: Josh Cartwright
---
drivers/mfd/qcom_rpm.c
The IPQ8064 reference boards make use of SMB208 regulators which are
controlled by RPM. Implement support for these regulators in the RPM
regulator driver.
Signed-off-by: Josh Cartwright
---
drivers/regulator/qcom_rpm-regulator.c | 19 +++
1 file changed, 19 insertions(+)
diff
The IPQ8064 SoC has several RPM-controlled resources, an NSS fabrick
clock and four regulator resources. Provide definitions for them.
Signed-off-by: Josh Cartwright
---
Documentation/devicetree/bindings/mfd/qcom-rpm.txt | 6 +-
include/dt-bindings/mfd/qcom-rpm.h | 6
regulator driver
to support the SMB208.
This patchset is based ontop of v7 of Bjorne Andersson's RPM patchset [1].
1:
http://lkml.kernel.org/r/1411428329-23172-1-git-send-email-bjorn.anders...@sonymobile.com
Josh Cartwright (3):
mfd: devicetree: qcom_rpm: document IPQ8064 resources
cc1: some warnings being treated as errors
>
> Looking at the git logs it seems this was added via:
>
> commit cf1fc187628913070c3e418ce0e205732435aa2f
> Author: Josh Cartwright
> Date: Tue Sep 23 15:59:53 2014 -0500
>
> pinctrl: qcom: use restart_notifier mechanism for ps_hold
>
On Wed, Oct 08, 2014 at 09:18:44PM +0200, Nicolas Dechesne wrote:
> Georgi,
>
> On Tue, Sep 2, 2014 at 5:40 PM, Georgi Djakov wrote:
> > Enable support for the two SD host controllers on the APQ8084 platform
> > by adding the required nodes to the DT files.
> > On the IFC6540 board, the first con
On Tue, Oct 07, 2014 at 04:07:43PM -0700, Stephen Boyd wrote:
> On 10/07/2014 03:10 PM, Josh Cartwright wrote:
> >On Thu, Oct 02, 2014 at 12:08:38PM -0700, Stephen Boyd wrote:
[..]
> >>I'm thinking:
> >>
> >> timer@200a000 {
> >&g
On Thu, Oct 02, 2014 at 12:08:38PM -0700, Stephen Boyd wrote:
[..]
> On 10/01/14 11:15, Josh Cartwright wrote:
> > The percpu-ness of the two WDTs makes configuration even more
> > interesting, as it's possible you'd want to independently configure
> > timeo
Hey Stephen-
Thanks for taking a look.
On Wed, Oct 01, 2014 at 10:28:55AM -0700, Stephen Boyd wrote:
> On 10/01, Josh Cartwright wrote:
> > @@ -96,6 +104,13 @@
> > cpu-offset = <0x8>;
> > };
> >
Describe the Krait Processor Sub-system (KPSS) Watchdog timer in the
MSM8960 device tree. Also, add a fixed-clock description of SLEEP_CLK,
which will do for now.
Signed-off-by: Josh Cartwright
---
arch/arm/boot/dts/qcom-msm8960.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff
Describe the Krait Processor Sub-system (KPSS) Watchdog timer in the
APQ8064 device tree. Also, add a fixed-clock description of SLEEP_CLK,
which will do for now.
Signed-off-by: Josh Cartwright
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff
Now that the Krait Processor Sub-system (KPSS) Watchdog driver has been pulled
into Wim's tree destined for 3.18, add descriptions of the WDT in the relevant
device trees, and include the driver in qcom_defconfig.
Josh Cartwright (4):
ARM: qcom: add QCOM_WDT driver to qcom_defconfig
ARM:
Describe the Krait Processor Sub-system (KPSS) Watchdog timer in the
IPQ8064 device tree. Also, add a fixed-clock description of SLEEP_CLK,
which will do for now.
Signed-off-by: Josh Cartwright
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff
Select QCOM_WDT to allow for the watchdog driver to be built.
Signed-off-by: Josh Cartwright
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 8c7da33..80bad9a 100644
--- a/arch/arm
Add a driver for the watchdog timer block found in the Krait Processor
Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
Signed-off-by: Josh Cartwright
---
drivers/watchdog/Kconfig| 13
drivers/watchdog/Makefile | 1 +
drivers/watchdog/qcom-wdt.c | 186
The Qualcomm Krait Processor Sub-system (KPSS) contains one or more
instances of the WDT. Provide documentation on how to describe these in
the device tree.
Signed-off-by: Josh Cartwright
---
.../devicetree/bindings/watchdog/qcom-wdt.txt | 24 ++
1 file changed, 24
ff-by: Josh Cartwright
---
drivers/watchdog/qcom-wdt.c | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
index 68db322..aa85618 100644
--- a/drivers/watchdog/qcom-wdt.c
+++ b/drivers/watchdog/qcom-
hanges since v1:
- Make use of clock API instead of using a 'clock-frequency' property
- Setup default timeout of 30 seconds when one is not specified
- Add remove() function to allow for module unloading
- Don't acquire/release watchdog lock on restart
- Don't b
On Thu, Sep 25, 2014 at 11:41:49AM -0700, Guenter Roeck wrote:
> On Thu, Sep 25, 2014 at 12:48:53PM -0500, Josh Cartwright wrote:
> > The WDT's BITE_TIME warm-reset behavior can be leveraged as a last
> > resort mechanism for triggering chip reset. Usually, other restart
On Thu, Sep 25, 2014 at 11:43:14AM -0700, Guenter Roeck wrote:
> On Thu, Sep 25, 2014 at 12:48:52PM -0500, Josh Cartwright wrote:
[..]
> > +- timeout-sec : shall contain the default watchdog timeout in seconds,
> > +if unset, the default timeout is 30 secon
On Thu, Sep 25, 2014 at 11:38:57AM -0700, Guenter Roeck wrote:
> On Thu, Sep 25, 2014 at 12:48:51PM -0500, Josh Cartwright wrote:
> > Add a driver for the watchdog timer block found in the Krait Processor
> > Subsystem (KPSS) on the MSM8960, APQ8064, and IPQ8064.
> >
&g
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