Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
v5:
* Fix copy/paste error when killing qcom_ipq806x_sata_delay_us
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2
On Jun 17, 2014, at 7:25 AM, Bartlomiej Zolnierkiewicz
wrote:
>
> Hi,
>
> On Friday, June 13, 2014 11:16:03 AM Kumar Gala wrote:
>> Add support for the Qualcomm AHCI SATA controller that exists on several
>> SoC and specifically the IPQ806x family of chips.
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so
On Jun 17, 2014, at 7:25 AM, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Friday, June 13, 2014 11:16:03 AM Kumar Gala wrote:
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v5:
* Fix copy/paste error when killing qcom_ipq806x_sata_delay_us
v4:
* removed qcom_ipq806x_sata_delay_us as it was only used one
v3:
* Added
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v3:
* Added comment about
, 2014 at 03:13:22PM -0500, Kumar Gala wrote:
WARNING: drivers/tty/built-in.o(.data+0x3544): Section mismatch in
reference from the variable msm_platform_driver to the function
.init.text:msm_serial_probe()
The variable msm_platform_driver references
the function __init msm_serial_probe
On Jun 16, 2014, at 5:04 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 13 June 2014 12:48 AM, Kumar Gala wrote:
>> Add a PHY driver for uses with AHCI based SATA controller driver on the
>> IPQ806x family of SoCs.
>>
>> Signed-off-by: Kumar Ga
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v3:
* Added Kconfig HAS_IOMEM dep
* re-ordered probe function so phy_provider_register is last
v2:
* dropped unused dev pointer in struct
On Jun 16, 2014, at 5:04 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi,
On Friday 13 June 2014 12:48 AM, Kumar Gala wrote:
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers
On Jun 12, 2014, at 2:34 PM, Andy Gross wrote:
> This patch adds support for v1.1.1 of the SPI QUP controller.
>
> Signed-off-by: Andy Gross
> ---
> .../devicetree/bindings/spi/qcom,spi-qup.txt |6 +++-
> drivers/spi/spi-qup.c | 36
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added remove function
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala
---
v2:
* Fixed MODULE_LICENSE to be GPL v2
On Jun 13, 2014, at 9:38 AM, Stanimir Varbanov wrote:
> Hi Kumar,
>
>> +
>> +static struct platform_driver qcom_ahci_driver = {
>> +.probe = qcom_ahci_probe,
>> +.remove = ata_platform_remove_one,
>> +.driver = {
>> +.name = "qcom_ahci_qcom",
>> +.owner =
On Jun 13, 2014, at 9:38 AM, Stanimir Varbanov svarba...@mm-sol.com wrote:
Hi Kumar,
+
+static struct platform_driver qcom_ahci_driver = {
+.probe = qcom_ahci_probe,
+.remove = ata_platform_remove_one,
+.driver = {
+.name = qcom_ahci_qcom,
+.owner =
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Fixed MODULE_LICENSE
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* dropped unused dev pointer in struct qcom_ipq806x_sata_phy
* remove unnecessary reg initializaiton
* Removed unneeded error message
* Added
On Jun 12, 2014, at 2:34 PM, Andy Gross agr...@codeaurora.org wrote:
This patch adds support for v1.1.1 of the SPI QUP controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/spi/qcom,spi-qup.txt |6 +++-
drivers/spi/spi-qup.c
On Jun 12, 2014, at 2:50 PM, Stephen Boyd wrote:
> On 06/12/14 12:13, Kumar Gala wrote:
>> +static int qcom_ahci_probe(struct platform_device *pdev)
>> +{
>> +struct ahci_host_priv *hpriv;
>> +struct clk *rxoob_clk;
>> +int rc;
>> +
>>
Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
Documentation/devicetree/bindings/phy/qcom-phy.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
drivers/phy/Kconfig | 6 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 204
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala
---
drivers/ata/Kconfig | 10 ++
drivers
Qualcomm IPQ806x SoCs with SATA controllers need 5 clocks to be enabled.
Signed-off-by: Kumar Gala
---
drivers/ata/ahci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 05882e4..001aa99 100644
--- a/drivers/ata/ahci.h
+++ b
Add device tree binding for Qualcomm AHCI SATA controller and specifically
the sata controller on the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala
---
.../devicetree/bindings/ata/qcom-sata.txt | 40 ++
1 file changed, 40 insertions(+)
create mode 100644
Qualcomm IPQ806x SoCs with SATA controllers need 5 clocks to be enabled.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/ata/ahci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 05882e4..001aa99 100644
--- a/drivers
Add device tree binding for Qualcomm AHCI SATA controller and specifically
the sata controller on the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
.../devicetree/bindings/ata/qcom-sata.txt | 40 ++
1 file changed, 40 insertions
Add support for the Qualcomm AHCI SATA controller that exists on several
SoC and specifically the IPQ806x family of chips. The IPQ806x SATA support
requires the associated IPQ806x SATA PHY Driver to be enabled as well.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/ata/Kconfig
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/phy/Kconfig | 6 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-qcom-ipq806x-sata.c | 204
Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
the IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
Documentation/devicetree/bindings/phy/qcom-phy.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644 Documentation
On Jun 12, 2014, at 2:50 PM, Stephen Boyd sb...@codeaurora.org wrote:
On 06/12/14 12:13, Kumar Gala wrote:
+static int qcom_ahci_probe(struct platform_device *pdev)
+{
+struct ahci_host_priv *hpriv;
+struct clk *rxoob_clk;
+int rc;
+
+hpriv = ahci_platform_get_resources
Boyd
> ---
>
> Patch based on next-20140610
>
> drivers/mmc/host/sdhci-msm.c | 4
> 1 file changed, 4 insertions(+)
Acked-by: Kumar Gala
Feel free to pick up this version of the patch and ignore mine.
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation
Recent changes in sdhci core need to get reflected in sdhci_msm_ops otherwise
we ended up dereferencing null pointers in the ops struct and crash.
Signed-off-by: Kumar Gala
---
drivers/mmc/host/sdhci-msm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b
Recent changes in sdhci core need to get reflected in sdhci_msm_ops otherwise
we ended up dereferencing null pointers in the ops struct and crash.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/mmc/host/sdhci-msm.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc
...@arm.linux.org.uk
Signed-off-by: Stephen Boyd sb...@codeaurora.org
---
Patch based on next-20140610
drivers/mmc/host/sdhci-msm.c | 4
1 file changed, 4 insertions(+)
Acked-by: Kumar Gala ga...@codeaurora.org
Feel free to pick up this version of the patch and ignore mine.
- k
--
Employee
with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
Signed-off-by: Kumar Gala
---
drivers/tty/serial/msm_serial.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/msm_serial.c b
with __init* or __refdata (see linux/init.h) or name the variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/tty/serial/msm_serial.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty
On Jun 2, 2014, at 2:15 PM, Arnd Bergmann wrote:
> On Monday 02 June 2014 13:09:08 Kumar Gala wrote:
>>> However, what do we do with the 2 cases that exist in upstream that
>>>> are using ranges for cfg space?
>>>
>>> Ignore them in the core code
On May 31, 2014, at 10:45 AM, Georgi Djakov wrote:
> This patch adds the necessary node to probe the global clock
> controller on APQ8084 platforms.
>
> Signed-off-by: Georgi Djakov
> ---
> arch/arm/boot/dts/qcom-apq8084.dtsi | 10 ++
> 1 file changed, 10 insertions(+)
Can you split
On Jun 2, 2014, at 11:23 AM, Grant Likely wrote:
> On Mon, 2 Jun 2014 10:40:30 -0500, Kumar Gala wrote:
>>
>> On Jun 2, 2014, at 10:09 AM, Grant Likely wrote:
>>
>>> On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann wrote:
>>>> On Saturday 31 May
On Jun 2, 2014, at 10:09 AM, Grant Likely wrote:
> On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann wrote:
>> On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote:
>>> We would like to be able to describe PCIe ECAM resources as
>>> IORESOURCE_MEM blocks while distinguish them from standard
>>>
On Jun 2, 2014, at 10:09 AM, Grant Likely grant.lik...@linaro.org wrote:
On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de wrote:
On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote:
We would like to be able to describe PCIe ECAM resources as
IORESOURCE_MEM blocks while
On Jun 2, 2014, at 11:23 AM, Grant Likely grant.lik...@linaro.org wrote:
On Mon, 2 Jun 2014 10:40:30 -0500, Kumar Gala ga...@codeaurora.org wrote:
On Jun 2, 2014, at 10:09 AM, Grant Likely grant.lik...@linaro.org wrote:
On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de wrote
On May 31, 2014, at 10:45 AM, Georgi Djakov gdja...@mm-sol.com wrote:
This patch adds the necessary node to probe the global clock
controller on APQ8084 platforms.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 10 ++
1 file changed, 10
On Jun 2, 2014, at 2:15 PM, Arnd Bergmann a...@arndb.de wrote:
On Monday 02 June 2014 13:09:08 Kumar Gala wrote:
However, what do we do with the 2 cases that exist in upstream that
are using ranges for cfg space?
Ignore them in the core code? Make the specific host controller handle
them
On May 29, 2014, at 8:41 PM, Liviu Dudau wrote:
> On Thu, May 29, 2014 at 07:29:31PM -0600, Bjorn Helgaas wrote:
>> On Thu, May 29, 2014 at 6:56 PM, Liviu Dudau wrote:
>>> On Thu, May 29, 2014 at 03:51:28PM -0500, Kumar Gala wrote:
>>>>
>>>> On Ma
On May 30, 2014, at 3:37 PM, Jason Gunthorpe
wrote:
> On Fri, May 30, 2014 at 02:41:17AM +0100, Liviu Dudau wrote:
>
>> Agree, I'm only concerned that if this ECAM config space gets added to
>> the list of pci_host_bridge windows it will be indistinguishable from
>> IORESOURCE_MEM resources
On May 30, 2014, at 12:28 PM, Stephen Boyd wrote:
> On 05/29/14 09:26, Kumar Gala wrote:
>> Signed-off-by: Kumar Gala
>> ---
>> arch/arm/configs/qcom_defconfig | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/configs/qcom_defconfi
The following changes since commit 87cfb00d666cca3abf36f755279cde1b27b9c377:
ARM: qcom: Select PINCTRL by default for ARCH_QCOM (2014-05-22 11:50:42 -0500)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
tags/qcom-soc-for-3.16-2
Kumar Gala (1):
ARM: qcom: Enable GSBI driver in defconfig
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum
The following changes since commit 5d144e36b7c51612922fa05d37ff3a869261cc82:
soc: qcom: Add GSBI driver (2014-05-23 11:38:04 -0500)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
tags/qcom-drivers-for-3.16-2
for you to fetch
support
ARM: dts: qcom: Add APQ8084-MTP board support
Kumar Gala (4):
ARM: dts: qcom: Update msm8974/apq8074 device trees
ARM: dts: qcom: Update msm8960 device trees
ARM: dts: qcom: Update msm8660 device trees
ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board
support
ARM: dts: qcom: Add APQ8084-MTP board support
Kumar Gala (4):
ARM: dts: qcom: Update msm8974/apq8074 device trees
ARM: dts: qcom: Update msm8960 device trees
ARM: dts: qcom: Update msm8660 device trees
ARM: dts: qcom: Add initial APQ8064 SoC and IFC6410 board
The following changes since commit 5d144e36b7c51612922fa05d37ff3a869261cc82:
soc: qcom: Add GSBI driver (2014-05-23 11:38:04 -0500)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
tags/qcom-drivers-for-3.16-2
for you to fetch
Kumar Gala (1):
ARM: qcom: Enable GSBI driver in defconfig
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum
The following changes since commit 87cfb00d666cca3abf36f755279cde1b27b9c377:
ARM: qcom: Select PINCTRL by default for ARCH_QCOM (2014-05-22 11:50:42 -0500)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git
tags/qcom-soc-for-3.16-2
On May 30, 2014, at 12:28 PM, Stephen Boyd sb...@codeaurora.org wrote:
On 05/29/14 09:26, Kumar Gala wrote:
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig
b/arch/arm
On May 30, 2014, at 3:37 PM, Jason Gunthorpe jguntho...@obsidianresearch.com
wrote:
On Fri, May 30, 2014 at 02:41:17AM +0100, Liviu Dudau wrote:
Agree, I'm only concerned that if this ECAM config space gets added to
the list of pci_host_bridge windows it will be indistinguishable from
On May 29, 2014, at 8:41 PM, Liviu Dudau li...@dudau.co.uk wrote:
On Thu, May 29, 2014 at 07:29:31PM -0600, Bjorn Helgaas wrote:
On Thu, May 29, 2014 at 6:56 PM, Liviu Dudau li...@dudau.co.uk wrote:
On Thu, May 29, 2014 at 03:51:28PM -0500, Kumar Gala wrote:
On May 29, 2014, at 3:44 PM
On May 29, 2014, at 3:44 PM, Rob Herring wrote:
> On Thu, May 29, 2014 at 11:03 AM, Kumar Gala wrote:
>> If we have a PCI config space specified in something like a ranges
>> property we should treat it as memory type resource.
>
> Config space should not be in ranges[1
On May 29, 2014, at 11:30 AM, Jason Gunthorpe
wrote:
> On Thu, May 29, 2014 at 11:03:36AM -0500, Kumar Gala wrote:
>
>> Just because the kernel doesn’t handle this is NO reason to change
>> the way the DT works.
>
> The OF specs do not specify how to process a
On May 29, 2014, at 11:19 AM, Srinivas Kandagatla
wrote:
>> += SUBDEVICES
>> +
>> +The RPM exposes resources to its subnodes. The below bindings specify the
>> set
>> +of valid subnodes that can operate on these resources.
>
> Why should these devices be on sub nodes?
>
> Any reason not to
Signed-off-by: Kumar Gala
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index bfed753..42ebd72 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -131,6
On May 29, 2014, at 10:14 AM, Kumar Gala wrote:
>
> On Apr 24, 2014, at 11:31 AM, Andy Gross wrote:
>
>> This patch removes direct access of the GSBI registers. GSBI configuration
>> should be done through the GSBI driver directly.
>>
>> Signed-off-by:
If we have a PCI config space specified in something like a ranges
property we should treat it as memory type resource.
Signed-off-by: Kumar Gala
---
drivers/of/address.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index cb4242a..4e7ee59
On May 29, 2014, at 10:18 AM, Liviu Dudau wrote:
> On Thu, May 29, 2014 at 10:03:54AM -0500, Kumar Gala wrote:
>>
>> On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I wrote:
>>
>>> The configuration address space has so far been specified in *ranges*,
>
-by: Kumar Gala
---
v2:
* Added GSBI node
arch/arm/boot/dts/qcom-msm8660-surf.dts | 10 +++
arch/arm/boot/dts/qcom-msm8660.dtsi | 115 +++-
2 files changed, 78 insertions(+), 47 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts
b/arch/arm/boot/dts
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
order.
Signed-off-by: Kumar Gala
---
v2:
* Fix gsbi controller reg address
arch/arm/boot/dts/Makefile | 8 +-
arch/arm/boot/dts
of the
binding spec
* Add GSBI node and configuration of GSBI controller
Signed-off-by: Kumar Gala
---
v2:
* Added GSBI node
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 10 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 176 ++---
2 files changed, 108 insertions(+), 78
On Apr 24, 2014, at 11:31 AM, Andy Gross wrote:
> This patch removes direct access of the GSBI registers. GSBI configuration
> should be done through the GSBI driver directly.
>
> Signed-off-by: Andy Gross
> ---
> drivers/tty/serial/msm_serial.c | 48 ++-
On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I wrote:
> The configuration address space has so far been specified in *ranges*,
> however it should be specified in *reg* making it a platform MEM resource.
> Hence used 'platform_get_resource_*' API to get configuration address
> space in the
On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address
On Apr 24, 2014, at 11:31 AM, Andy Gross agr...@codeaurora.org wrote:
This patch removes direct access of the GSBI registers. GSBI configuration
should be done through the GSBI driver directly.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/tty/serial/msm_serial.c | 48
of the
binding spec
* Add GSBI node and configuration of GSBI controller
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Added GSBI node
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 10 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 176 ++---
2 files changed, 108
-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Added GSBI node
arch/arm/boot/dts/qcom-msm8660-surf.dts | 10 +++
arch/arm/boot/dts/qcom-msm8660.dtsi | 115 +++-
2 files changed, 78 insertions(+), 47 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts
b
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
order.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v2:
* Fix gsbi controller reg address
arch/arm/boot/dts/Makefile | 8
If we have a PCI config space specified in something like a ranges
property we should treat it as memory type resource.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
drivers/of/address.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/address.c b/drivers/of/address.c
index
On May 29, 2014, at 10:18 AM, Liviu Dudau li...@dudau.co.uk wrote:
On Thu, May 29, 2014 at 10:03:54AM -0500, Kumar Gala wrote:
On May 29, 2014, at 1:38 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
The configuration address space has so far been specified in *ranges*,
however it should
On May 29, 2014, at 10:14 AM, Kumar Gala ga...@codeaurora.org wrote:
On Apr 24, 2014, at 11:31 AM, Andy Gross agr...@codeaurora.org wrote:
This patch removes direct access of the GSBI registers. GSBI configuration
should be done through the GSBI driver directly.
Signed-off-by: Andy
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index bfed753..42ebd72 100644
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs
On May 29, 2014, at 11:19 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
+= SUBDEVICES
+
+The RPM exposes resources to its subnodes. The below bindings specify the
set
+of valid subnodes that can operate on these resources.
Why should these devices be on sub nodes?
On May 29, 2014, at 11:30 AM, Jason Gunthorpe jguntho...@obsidianresearch.com
wrote:
On Thu, May 29, 2014 at 11:03:36AM -0500, Kumar Gala wrote:
Just because the kernel doesn’t handle this is NO reason to change
the way the DT works.
The OF specs do not specify how to process a config
On May 29, 2014, at 3:44 PM, Rob Herring robherri...@gmail.com wrote:
On Thu, May 29, 2014 at 11:03 AM, Kumar Gala ga...@codeaurora.org wrote:
If we have a PCI config space specified in something like a ranges
property we should treat it as memory type resource.
Config space should
On May 28, 2014, at 3:09 PM, Josh Cartwright wrote:
> On Wed, May 28, 2014 at 01:27:23PM -0500, Kumar Gala wrote:
>> * Move SoC peripherals into an SoC container node
>> * Move serial enabling into board file (qcom-msm8960-cdp.dts)
>> * Cleanup cpu node to match bindin
property from l2-cache node as its not part of the
binding spec
* Move timer node out of SoC container
Signed-off-by: Kumar Gala
---
v2:
* Move timer node out of SoC container
arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 ++-
arch/arm/boot/dts/qcom-msm8974.dtsi| 49
property from l2-cache node as its not part of the
binding spec
Signed-off-by: Kumar Gala
---
arch/arm/boot/dts/qcom-apq8074-dragonboard.dts | 28 ++-
arch/arm/boot/dts/qcom-msm8974.dtsi| 31 --
2 files changed, 36 insertions(+), 23 deletions
of the
binding spec
Signed-off-by: Kumar Gala
---
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 165 +
2 files changed, 93 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
b/arch/arm/boot
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8660-surf.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
Signed-off-by: Kumar Gala
---
arch/arm/boot/dts/qcom-msm8660
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
order.
Signed-off-by: Kumar Gala
---
v3:
* Cleanup cpu node to have compatible & enable-method per node and
not in the container
* Droppe
On May 28, 2014, at 11:59 AM, Bjorn Andersson wrote:
> On Wed, May 28, 2014 at 9:23 AM, Kumar Gala wrote:
>>
>> On May 27, 2014, at 12:28 PM, Bjorn Andersson
>> wrote:
>>
>>> This series adds a regulator driver for the Resource Power Manager found in
&g
On May 27, 2014, at 12:28 PM, Bjorn Andersson
wrote:
> Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660, 8960
> and 8064 based devices. The binding currently describes the rpm itself and the
> regulator subnodes.
>
> Signed-off-by: Bjorn Andersson
> ---
>
On May 27, 2014, at 12:28 PM, Bjorn Andersson
wrote:
> This series adds a regulator driver for the Resource Power Manager found in
> Qualcomm 8660, 8960 and 8064 based devices.
>
> The RPM driver exposes resources to its child devices, that can be accessed to
> implement drivers for the
On May 28, 2014, at 3:09 PM, Josh Cartwright jo...@codeaurora.org wrote:
On Wed, May 28, 2014 at 01:27:23PM -0500, Kumar Gala wrote:
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec
On May 27, 2014, at 12:28 PM, Bjorn Andersson bjorn.anders...@sonymobile.com
wrote:
This series adds a regulator driver for the Resource Power Manager found in
Qualcomm 8660, 8960 and 8064 based devices.
The RPM driver exposes resources to its child devices, that can be accessed to
On May 27, 2014, at 12:28 PM, Bjorn Andersson bjorn.anders...@sonymobile.com
wrote:
Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660, 8960
and 8064 based devices. The binding currently describes the rpm itself and the
regulator subnodes.
Signed-off-by: Bjorn
On May 28, 2014, at 11:59 AM, Bjorn Andersson bj...@kryo.se wrote:
On Wed, May 28, 2014 at 9:23 AM, Kumar Gala ga...@codeaurora.org wrote:
On May 27, 2014, at 12:28 PM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
This series adds a regulator driver for the Resource Power
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board. Also, keep dtb build list and qcom_dt_match in sorted
order.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v3:
* Cleanup cpu node to have compatible enable-method per node
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