On Mon, Jul 22, 2019 at 12:18 PM Ilias Apalodimas
wrote:
>
> On Thu, Jul 18, 2019 at 07:48:04AM +, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/17/2019, 19:58:53 (UTC+00:00)
> >
> > > Let me know if you have any thoughts.
> >
> > Can you try attached patch ?
> >
>
> The log says some
: I38b6fd0addc1d93ae172332b67e6eb71c0871508
Signed-off-by: Lars Persson
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 677ef41cb012..a91d04e5c084 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1432,6 +1432,7 @@ F:arch/arm/mach-artpec
F: arch/arm/boot/dts/artpec6*
F
On Fri, Jun 21, 2019 at 12:50 PM Wolfram Sang wrote:
>
> Hi,
>
> On Fri, Jun 21, 2019 at 03:16:11PM +0900, Masahiro Yamada wrote:
> > (Added Lars Persson, Guennadi Liakhovetski)
> >
> > On Fri, Jun 21, 2019 at 3:06 PM Masahiro Yamada
> > wrote:
> >
>
On Wed, May 15, 2019 at 1:19 PM Greg Kroah-Hartman
wrote:
>
> [ Upstream commit 05fd5c2c61732152a6bddc318aae62d7e436629b ]
>
> Commit 088aaf17aa79300cab14dbee2569c58cfafd7d6e introduced a leak where
> if SMB2_read() returned an error we would return without freeing the
> request buffer.
>
> Cc: St
nce inside move_to_new_page
to make it common for both cases.
Cc: sta...@vger.kernel.org
Fixes: 97ee0524614 ("flush cache before installing new page at migraton")
Reviewed-by: Paul Burton
Acked-by: Mel Gorman
Signed-off-by: Lars Persson
---
v2: Added a Fixes footer and CC for stable.
On 2/26/19 12:57 PM, Lars Persson wrote:
On 2/26/19 11:07 AM, Vlastimil Babka wrote:
On 2/26/19 9:40 AM, Lars Persson wrote:
What about CC stable and a Fixes tag, would it be applicable here?
Yes this is candidate for stable so let's add:
Cc:
I do not find a good candidate
On 2/26/19 11:07 AM, Vlastimil Babka wrote:
On 2/26/19 9:40 AM, Lars Persson wrote:
What about CC stable and a Fixes tag, would it be applicable here?
Yes this is candidate for stable so let's add:
Cc:
I do not find a good candidate for a Fixes tag.
How bout a version range wher
On Tue, Feb 26, 2019 at 10:23 AM Anshuman Khandual
wrote:
> On 02/19/2019 06:02 PM, Lars Persson wrote:
> > Our MIPS 1004Kc SoCs were seeing random userspace crashes with SIGILL
> > and SIGSEGV that could not be traced back to a userspace code
> > bug. They had all the magic
On 2/25/19 4:07 PM, Vlastimil Babka wrote:
On 2/19/19 1:32 PM, Lars Persson wrote:
Our MIPS 1004Kc SoCs were seeing random userspace crashes with SIGILL
and SIGSEGV that could not be traced back to a userspace code
bug. They had all the magic signs of an I/D cache coherency issue.
Now
nce inside move_to_new_page
to make it common for both cases.
Signed-off-by: Lars Persson
---
mm/migrate.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/mm/migrate.c b/mm/migrate.c
index d4fd680be3b0..80fc19e610b5 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -248
On Tue, Feb 5, 2019 at 8:14 AM Jan Stancek wrote:
> Hi,
>
> are you using THP (CONFIG_TRANSPARENT_HUGEPAGE)?
>
> The changed line should affect only THP and normal compound pages,
> so a test with THP disabled might be interesting.
>
> >
> > The breakage consists of random processes dying with SIG
On Fri, Nov 30, 2018 at 1:07 PM Jan Stancek wrote:
>
> LTP proc01 testcase has been observed to rarely trigger crashes
> on arm64:
> page_mapped+0x78/0xb4
> stable_page_flags+0x27c/0x338
> kpageflags_read+0xfc/0x164
> proc_reg_read+0x7c/0xb8
> __vfs_read+0x58/0x178
> vfs_re
On 1/22/19 4:14 PM, Greg Kroah-Hartman wrote:
When calling debugfs functions, there is no need to ever check the
return value. The function can work or not, but the code logic should
never do something different based on this.
Cc: Jesper Nilsson
Cc: Lars Persson
Cc: Herbert Xu
Cc: "
On Mon, Sep 24, 2018 at 8:32 AM Richard Weinberger wrote:
>
> Lars,
>
> Am Sonntag, 23. September 2018, 15:49:42 CEST schrieb Lars Persson:
> > Hi Richard
> >
> > Sorry, I assumed this omission from -stable was a mistake.
> >
> > The timing for our boot
On Sun, Sep 23, 2018 at 2:58 PM Richard Weinberger wrote:
>
> Lars,
>
> Am Sonntag, 23. September 2018, 14:49:23 CEST schrieb Lars Persson:
> > On Sun, Jul 1, 2018 at 6:27 PM Greg Kroah-Hartman
> > wrote:
> > >
> > > 4.9-stable review patch. I
ly
handle interrupted erasures in EBA
This will in turn require also this follow-up patch:
25677478474a91fa1b46f19a4a591a9848bca6fb ubi: Initialize Fastmap
checkmapping correctly
BR,
Lars Persson
On 10/25/2017 12:18 PM, Kees Cook wrote:
In preparation for unconditionally passing the struct timer_list pointer to
all timer callbacks, switch to using the new timer_setup() and from_timer()
to pass the timer pointer explicitly.
Cc: Herbert Xu
Cc: Jesper Nilsson
Cc: Lars Persson
Cc
ypto_fail_dma_array_full);
> @@ -2984,6 +2982,8 @@ struct dbgfs_u32 {
> char *desc;
> };
>
> +static struct dentry *dbgfs_root;
> +
> static void artpec6_crypto_init_debugfs(void)
> {
> dbgfs_root = debugfs_create_dir("artpec6_crypto", NULL);
> --
> 2.9.0
Acked-by: Lars Persson
Thanks,
Lars
On 08/10/2017 02:53 PM, Lars Persson wrote:
From: Rabin Vincent
There are already helpers to (un)register multiple normal
and AEAD algos. Add one for ahashes too.
Signed-off-by: Lars Persson
Signed-off-by: Rabin Vincent
---
v4: crypto_register_skciphers was used where
Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.
Signed-off-by: Lars Persson
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
From: Rabin Vincent
There are already helpers to (un)register multiple normal
and AEAD algos. Add one for ahashes too.
Signed-off-by: Lars Persson
Signed-off-by: Rabin Vincent
---
v4: crypto_register_skciphers was used where crypto_unregister_skciphers
was intended.
crypto/ahash.c
Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.
Acked-by: Rob Herring
Signed-off-by: Lars Persson
---
.../devicetree/bindings/crypto/artpec6-crypto.txt| 16
1 file changed, 16 insertions(+)
create mode 100644
This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.
The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.
Signed-off-by: Lars Persson
---
drivers/crypto/Kconfig | 21 +
drivers
-off-by on patch 2.
Changelog v2:
- Use xts_check_key() for xts keys.
- Use CRYPTO_ALG_TYPE_SKCIPHER instead of CRYPTO_ALG_TYPE_ABLKCIPHER
in cra_flags.
Lars Persson (3):
dt-bindings: crypto: add ARTPEC crypto
crypto: axis: add ARTPEC-6/7 crypto accelerator driver
MAINTAINERS: Add ARTPEC
|2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Hi,
Acked-by: Lars Persson
BR,
Lars
estion. Please resubmit
with a sign-off. Thanks!
Sorry for missing this. We fixed it in patch set v3.
BR,
Lars Persson
Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.
Signed-off-by: Lars Persson
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
CRYPTO_ALG_TYPE_ABLKCIPHER
in cra_flags.
Lars Persson (3):
dt-bindings: crypto: add ARTPEC crypto
crypto: axis: add ARTPEC-6/7 crypto accelerator driver
MAINTAINERS: Add ARTPEC crypto maintainer
Rabin Vincent (1):
crypto: add crypto_(un)register_ahashes()
.../devicetree/bindings/crypto/artpec6-crypto.txt
From: Rabin Vincent
There are already helpers to (un)register multiple normal
and AEAD algos. Add one for ahashes too.
Signed-off-by: Lars Persson
Signed-off-by: Rabin Vincent
---
crypto/ahash.c | 29 +
include/crypto/internal/hash.h | 2 ++
2
This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.
The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.
Signed-off-by: Lars Persson
---
drivers/crypto/Kconfig | 21 +
drivers
Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.
Signed-off-by: Lars Persson
---
.../devicetree/bindings/crypto/artpec6-crypto.txt| 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree
Document the device tree bindings for the ARTPEC crypto accelerator on
ARTPEC-6 and ARTPEC-7 SoCs.
Signed-off-by: Lars Persson
---
.../devicetree/bindings/crypto/artpec6-crypto.txt| 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree
This is an asynchronous crypto API driver for the accelerator present
in the ARTPEC-6 and -7 SoCs from Axis Communications AB.
The driver supports AES in ECB/CTR/CBC/XTS/GCM modes and SHA1/2 hash
standards.
Signed-off-by: Lars Persson
---
drivers/crypto/Kconfig | 21 +
drivers
Assign the Axis kernel team as maintainer for crypto drivers under
drivers/crypto/axis.
Signed-off-by: Lars Persson
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d5b6c71e783e..72186cf9820d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
This series adds a driver for the crypto accelerator in the ARTPEC series of
SoCs from Axis Communications AB.
Changelog v2:
- Use xts_check_key() for xts keys.
- Use CRYPTO_ALG_TYPE_SKCIPHER instead of CRYPTO_ALG_TYPE_ABLKCIPHER
in cra_flags.
Lars Persson (3):
dt-bindings: crypto: add
From: Rabin Vincent
There are already helpers to (un)register multiple normal
and AEAD algos. Add one for ahashes too.
Signed-off-by: Lars Persson
---
crypto/ahash.c | 29 +
include/crypto/internal/hash.h | 2 ++
2 files changed, 31 insertions
> 23 nov. 2016 kl. 12:11 skrev Joao Pinto :
>
> Hi Peppe and Lars,
>
>> On 23-11-2016 10:59, Giuseppe CAVALLARO wrote:
>> Hello Joao, Lars.
>>
>>> On 11/22/2016 3:16 PM, Joao Pinto wrote:
> Ok, it makes sense.
> Just for curiosity the target setup is the following:
> https://www.you
> 21 nov. 2016 kl. 16:06 skrev Joao Pinto :
>
>> On 21-11-2016 14:25, Giuseppe CAVALLARO wrote:
>>> On 11/21/2016 2:28 PM, Lars Persson wrote:
>>>
>>>
>>>> 21 nov. 2016 kl. 13:53 skrev Giuseppe CAVALLARO :
>>>>
>>>>
> 21 nov. 2016 kl. 13:53 skrev Giuseppe CAVALLARO :
>
> Hello Joao
>
>> On 11/21/2016 1:32 PM, Joao Pinto wrote:
>> Hello,
>>
>>> On 21-11-2016 05:29, Rayagond Kokatanur wrote:
On Sat, Nov 19, 2016 at 7:26 PM, Rabin Vincent wrote:
> On Fri, Nov 18, 2016 at 02:20:27PM +, Joao Pint
We move register_netdev() to the end of dwceqos_probe() to close any
races where the netdev callbacks are called before the initialization
has finished.
Reported-by: Pavel Andrianov
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 38
Hi Pavel,
Thanks for the notification. I agree that we should register the device
after all initialization has completed. A patch will be sent shortly.
BR,
Lars
On 09/05/2016 10:26 AM, Pavel Andrianov wrote:
Hi!
There is a potential bug in
drivers/net/ethernet/synopsys/dwc_eth_qos.ko. In
the interrupt
enable to after we've enable NAPI and the reclaim tasklet.
Fixes: cd5e41234729 ("dwc_eth_qos: do phy_start before resetting hardware")
Signed-off-by: Rabin Vincent
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 17 ++---
1 f
The irq affinity is required for pmu interrupts.
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/artpec6.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 4e40d55..3489019c 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
Use defines from the clock binding header as clock indexes.
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/artpec6.dtsi | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 3fac4c4
This brings the dtsi up to date with with tested and optimized settings from the
Axis tree.
Lars Persson (3):
ARM: dts: artpec: use clock binding header
ARM: dts: artpec: use optimized pl310 settings
ARM: dts: artpec: set irq affinity on pmu interrupts
arch/arm/boot/dts/artpec6.dtsi | 31
Use the cache settings that were determined to give best performance
on artpec-6 typical workloads.
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/artpec6.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index
On 08/16/2016 01:59 PM, Michal Marek wrote:
On 2016-08-16 13:40, Lars Persson wrote:
We need to filter out also -I=/path to allow sysroot relative
include paths in the makefiles of external modules.
Signed-off-by: Lars Persson
---
scripts/Kbuild.include | 2 +-
1 file changed, 1 insertion
We need to filter out also -I=/path to allow sysroot relative
include paths in the makefiles of external modules.
Signed-off-by: Lars Persson
---
scripts/Kbuild.include | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index
> 24 apr. 2016 kl. 01:31 skrev Arnd Bergmann :
>
>> On Monday 14 March 2016, Lars Persson wrote:
>> The clock binding for the main clock controller was changed to an
>> indexed controller style binding on request of the clk
>> maintainers. This updates th
known if later packets also will fail in the
validate path.
Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson
---
v3: After a discussion with Eric and Cong I went back to v1 and added the
likely() for the common path.
---
net/sched/sch_generic
On 04/11/2016 04:22 PM, Eric Dumazet wrote:
On Mon, 2016-04-11 at 15:38 +0200, Lars Persson wrote:
I though it would be prudent because the queue can be non-empty even for
the case of skb=NULL. So should it be there in this patch, another patch
or not at all ?
Then maybe change return code
On 04/11/2016 03:23 PM, Eric Dumazet wrote:
On Mon, 2016-04-11 at 08:24 +0200, Lars Persson wrote:
A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the
edule call conditional to avoid scheduling an
empty queue.
Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-by: Lars Persson
---
net/sched/sch_generic.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/net/sched/sch_generi
A failure in validate_xmit_skb_list() triggered an unconditional call
to dev_requeue_skb with skb=NULL. This slowly grows the queue
discipline's qlen count until all traffic through the queue stops.
Fixes: 55a93b3ea780 ("qdisc: validate skb without holding lock")
Signed-off-b
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring
Signed-off-by: Lars Persson
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++
include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38
2
the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock controller
clk: add artpec-6 clock controller
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock controller
clk: add artpec-6 clock
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson
---
MAINTAINERS| 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 242
On 04/02/2016 03:39 AM, Stephen Boyd wrote:
On 03/31, Lars Persson wrote:
diff --git a/drivers/clk/axis/Makefile b/drivers/clk/axis/Makefile
new file mode 100644
index 000..628c9d3
--- /dev/null
+++ b/drivers/clk/axis/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
bindings.
Changes since v1:
- The driver now provides all clocks from the main clock controller block
through one DT node.
- Added a header file for the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson
---
MAINTAINERS| 2 +-
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 230
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring
Signed-off-by: Lars Persson
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++
include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38
2
gh a platform driver. Is this the style we should
implement ?
Best Regards,
Lars Persson
On 02/25/2016 03:58 PM, Lars Persson wrote:
Add clock support for the Artpec-6 SoC port. The ARM parts are in the series
"arm: Add Artpec-6 SoC" and it goes through the arm-soc tree.
Changes s
The clock binding for the main clock controller was changed to an
indexed controller style binding on request of the clk
maintainers. This updates the dtsi to use the new bindings.
Signed-off-by: Lars Persson
---
v2: Use numerical clock indexes to enable merge before the clock driver bindings
On 03/13/2016 01:14 AM, Olof Johansson wrote:
On Thu, Feb 25, 2016 at 10:34:14AM +0100, Lars Persson wrote:
The clock bindings for the main clock controller was changed to an
indexed controller style binding on request of the clk
maintainers. This updates the dtsi to use the new bindings
d code, typically resulting in a reserved
> instruction exception, a trap or a segfault.
>
> Fix this race condition fully by performing any cache maintenance
> required to keep the icache & dcache in sync in set_pte_at, before the
> page is made valid. This has the added bonus
> 1 mars 2016 kl. 03:38 Paul Burton :
>
> The flush_kernel_dcache_page function was previously essentially a nop.
> This is incorrect for MIPS, where if a page has been modified & either
> it aliases or it's executable & the icache doesn't fill from dcache then
> the content needs to be written
.
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/synopsys/dwc_eth_qos.c
b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
index 926db2d..53d48c0 100644
--- a/drivers/net
From: Rabin Vincent
Since we are in non-atomic context here we can pass GFP_KERNEL to
dma_alloc_coherent(). This enables use of the CMA.
Signed-off-by: Rabin Vincent
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 4 ++--
1 file changed, 2 insertions(+), 2
o plug the race with the phy state machine we defer link speed
setting until the hardware init has finished.
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/net/etherne
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/synopsys/dwc_eth_qos.c
b/drivers/net/ethernet/synopsys/dwc_eth_qos.c
index 3ca2d5c..6897c1d 100644
--- a/drivers/net/ethernet/synopsys
From: Rabin Vincent
The xmit handler and the tx_reclaim tasklet had a race on the tx_free
variable which could lead to a tx timeout if tx_free was updated after
the tx complete interrupt.
Signed-off-by: Rabin Vincent
Signed-off-by: Lars Persson
---
drivers/net/ethernet/synopsys/dwc_eth_qos.c
.
The memory allocation was improved to support use of the CMA as DMA allocator
backend.
Lars Persson (2):
dwc_eth_qos: release descriptors outside netif_tx_lock
dwc_eth_qos: do phy_start before resetting hardware
Rabin Vincent (3):
dwc_eth_qos: fix race condition in dwceqos_start_xmit
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring
Signed-off-by: Lars Persson
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++
include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38
2
le for the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
A platform driver was not possible because the clocks are needed earlier in the
kernel startup.
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock controller
clk: add artpec-6 clock controller
.../
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson
---
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 189 +
3 files changed, 191 insertions
The clock bindings for the main clock controller was changed to an
indexed controller style binding on request of the clk
maintainers. This updates the dtsi to use the new bindings.
Signed-off-by: Lars Persson
---
Note: This patch depends on a header file delivered through the clk tree in
&quo
Relaxed the license on the dtsi to permit use in other projects.
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/artpec6.dtsi | 40 +---
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson
---
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile | 1 +
drivers/clk/axis/clk-artpec6.c | 177 +
3 files changed, 179 insertions
s from the main clock controller block
through one DT node.
- Added a header file for the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
A platform driver was not possible because the clocks are needed earlier in the
kernel startup.
Lars Persson (2):
clk: add device tr
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Acked-by: Rob Herring
Signed-off-by: Lars Persson
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++
include/dt-bindings/clock/axis,artpec6-clkctrl.h | 38
2
e, before the page is
provided to userland.
Reviewed-by: Lars Persson
Signed-off-by: Paul Burton
---
arch/mips/mm/cache.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 3f159ca..734cb2f 100644
--- a/arc
Add a driver for the main clock controller of the Artpec-6 Soc.
Signed-off-by: Lars Persson
---
drivers/clk/Makefile | 1 +
drivers/clk/axis/Makefile| 1 +
drivers/clk/axis/clk-artpec6.c | 177
Add device tree documentation for the main clock controller in the
Artpec-6 SoC.
Signed-off-by: Lars Persson
---
.../devicetree/bindings/clock/artpec6.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/artpec6
the clock indexes.
- Refer to clock-bindings.txt in the bindings document.
A platform driver was not possible because the clocks are needed earlier in the
kernel startup.
Lars Persson (2):
clk: add device tree binding for Artpec-6 clock controller
clk: add artpec-6 clock controller
.../devicetre
On 02/17/2016 01:02 AM, Michael Turquette wrote:
Hi Lars,
Quoting Lars Persson (2016-02-11 08:01:04)
The PLL1 clock is a fixed-factor clock with factors derived from boot
mode pins. This driver is a simple wrapper to register the fixed
factor clock according to the pin settings.
Signed-off
On 02/17/2016 12:59 AM, Michael Turquette wrote:
Quoting Lars Persson (2016-02-14 00:03:06)
On 02/12/2016 05:39 PM, Rob Herring wrote:
On Thu, Feb 11, 2016 at 05:01:03PM +0100, Lars Persson wrote:
Add device tree documentation for the main PLL in the Artpec-6 SoC.
Roughly how many clocks
On 02/12/2016 05:39 PM, Rob Herring wrote:
On Thu, Feb 11, 2016 at 05:01:03PM +0100, Lars Persson wrote:
Add device tree documentation for the main PLL in the Artpec-6 SoC.
Roughly how many clocks does this SoC have?
It will have 17 clocks declared in the device tree and three
SoC-specific
Initial device tree for the Artpec-6 SoC.
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/artpec6.dtsi | 236 +
1 file changed, 236 insertions(+)
create mode 100644 arch/arm/boot/dts/artpec6.dtsi
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm
Signed-off-by: Lars Persson
Signed-off-by: Jesper Nilsson
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f1fa4f..d32c1aa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -932,6 +932,16 @@ M: Tsahee Zidenberg
S: Maintained
F
s for axis,artpec6-pll1-clock.
- Moved the uart aliases to the board dts.
- Kconfig cleanup.
- Added a device tree binding for the dma configuration.
- Added CONFIG_SYNOPSYS_DWC_ETH_QOS to multi_v7_defconfig.
- Added binding documentation for axis,artpec6-dev-board.
Lars Persson (6):
arm: add d
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/Makefile | 2 ++
arch/arm/boot/dts/artpec6-devboard.dts | 64 ++
2 files changed, 66 insertions(+)
create mode 100644 arch/arm/boot/dts/artpec6-devboard.dts
diff --git a/arch/arm/boot/dts/Makefile b
Signed-off-by: Lars Persson
---
arch/arm/configs/multi_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 8e8b2ac..1149642 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs
This adds device tree bindings for the Artpec-6 SoC.
Signed-off-by: Lars Persson
---
Documentation/devicetree/bindings/arm/axis.txt | 29 ++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/axis.txt
diff --git a/Documentation
Basic machine port for the Artpec-6 SoC from Axis
Communications.
Signed-off-by: Lars Persson
---
arch/arm/Kconfig | 2 +
arch/arm/Makefile| 1 +
arch/arm/mach-artpec/Kconfig | 20 ++
arch/arm/mach-artpec/Makefile| 1 +
arch/arm
The PLL1 clock is a fixed-factor clock with factors derived from boot
mode pins. This driver is a simple wrapper to register the fixed
factor clock according to the pin settings.
Signed-off-by: Lars Persson
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-artpec6.c | 70
Add device tree documentation for the main PLL in the Artpec-6 SoC.
Signed-off-by: Lars Persson
---
Documentation/devicetree/bindings/clock/artpec6.txt | 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
diff --git a
Add clock support for the Artpec-6 SoC port. The ARM parts are in the series
"arm: Add Artpec-6 SoC" and it goes through the arm-soc tree.
Lars Persson (2):
clk: add device tree binding for artpec-6 pll1 clock
clk: add artpec-6 pll1 clock driver
.../devicetree/bindings/clock/a
CONFIG_SYNOPSYS_DWC_ETH_QOS to multi_v7_defconfig.
- Added binding documentation for axis,artpec6-dev-board.
Lars Persson (8):
clk: add device tree binding for artpec-6 pll1 clock
clk: add artpec-6 pll1 clock driver
arm: add device-tree SoC bindings for Axis Artpec-6
arm: dts: add Artpec-6 SoC
Signed-off-by: Lars Persson
Signed-off-by: Jesper Nilsson
---
MAINTAINERS | 10 ++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f1fa4f..d32c1aa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -932,6 +932,16 @@ M: Tsahee Zidenberg
S: Maintained
F
Initial device tree for the Artpec-6 SoC.
Signed-off-by: Lars Persson
---
arch/arm/boot/dts/artpec6.dtsi | 236 +
1 file changed, 236 insertions(+)
create mode 100644 arch/arm/boot/dts/artpec6.dtsi
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm
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