MOVDIR64B (CPUID.0x07.0x0:ECX[bit 28]).
This patch exposes the movdir64b feature to the guest.
The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Liu Jingqi
Cc: Xu Tao
instructions patches.
Liu Jingqi (2):
KVM: x86: expose MOVDIRI CPU feature into VM.
KVM: x86: expose MOVDIR64B CPU feature into VM.
arch/x86/kvm/cpuid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.7.4
MOVDIR64B (CPUID.0x07.0x0:ECX[bit 28]).
This patch exposes the movdir64b feature to the guest.
The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Liu Jingqi
Cc: Xu Tao
instructions patches.
Liu Jingqi (2):
KVM: x86: expose MOVDIRI CPU feature into VM.
KVM: x86: expose MOVDIR64B CPU feature into VM.
arch/x86/kvm/cpuid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.7.4
MOVDIRI(CPUID.0x07.0x0:ECX[bit 27]).
This patch exposes the movdiri feature to the guest.
The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Liu Jingqi
Cc: Xu Tao
MOVDIRI(CPUID.0x07.0x0:ECX[bit 27]).
This patch exposes the movdiri feature to the guest.
The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Liu Jingqi
Cc: Xu Tao
> -Original Message-
> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> Sent: Monday, August 20, 2018 6:16 PM
> To: Liu, Jingqi ; rkrc...@redhat.com;
> t...@linutronix.de;
> mi...@redhat.com; h...@zytor.com
> Cc: x...@kernel.org; k...@vger.kernel.org; linux-kernel@
> -Original Message-
> From: Paolo Bonzini [mailto:pbonz...@redhat.com]
> Sent: Monday, August 20, 2018 6:16 PM
> To: Liu, Jingqi ; rkrc...@redhat.com;
> t...@linutronix.de;
> mi...@redhat.com; h...@zytor.com
> Cc: x...@kernel.org; k...@vger.kernel.org; linux-kernel@
Hi Paolo,
Do you have any comments for the series ?
Thanks
Jingqi
On 7/10/2018 4:54 PM, Jingqi Liu wrote:
A few new features including user wait (umwait, umonitor, tpause)
and direct stores (movdiri and movdir64b) will be available in
Intel Snow Ridge, and need to be exposed to guest VM.
The
Hi Paolo,
Do you have any comments for the series ?
Thanks
Jingqi
On 7/10/2018 4:54 PM, Jingqi Liu wrote:
A few new features including user wait (umwait, umonitor, tpause)
and direct stores (movdiri and movdir64b) will be available in
Intel Snow Ridge, and need to be exposed to guest VM.
The
On 04/07/2018 21:37, Paolo Bonzini wrote:
> On 04/07/2018 15:06, Jingqi Liu wrote:
> > A new control bit(bit 29) in the TEST_CTRL MSR will be introduced to
> > enable detection of split locks.
> >
> > When bit 29 of the TEST_CTRL(33H) MSR is set, the processor causes an
> > #AC exception to be
On 04/07/2018 21:37, Paolo Bonzini wrote:
> On 04/07/2018 15:06, Jingqi Liu wrote:
> > A new control bit(bit 29) in the TEST_CTRL MSR will be introduced to
> > enable detection of split locks.
> >
> > When bit 29 of the TEST_CTRL(33H) MSR is set, the processor causes an
> > #AC exception to be
On 5/8/2018 12:30 AM, Paolo Bonzini wrote:
>
> On 04/05/2018 05:55, Jingqi Liu wrote:
> > The CLDEMOTE instruction hints to hardware that the cache line that
> > contains the linear address should be moved("demoted") from the
> > cache(s) closest to the processor core to a level more distant
On 5/8/2018 12:30 AM, Paolo Bonzini wrote:
>
> On 04/05/2018 05:55, Jingqi Liu wrote:
> > The CLDEMOTE instruction hints to hardware that the cache line that
> > contains the linear address should be moved("demoted") from the
> > cache(s) closest to the processor core to a level more distant
Hi Paolo,
I had changed the Signed-off-by chain.
Could you help to review?
Thanks.
On 5/22/2018 5:01 PM, Liu, Jingqi wrote:
>
> The CLDEMOTE instruction hints to hardware that the cache line that contains
> the linear address should be moved("demoted") from t
Hi Paolo,
I had changed the Signed-off-by chain.
Could you help to review?
Thanks.
On 5/22/2018 5:01 PM, Liu, Jingqi wrote:
>
> The CLDEMOTE instruction hints to hardware that the cache line that contains
> the linear address should be moved("demoted") from t
://software.intel.com/sites/default/files/managed/c5/15/\
> architecture-instruction-set-extensions-programming-reference.pdf
> This patch has a dependency on https://lkml.org/lkml/2018/4/23/928
>
> Signed-off-by: Jingqi Liu <jingqi@intel.com>
> Signed-off-by: Wei Wang <wei.w.
Hi Paolo,
Thanks.
Will you help to modify the Signed-off-by chain ?
Or do I need to submit the second version after modifying the Signed-off-by
chain ?
Thanks,
Jingqi Liu
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Tuesday, May 8, 2018 12:30 AM
To: Liu
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