gt; > TRBE was enabled. And we must prohibit the generation
> > > > of trace while we are in EL1 by clearing the TRFCR_EL1.
> > > >
> > > > For vhe, the EL2 must prevent the EL1 access to the Trace
> > > > Buffer.
> > > >
>
will need to express the same
dependency.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/pci-host-common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/pci-host-common.c
b/drivers/pci/controller/pci-host-common.c
index 6ab694f8d283
We have now three ways of ending up with NO_MSI being set.
Document them.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/msi.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index d9c73c173c14
The few quirks that deal with NO_MSI tend to be copy-paste heavy.
Refactor them so that the hierarchy of conditions is slightly
cleaner.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/quirks.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff
') indicating that implicit
dependency, and use this property to set the NO_MSI flag when
no MSI domain is found at probe time.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/probe.c | 2 ++
include/linux/pci.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/pci
, which still opens the possibility
for another block to provide the MSI functionnality.
Acked-by: Bjorn Helgaas
Reported-by: Frank Wunderlich
Signed-off-by: Thomas Gleixner
[maz: commit message, switched over to msi_domain attribute]
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/pcie
It doesn't have any caller left.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/msi.c | 11 +--
include/linux/msi.h | 1 -
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 79b5a995bd02..d9c73c173c14
.
Acked-by: Bjorn Helgaas
Tested-by: Marek Vasut
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/Kconfig | 1 -
drivers/pci/controller/pcie-rcar-host.c | 352
2 files changed, 170 insertions(+), 183 deletions(-)
diff --git a/drivers/pci/controller/Kconfig
msi_controller had a good, long life as the abstraction for
a driver providing MSIs to PCI devices. But it has been replaced
in all drivers by the more expressive generic MSI framework.
Farewell, struct msi_controller.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
include/linux
that will
*not* be DMA'd to.
Since the rcar platform already has a requirement that this
address should be in the first 4GB of the physical address space,
use the controller's own base address as the capture address.
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/pcie-rcar-host.c | 18
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/pci-hyperv.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/pci/controller/pci-hyperv.c
b/drivers/pci/controller/pci-hyperv.c
index 27a17a1e4a7c..2c014ba7ed4b 100644
--- a/drivers/pci/controller/pci-hyperv.c
+++ b/drivers
, since I cannot test it.
Acked-by: Bjorn Helgaas
Tested-by: Bharat Kumar Gogada
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-xilinx.c | 242 ---
2 files changed, 106 insertions(+), 138 deletions(-)
diff
As there is no driver using msi_controller, we can now safely
remove its use from the PCI probe code.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/msi.c | 23 +--
drivers/pci/probe.c | 2 --
include/linux/pci.h | 2 --
3 files changed, 1 insertion
that will
*not* be DMA'd to.
Use the physical address of the 'port' data structure as the MSI
capture address, aligned on a 4K boundary.
Tested-by: Bharat Kumar Gogada
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/pcie-xilinx.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions
Marc's draft]
Signed-off-by: Thierry Reding
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/Kconfig | 1 -
drivers/pci/controller/pci-tegra.c | 343 -
2 files changed, 185 insertions(+), 159 deletions(-)
diff --git a/drivers/pci/controller/Kconfig b
space")
- Fixed rcar resume code
- Reworked commit messages
- Rebased onto v5.12-rc4
- Collected Acks, and TBs, with thanks.
[1] https://lore.kernel.org/r/20210225151023.3642391-1-...@kernel.org
[2] https://lore.kernel.org/r/20210322184614.802565-1-...@kernel.org
Marc Zyngier (13):
From: Jianyong Wu
Add clocksource id to the ARM generic counter so that it can be easily
identified from callers such as ptp_kvm.
Cc: Mark Rutland
Reviewed-by: Andre Przywara
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-6
From: Jianyong Wu
Implement the hypervisor side of the KVM PTP interface.
The service offers wall time and cycle count from host to guest.
The caller must specify whether they want the host's view of
either the virtual or physical counter.
Signed-off-by: Jianyong Wu
Signed-off-by: Marc
-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-8-jianyong...@arm.com
---
drivers/clocksource/arm_arch_timer.c | 34
drivers/ptp/Kconfig | 2 +-
drivers/ptp/Makefile | 1 +
drivers/ptp/ptp_kvm_arm.c
to
take the snapshot and act accordingly.
Signed-off-by: Thomas Gleixner
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r/20201209060932.212364-5-jianyong...@arm.com
---
include/linux/clocksource.h | 6 ++
include/linux/clocksource_ids.h | 11
From: Jianyong Wu
Currently, the ptp_kvm module contains a lot of x86-specific code.
Let's move this code into a new arch-specific file in the same directory,
and rename the arch-independent file to ptp_kvm_common.c.
Reviewed-by: Andre Przywara
Signed-off-by: Jianyong Wu
Signed-off-by: Marc
From: Will Deacon
We can advertise ourselves to guests as KVM and provide a basic features
bitmap for discoverability of future hypervisor services.
Cc: Marc Zyngier
Signed-off-by: Will Deacon
Signed-off-by: Jianyong Wu
Signed-off-by: Marc Zyngier
Link: https://lore.kernel.org/r
Given that this series[0] has languished in my Inbox for the best of the
past two years, and in an effort to eventually get it merged, I've
taken the liberty to pick it up and do the changes I wanted to see
instead of waiting to go through yet another round.
All the patches have a link to their
compatible with KVM. Once this has been established,
additional services can be discovered via a feature bitmap.
Reviewed-by: Steven Price
Signed-off-by: Will Deacon
Signed-off-by: Jianyong Wu
[maz: move code to its own file, plug it into PSCI]
Signed-off-by: Marc Zyngier
Link: https://lore.ke
On Tue, 30 Mar 2021 14:06:37 +0100,
Lorenzo Pieralisi wrote:
>
> On Tue, Mar 30, 2021 at 12:05:46PM +0100, Lorenzo Pieralisi wrote:
> > On Tue, Mar 30, 2021 at 11:33:13AM +0100, Marc Zyngier wrote:
> > > [+Lorenzo, +Julien on an actual email address]
> > >
>
On Tue, 30 Mar 2021 14:34:23 +0100,
Suzuki K Poulose wrote:
>
> On 30/03/2021 13:15, Marc Zyngier wrote:
> > On Tue, 30 Mar 2021 12:12:49 +0100,
> > Suzuki K Poulose wrote:
[...]
> >> May be we could do this check at kvm_arch_vcpu_load()/put() ?
> >
> >
On Tue, 30 Mar 2021 12:12:49 +0100,
Suzuki K Poulose wrote:
>
> Hi Marc
>
> On 30/03/2021 11:12, Marc Zyngier wrote:
> > Hi Suzuki,
> >
> > [+ Alex]
> >
> > On Tue, 23 Mar 2021 12:06:35 +,
> > Suzuki K Poulose wrote:
> >>
>
[+Lorenzo, +Julien on an actual email address]
On Tue, 30 Mar 2021 11:06:19 +0100,
Lecopzer Chen wrote:
>
> When pseudo-NMI enabled, register_nmi() set priority of specific IRQ
> by byte ops, and this doesn't work in GIC-600.
>
> We have asked ARM Support [1]:
> > Please refer to following
revent the EL1 access to the Trace
> > Buffer.
> >
> > Cc: Will Deacon
> > Cc: Catalin Marinas
> > Cc: Marc Zyngier
> > Cc: Mark Rutland
> > Cc: Anshuman Khandual
> > Acked-by: Mathieu Poirier
> > Signed-off-by: Suzuki K Poulose
> >
the guest, we must flush any trace data if the
> TRBE was enabled. And we must prohibit the generation
> of trace while we are in EL1 by clearing the TRFCR_EL1.
>
> For vhe, the EL2 must prevent the EL1 access to the Trace
> Buffer.
>
> Cc: Will Deacon
> Cc: Catalin Mari
On Mon, 29 Mar 2021 11:38:04 +0100,
Jingyi Wang wrote:
>
>
>
> On 3/29/2021 5:55 PM, Marc Zyngier wrote:
> > On Mon, 29 Mar 2021 09:52:08 +0100,
> > Jingyi Wang wrote:
> >>
> >> IRM, bit[40] in ICC_SGI1R, determines how the generated SGIs
>
On Mon, 29 Mar 2021 09:52:10 +0100,
Jingyi Wang wrote:
>
> Currently, arm use gic_ipi_send_mask() to inject single IPI, which
> make the procedure a little complex. We use gic_ipi_send_single()
> instead as some other archs.
>
> Signed-off-by: Jingyi Wang
> ---
> arch/arm/kernel/smp.c | 16
On Mon, 29 Mar 2021 09:52:08 +0100,
Jingyi Wang wrote:
>
> IRM, bit[40] in ICC_SGI1R, determines how the generated SGIs
> are distributed to PEs. If the bit is set, interrupts are routed
> to all PEs in the system excluding "self". We use cpumask to
> determine if this bit should be set and make
On Sat, 27 Mar 2021 20:29:04 +,
Pali Rohár wrote:
>
> On Saturday 27 March 2021 19:44:30 Marc Zyngier wrote:
> > On Sat, 27 Mar 2021 19:28:37 +,
> > Pali Rohár wrote:
> > >
> > > On Wednesday 24 March 2021 11:05:08 Jianjun Wang wrote:
> > &g
On Sat, 27 Mar 2021 19:28:37 +,
Pali Rohár wrote:
>
> On Wednesday 24 March 2021 11:05:08 Jianjun Wang wrote:
> > +static void mtk_pcie_msi_handler(struct mtk_pcie_port *port, int set_idx)
> > +{
> > + struct mtk_msi_set *msi_set = >msi_sets[set_idx];
> > + unsigned long msi_enable,
On Fri, 26 Mar 2021 01:02:43 +,
"Dey, Megha" wrote:
>
> Hi Marc,
>
> On 3/25/2021 10:53 AM, Marc Zyngier wrote:
> > On Fri, 26 Feb 2021 20:11:17 +,
> > Megha Dey wrote:
> >> From: Dave Jiang
> >>
> >> Add new
On Thu, 25 Mar 2021 18:59:48 +,
Thomas Gleixner wrote:
>
> On Thu, Mar 25 2021 at 17:23, Marc Zyngier wrote:
> >> +{
> >> + struct irq_desc *desc;
> >> + struct irq_data *data;
> >> + unsigned long flags;
> >> + int res = -ENODEV;
On Thu, 25 Mar 2021 18:44:48 +,
Thomas Gleixner wrote:
>
> On Thu, Mar 25 2021 at 17:08, Marc Zyngier wrote:
> > Megha Dey wrote:
> >> @@ -434,6 +434,12 @@ int __msi_domain_alloc_irqs(struct irq_domain
> >> *domain, struct device *dev,
> >>
On Fri, 26 Feb 2021 20:11:17 +,
Megha Dey wrote:
>
> From: Dave Jiang
>
> Add new helpers to get the Linux IRQ number and device specific index
> for given device-relative vector so that the drivers don't need to
> allocate their own arrays to keep track of the vectors and hwirq for
> the
On Fri, 26 Feb 2021 20:11:16 +,
Megha Dey wrote:
>
> Generic IMS(Interrupt Message Store) irq chips and irq domain
> implementations for IMS based devices which store the interrupt messages
> in an array in device memory.
>
> Allocation and freeing of interrupts happens via the generic
>
On Fri, 26 Feb 2021 20:11:12 +,
Megha Dey wrote:
>
> Introduce a new function pointer in the irq_chip structure(irq_set_auxdata)
> which is responsible for updating data which is stored in a shared register
> or data storage. For example, the idxd driver uses the auxiliary data API
> to
On Fri, 26 Feb 2021 20:11:11 +,
Megha Dey wrote:
>
> From: Thomas Gleixner
>
> For devices which don't have a standard storage for MSI messages like the
> upcoming IMS (Interrupt Message Store) it's required to allocate storage
> space before allocating interrupts and after freeing them.
>
On Fri, 19 Mar 2021 10:01:08 +, Quentin Perret wrote:
> This is the v6 of the series previously posted here:
>
> https://lore.kernel.org/r/20210315143536.214621-1-qper...@google.com/
>
> This basically allows us to wrap the host with a stage 2 when running in
> nVHE, hence paving the way
On Wed, 24 Mar 2021 18:05:46 +,
Will Deacon wrote:
>
> On Fri, Mar 05, 2021 at 06:38:36AM +0900, Hector Martin wrote:
> > From: Marc Zyngier
> >
> > It seems that the CPU known as Apple M1 has the terrible habit
> > of being stuck with HCR_EL2.E2H==1, in
On Mon, 22 Mar 2021 14:01:52 +0800, Shenming Lu wrote:
> In GICv4.1, migration has been supported except for (directly-injected)
> VLPI. And GICv4.1 Spec explicitly gives a way to get the VLPI's pending
> state (which was crucially missing in GICv4.0). So we make VLPI migration
> capable on
On Wed, 24 Mar 2021 17:19:36 +,
Catalin Marinas wrote:
>
> On Wed, Mar 24, 2021 at 05:06:58PM +, Suzuki K Poulose wrote:
> > On 24/03/2021 16:30, Marc Zyngier wrote:
> > >
> > > OK, so we definitely do need these patches, don't we? Both? Just one?
> >
On Sat, 20 Mar 2021 18:16:04 +,
Jonathan Neuschäfer wrote:
>
> The WPCM450 AIC ("Advanced Interrupt Controller") is the interrupt
> controller found in the Nuvoton WPCM450 SoC and other Winbond/Nuvoton
> SoCs.
>
> The list of registers if based on the AMI vendor kernel and the
> Nuvoton
On Wed, 24 Mar 2021 16:25:12 +,
Suzuki K Poulose wrote:
>
> On 24/03/2021 16:16, Marc Zyngier wrote:
> > On Wed, 24 Mar 2021 15:51:14 +,
> > Suzuki K Poulose wrote:
> >>
> >> On 24/03/2021 13:49, Marc Zyngier wrote:
> >>> On Wed, 24
vectors are composed of 8 sets,
> each set has its own address for MSI message, and supports 32 MSI vectors
> to generate interrupt.
>
> Signed-off-by: Jianjun Wang
> Acked-by: Ryder Lee
Reviewed-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
On Wed, 24 Mar 2021 03:05:07 +,
Jianjun Wang wrote:
>
> Add INTx support for MediaTek Gen3 PCIe controller.
>
> Signed-off-by: Jianjun Wang
> Acked-by: Ryder Lee
Reviewed-by: Marc Zyngier
M.
--
Without deviation from the norm, progress is not possible.
On Wed, 24 Mar 2021 15:51:14 +,
Suzuki K Poulose wrote:
>
> On 24/03/2021 13:49, Marc Zyngier wrote:
> > On Wed, 24 Mar 2021 09:39:13 +,
> > Suzuki K Poulose wrote:
> >>
> >> On 23/03/2021 18:21, Catalin Marinas wrote:
> >>> Hi Suzuki?
On Wed, 24 Mar 2021 13:19:38 +,
Lorenzo Pieralisi wrote:
>
> On Tue, Mar 23, 2021 at 06:09:36PM +, Marc Zyngier wrote:
> > Hi Robin,
> >
> > On Tue, 23 Mar 2021 11:45:02 +,
> > Robin Murphy wrote:
> > >
> > > On 2021-03-22 18
On Wed, 24 Mar 2021 13:56:16 +,
Bharat Kumar Gogada wrote:
> > Thanks for that. Can you please try the following patch and let me know if
> > it
> > helps?
> >
> > Thanks,
> >
> > M.
> >
> > diff --git a/drivers/pci/controller/pcie-xilinx.c
> > b/drivers/pci/controller/pcie-
> >
On Wed, 24 Mar 2021 09:39:13 +,
Suzuki K Poulose wrote:
>
> On 23/03/2021 18:21, Catalin Marinas wrote:
> > Hi Suzuki?
> >
> > On Tue, Mar 23, 2021 at 12:06:33PM +, Suzuki K Poulose wrote:
> >> tsb csync synchronizes the trace operation of instructions.
> >> The instruction is a nop
ded not to even try, since I
> > cannot test it.
> >
> > Acked-by: Bjorn Helgaas
> > Signed-off-by: Marc Zyngier
> > ---
> > drivers/pci/controller/Kconfig | 2 +-
> > drivers/pci/controller/pcie-xilinx.c | 234 +++
> &g
; > *not* be DMA'd to.
> >
> > Use the physical address of the 'port' data structure as the MSI capture
> > address.
> >
> > Signed-off-by: Marc Zyngier
> > ---
> > drivers/pci/controller/pcie-xilinx.c | 18 ++
> >
5:
> > - No change
> >
> > drivers/irqchip/irq-loongson-liointc.c | 58 ++
> > 1 file changed, 49 insertions(+), 9 deletions(-)
>
> Marc, if you are ok with this change, I'd like to apply the series
> to mips-next...
Sure. Feel free to add my
Acked-by: Marc Zyngier
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
On Tue, 23 Mar 2021 22:06:22 +,
Nick Desaulniers wrote:
>
> On Tue, Mar 23, 2021 at 6:18 AM Arnd Bergmann wrote:
> >
> > From: Arnd Bergmann
> >
> > When building with extra warnings enabled, clang points out a
> > mistake in the error handling:
> >
> >
On Tue, 23 Mar 2021 10:06:39 +,
Thierry Reding wrote:
[...]
> Obviously if we don't integrate this with IRQs directly, it becomes a
> bit more difficult to relate the captured timestamps to the events
> across subsystem boundaries. I'm not sure how this would be solved
> properly. If the
Hi Robin,
On Tue, 23 Mar 2021 11:45:02 +,
Robin Murphy wrote:
>
> On 2021-03-22 18:46, Marc Zyngier wrote:
> > The new 'no_msi' attribute solves the problem of advertising the lack
> > of MSI capability for host bridges that know for sure that there will
> > be no
On Tue, 23 Mar 2021 12:06:28 +, Suzuki K Poulose wrote:
> This series enables future IP trace features Embedded Trace Extension
> (ETE) and Trace Buffer Extension (TRBE). This series applies on
> v5.12-rc4 + some patches queued. A standalone tree is also available here [0].
> The queued
On Tue, 23 Mar 2021 12:06:28 +, Suzuki K Poulose wrote:
> This series enables future IP trace features Embedded Trace Extension
> (ETE) and Trace Buffer Extension (TRBE). This series applies on
> v5.12-rc4 + some patches queued. A standalone tree is also available here [0].
> The queued
can still access the TRFCR_EL1 unless we trap it.
This will also make sure that the guest cannot fiddle with
the filtering controls set by a nvhe host.
Cc: Marc Zyngier
Cc: Will Deacon
Cc: Mark Rutland
Cc: Catalin Marinas
Signed-off-by: Suzuki K Poulose
We have already have the v8.4 self
will need to express the same
dependency.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/pci-host-common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/pci-host-common.c
b/drivers/pci/controller/pci-host-common.c
index 6ab694f8d283
-by: Bjorn Helgaas
Signed-off-by: Thomas Gleixner
[maz: commit message]
Signed-off-by: Marc Zyngier
---
drivers/pci/probe.c | 2 ++
include/linux/pci.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index fb04fc81a8bd..146bd85c037e 100644
--- a/drivers
time.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/probe.c | 2 +-
include/linux/pci.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 146bd85c037e..bac9f69a06a8 100644
--- a/drivers/pci/probe.c
+++ b
The few quirks that deal with NO_MSI tend to be copy-paste heavy.
Refactor them so that the hierarchy of conditions is slightly
cleaner.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/quirks.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff
.
Acked-by: Bjorn Helgaas
Reported-by: Frank Wunderlich
Signed-off-by: Thomas Gleixner
[maz: commit message]
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/pcie-mediatek.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/pcie-mediatek.c
b/drivers/pci/controller
We have now 4 ways of ending up with NO_MSI being set.
Document them.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/msi.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index d9c73c173c14
As there is no driver using msi_controller, we can now safely
remove its use from the PCI probe code.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/msi.c | 23 +--
drivers/pci/probe.c | 2 --
include/linux/pci.h | 2 --
3 files changed, 1 insertion
It doesn't have any caller left.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/msi.c | 11 +--
include/linux/msi.h | 1 -
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 79b5a995bd02..d9c73c173c14
msi_controller had a good, long life as the abstraction for
a driver providing MSIs to PCI devices. But it has been replaced
in all drivers by the more expressive generic MSI framework.
Farewell, struct msi_controller.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
include/linux
.
Acked-by: Bjorn Helgaas
Tested-by: Marek Vasut
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/Kconfig | 1 -
drivers/pci/controller/pcie-rcar-host.c | 352
2 files changed, 170 insertions(+), 183 deletions(-)
diff --git a/drivers/pci/controller/Kconfig
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/pci-hyperv.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/pci/controller/pci-hyperv.c
b/drivers/pci/controller/pci-hyperv.c
index 27a17a1e4a7c..2c014ba7ed4b 100644
--- a/drivers/pci/controller/pci-hyperv.c
+++ b/drivers
try, since I cannot test it.
Acked-by: Bjorn Helgaas
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-xilinx.c | 234 +++
2 files changed, 97 insertions(+), 139 deletions(-)
diff --git a/drivers/pci/controller
that will
*not* be DMA'd to.
Use the physical address of the 'port' data structure as the MSI
capture address.
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/pcie-xilinx.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx.c
b
that will
*not* be DMA'd to.
Since the rcar platform already has a requirement that this
address should be in the first 4GB of the physical address space,
use the controller's own base address as the capture address.
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/pcie-rcar-host.c | 18
Marc's draft]
Signed-off-by: Thierry Reding
Signed-off-by: Marc Zyngier
---
drivers/pci/controller/Kconfig | 1 -
drivers/pci/controller/pci-tegra.c | 343 -
2 files changed, 185 insertions(+), 159 deletions(-)
diff --git a/drivers/pci/controller/Kconfig b
space")
- Fixed rcar resume code
- Reworked commit messages
- Rebased onto v5.12-rc4
- Collected Acks, and TBs, with thanks.
[1] https://lore.kernel.org/r/20210225151023.3642391-1-...@kernel.org
Marc Zyngier (13):
PCI: tegra: Convert to MSI domains
PCI: rcar: Don't allocate ex
On Mon, 22 Mar 2021 17:40:40 +,
Quentin Perret wrote:
>
> Hey Marc,
>
> On Monday 22 Mar 2021 at 16:48:27 (+), Marc Zyngier wrote:
> > In protected mode, late CPUs are not allowed to boot (enforced by
> > the PSCI relay). We can thus specialise the read_ctr ma
In protected mode, late CPUs are not allowed to boot (enforced by
the PSCI relay). We can thus specialise the read_ctr macro to
always return a pre-computed, sanitised value.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/assembler.h | 9 +
arch/arm64/kernel/image-vars.h | 1
* branch, and not whatever was in my sandbox...
Marc Zyngier (3):
KVM: arm64: Constraint KVM's own __flush_dcache_area to protectected
mode
KVM: arm64: Generate final CTR_EL0 value when running in Protected
mode
KVM: arm64: Drop the CPU_FTR_REG_HYP_COPY infrastructure
arch/arm64
Now that the read_ctr macro has been specialised for nVHE,
the whole CPU_FTR_REG_HYP_COPY infrastrcture looks completely
overengineered.
Simplify it by populating the two u64 quantities (MMFR0 and 1)
that the hypervisor need.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cpufeature.h
As we are about to specialise KVM's version of __flush_dcache_area
via a hack on the read_ctr macro, make sure that we won't ever
use KVM's copy of __flush_dcache_area(), as things would otherwise
break for late arriving CPUs.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/nvhe/cache.S | 4
In protected mode, late CPUs are not allowed to boot (enforced by
the PSCI relay). We can thus specialise the read_ctr macro to
always return a pre-computed, sanitised value.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/assembler.h | 9 +
arch/arm64/kernel/image-vars.h | 1
Now that the read_ctr macro has been specialised for nVHE,
the whole CPU_FTR_REG_HYP_COPY infrastrcture looks completely
overengineered.
Simplify it by populating the two u64 quantities (MMFR0 and 1)
that the hypervisor need.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cpufeature.h
As we are about to specialise KVM's version of __flush_dcache_area
via a hack opn the read_ctr macro, make sure that we won't ever
use KVM's copy of __flush_dcache_area(), as things would otherwise
break for late arriving CPUs.
Signed-off-by: Marc Zyngier
---
arch/arm64/kvm/hyp/nvhe/cache.S | 4
that's sorted, we can easily simplify the whole infrastructure to
only snapshot the two u64 we need before enabling the protected mode.
Tested on a Synquacer system.
M.
Marc Zyngier (3):
KVM: arm64: Constraint KVM's own __flush_dcache_area to protectected
mode
KVM: arm64: Generate
On Mon, 22 Mar 2021 12:33:10 +,
Michal Simek wrote:
>
> Hi,
>
> On 3/22/21 1:21 PM, Lorenzo Pieralisi wrote:
> > On Thu, Feb 25, 2021 at 03:10:13PM +, Marc Zyngier wrote:
> >> In anticipation of the removal of the msi_controller structure, convert
> >>
Hi Lorenzo,
On Mon, 22 Mar 2021 12:23:15 +,
Lorenzo Pieralisi wrote:
>
> On Thu, Feb 25, 2021 at 03:10:13PM +, Marc Zyngier wrote:
> > In anticipation of the removal of the msi_controller structure, convert
> > the ancient xilinx host controller driver to MSI domains.
Hi Quentin,
On Fri, 19 Mar 2021 10:01:21 +,
Quentin Perret wrote:
>
> Introduce the infrastructure in KVM enabling to copy CPU feature
> registers into EL2-owned data-structures, to allow reading sanitised
> values directly at EL2 in nVHE.
>
> Given that only a subset of these features are
On Sat, 20 Mar 2021 14:24:06 +,
Arnd Bergmann wrote:
>
> On Sat, Mar 20, 2021 at 2:23 PM Marc Zyngier wrote:
> >
> > On Sat, 20 Mar 2021 13:03:13 +,
> > Arnd Bergmann wrote:
> > >
> > > On Sat, Mar 20, 2021 at 1:54 PM Marc Zyngier wrote:
On Sat, 20 Mar 2021 13:03:13 +,
Arnd Bergmann wrote:
>
> On Sat, Mar 20, 2021 at 1:54 PM Marc Zyngier wrote:
> > On Fri, 19 Mar 2021 21:12:46 +,
>
> > >
> > > Ugh. pci_root_bus_fwnode() is another callback to find the
> > > irq_domain. Only
Thanks Bjorn for looping me in.
On Fri, 19 Mar 2021 21:12:46 +,
Bjorn Helgaas wrote:
>
> [+cc Arnd (author of 37d6a0a6f470 ("PCI: Add
> pci_register_host_bridge() interface"), which I think would make my
> idea below possible), Marc (IRQ domains maintainer)]
>
> On Sat, Mar 20, 2021 at
Hi Quentin,
On Wed, 17 Mar 2021 14:17:13 +,
Quentin Perret wrote:
>
> In order to further configure stage-2 page-tables, pass flags to the
> init function using a new enum.
>
> The first of these flags allows to disable FWB even if the hardware
> supports it as we will need to do so for
CONSTRAINED UNPREDICTABLE to deliver a vSGI to a PE with
> ID_AA64PFR0_EL1.GIC < b0011.
>
> Check the GIC CPUIF version by reading the SYS_ID_AA64_PFR0_EL1.
>
> Disable vSGIs if a CPUIF version < 4.1 is detected to prevent using
> vSGIs on systems where they may misbehave.
On Wed, 17 Mar 2021 09:48:09 +,
Maulik Shah wrote:
>
> Hi Marc,
>
> On 3/17/2021 2:47 PM, Marc Zyngier wrote:
> > On Wed, 17 Mar 2021 05:29:54 +,
> > Maulik Shah wrote:
> >> PDC interrupt controller driver do not use second reg. Remove it.
> >
On Wed, 17 Mar 2021 10:55:00 +,
Paolo Bonzini wrote:
>
> On 17/03/21 11:53, Marc Zyngier wrote:
> > On Wed, 17 Mar 2021 10:40:23 +,
> > Paolo Bonzini wrote:
> >>
> >> On 17/03/21 10:10, Marc Zyngier wrote:
> >>>> @@ -366,7 +366,7
On Wed, 17 Mar 2021 10:40:23 +,
Paolo Bonzini wrote:
>
> On 17/03/21 10:10, Marc Zyngier wrote:
> >> @@ -366,7 +366,7 @@ static int hyp_map_walker(u64 addr, u64 end, u32
> >> level, kvm_pte_t *ptep,
> >>if (WARN_ON(level == KVM_PGTABLE_MAX_LEVELS - 1
On Wed, 17 Mar 2021 05:29:54 +,
Maulik Shah wrote:
>
> PDC interrupt controller driver do not use second reg. Remove it.
This is a DT file, not a driver. What the driver does is irrelevant.
The real question is: what does this range do?
Thanks,
M.
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