results are
> attached.
I came up with the following patch, which allows the kernel to link
and boot. I don't have any BE userspace, so I didn't verify that I
could boot a guest (the hypervisor does correctly initialise though).
It's not exactly pretty, but it does the job...
Thanks,
Hi Guenter,
Thanks a lot for the heads up.
On 2021-01-29 21:43, Guenter Roeck wrote:
Hi,
On Tue, Jan 05, 2021 at 06:05:37PM +, David Brazdil wrote:
Add a post-processing step to compilation of KVM nVHE hyp code which
calls a custom host tool (gen-hyprel) on the partially linked object
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: 4c457e8cb75eda91906a4f89fc39bde3f9a43922
Gitweb:
https://git.kernel.org/tip/4c457e8cb75eda91906a4f89fc39bde3f9a43922
Author:Marc Zyngier
AuthorDate:Sat, 23 Jan 2021 12:27:59
Committer
On 2021-01-28 09:34, Suzuki K Poulose wrote:
On 1/27/21 9:58 AM, Marc Zyngier wrote:
On 2021-01-27 08:55, Anshuman Khandual wrote:
From: Suzuki K Poulose
When the kernel is booted at EL2 in a nvhe configuration,
enable the TRBE access to the EL1. The EL1 still can't trace
EL2, unless EL2
On 2021-01-28 02:37, Biwen Li (OSS) wrote:
-Original Message-
From: Marc Zyngier
Sent: 2021年1月27日 19:38
To: Biwen Li (OSS)
Cc: mark.rutl...@arm.com; Leo Li ;
t...@linutronix.de;
ja...@lakedaemon.net; linux-kernel@vger.kernel.org; Jiafei Pan
; linux-arm-ker...@lists.infradead.org; Ran
On 2021-01-27 12:31, Jianjun Wang wrote:
On Tue, 2021-01-26 at 13:57 +, Marc Zyngier wrote:
On 2021-01-13 11:39, Jianjun Wang wrote:
> Add MSI support for MediaTek Gen3 PCIe controller.
>
> This PCIe controller supports up to 256 MSI vectors, the MSI hardware
> block diagram i
On 2021-01-27 08:58, Biwen Li wrote:
From: Biwen Li
Add flag IRQCHIP_SKIP_SET_WAKE to remove call trace as follow,
...
[ 45.605239] Unbalanced IRQ 120 wake disable
[ 45.609445] WARNING: CPU: 0 PID: 1124 at kernel/irq/manage.c:800
irq_set_irq_wake+0x154/0x1a0
...
[ 45.645141] pstate:
Zyngier
Cc: Mark Rutland
cc: Anshuman Khandual
Signed-off-by: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
Acked-by: Marc Zyngier
One comment below, though:
---
arch/arm64/include/asm/el2_setup.h | 19 +++
arch/arm64/include/asm/kvm_arm.h | 2 ++
2 files changed, 21
There isn't much that a VHE kernel needs on top of whatever has
been done for nVHE, so let's move the little we need to the
VHE stub (the SPE setup), and drop the init_el2_state macro.
No expected functional change.
Signed-off-by: Marc Zyngier
Acked-by: David Brazdil
---
arch/arm64/kernel/hyp
Signed-off-by: Marc Zyngier
Reviewed-by: Suzuki K Poulose
Acked-by: David Brazdil
---
arch/arm64/include/asm/cpufeature.h | 6 +
arch/arm64/kernel/cpufeature.c | 42 -
2 files changed, 42 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/cpufe
Turning the MMU on is a popular sport in the arm64 kernel, and
we do it more than once, or even twice. As we are about to add
even more, let's turn it into a macro.
No expected functional change.
Signed-off-by: Marc Zyngier
Acked-by: Catalin Marinas
Acked-by: David Brazdil
---
arch/arm64
calls this new hypercall yet, so no functional change.
Signed-off-by: Marc Zyngier
Acked-by: David Brazdil
---
arch/arm64/include/asm/virt.h | 7 +++-
arch/arm64/kernel/hyp-stub.S | 76 ++-
2 files changed, 80 insertions(+), 3 deletions(-)
diff --git a/arch
833-1-...@kernel.org
[2] https://lore.kernel.org/r/20210104135011.2063104-1-...@kernel.org
[3] https://lore.kernel.org/r/2021032811.2455113-1-...@kernel.org
[4] https://lore.kernel.org/r/20210118094533.2874082-1-...@kernel.org
Marc Zyngier (20):
arm64: Fix labels in el2_setup macros
arm64:
On Fri, 15 Jan 2021 14:39:40 +0530, Vinod Koul wrote:
> Add the compatible string for SM8250 SoC from Qualcomm. This compatible
> is used already in DTS files but not documented yet
Applied to irq/irqchip-5.12, thanks!
[1/2] dt-bindings: qcom,pdc: Add compatible for SM8250
commit:
Hi Yanan,
On 2021-01-26 13:41, Yanan Wang wrote:
Hi all,
This series enable CPU TTRem feature for stage-2 page table and a RFC
is sent
for some comments, thanks.
The ARMv8.4 TTRem feature offers 3 levels of support when changing
block
size without changing any other parameters that are
On 2021-01-26 11:00, Biwen Li wrote:
From: Biwen Li
Add flag IRQCHIP_SKIP_SET_WAKE to remove call trace as follow,
[useless trace]
More importantly, what is the bug that you are fixing?
M.
--
Jazz is not dead. It just smells funny...
On 2021-01-13 11:39, Jianjun Wang wrote:
Add MSI support for MediaTek Gen3 PCIe controller.
This PCIe controller supports up to 256 MSI vectors, the MSI hardware
block diagram is as follows:
+-+
| GIC |
+-+
^
On 2021-01-13 11:39, Jianjun Wang wrote:
Add INTx support for MediaTek Gen3 PCIe controller.
Signed-off-by: Jianjun Wang
Acked-by: Ryder Lee
---
drivers/pci/controller/pcie-mediatek-gen3.c | 163
1 file changed, 163 insertions(+)
diff --git
On Thu, 14 Jan 2021 20:13:47 +0800, Yanan Wang wrote:
> This patch series(v3) make some optimization for stage-2 translation.
>
> About patch-1:
> Procedures of hyp stage-1 map and guest stage-2 map are quite different,
> but they are now tied closely by function kvm_set_valid_leaf_pte().
> So
On 2021-01-25 14:39, Shameerali Kolothum Thodi wrote:
-Original Message-
From: Marc Zyngier [mailto:m...@kernel.org]
Sent: 23 January 2021 12:28
To: linux-kernel@vger.kernel.org
Cc: Thomas Gleixner ; Bjorn Helgaas
; Shameerali Kolothum Thodi
; sta...@vger.kernel.org
Subject: [PATCH
On 2021-01-25 14:19, Ard Biesheuvel wrote:
On Mon, 25 Jan 2021 at 14:54, Marc Zyngier wrote:
On 2021-01-25 12:54, Ard Biesheuvel wrote:
[...]
> This struct now takes up
> - ~100 bytes for the characters themselves (which btw are not emitted
> into __initdata or __initconst)
>
On 2021-01-25 12:54, Ard Biesheuvel wrote:
On Mon, 25 Jan 2021 at 11:53, Marc Zyngier wrote:
Given that the early cpufeature infrastructure has borrowed quite
a lot of code from the kaslr implementation, let's reimplement
the matching of the "nokaslr" option with it.
Signed-of
ad, rewite the EL2 setup macros to use unambiguous labels,
thanks to the usual macro counter trick.
Acked-by: Catalin Marinas
Signed-off-by: Marc Zyngier
Acked-by: David Brazdil
---
arch/arm64/include/asm/el2_setup.h | 24
1 file changed, 12 insertions(+), 12 deletion
The arm64 kernel has long be able to use more than 39bit VAs.
Since day one, actually. Let's rewrite the offending comment.
Signed-off-by: Marc Zyngier
Acked-by: Catalin Marinas
Acked-by: David Brazdil
---
arch/arm64/mm/proc.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On 2021-01-25 13:15, Suzuki K Poulose wrote:
On 1/25/21 10:50 AM, Marc Zyngier wrote:
As we want to be able to disable VHE at runtime, let's match
"id_aa64mmfr1.vh=" from the command line as an override.
This doesn't have much effect yet as our boot code doesn't look
at the cpufeature
On Wed, 6 Jan 2021 10:34:48 +, Andre Przywara wrote:
> a fix to v5, now *really* fixing the wrong priority of SMCCC vs. RNDR
> in arch_get_random_seed_long_early(). Apologies for messing this up
> in v5 and thanks to broonie for being on the watch!
>
> Will, Catalin: it would be much
Hi all,
On Mon, 25 Jan 2021 20:07:56 +,
Oliver Upton wrote:
>
> > That means we have two options:
> > (a) define __hyp_panic_string in a different .c file in all pre-5.9
> > branches, or
> > (b) revert the backported patch.
> >
> > The patch was needed in 5.9 and should stay there. It
As we want to be able to disable VHE at runtime, let's match
"id_aa64mmfr1.vh=" from the command line as an override.
This doesn't have much effect yet as our boot code doesn't look
at the cpufeature, but only at the HW registers.
Signed-off-by: Marc Zyngier
Acked-by: David Brazdil
-by: Srinivas Ramana
Signed-off-by: Marc Zyngier
Link:
https://lore.kernel.org/r/1610152163-16554-2-git-send-email-sram...@codeaurora.org
Reviewed-by: Catalin Marinas
Acked-by: David Brazdil
---
arch/arm64/include/asm/pointer_auth.h | 10 ++
arch/arm64/include/asm/stackprotector.h | 1 +
arch
e=protected" option, even when
booting on a VHE system.
Signed-off-by: Marc Zyngier
Acked-by: Catalin Marinas
Acked-by: David Brazdil
---
Documentation/admin-guide/kernel-parameters.txt | 3 +++
arch/arm64/kernel/idreg-override.c | 2 ++
arch/arm64/kvm/arm.c
In order to map the override of idregs to options that a user
can easily understand, let's introduce yet another option
array, which maps an option to the corresponding idreg options.
Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
Acked-by: David Brazdil
---
arch/arm64/kernel/idreg
Finally we can check whether VHE is disabled on the command line,
and not enable it if that's the user's wish.
Signed-off-by: Marc Zyngier
Acked-by: David Brazdil
---
arch/arm64/kernel/asm-offsets.c | 3 +++
arch/arm64/kernel/hyp-stub.S| 11 +++
2 files changed, 14 insertions
In order to be able to disable Pointer Authentication at runtime,
whether it is for testing purposes, or to work around HW issues,
let's add support for overriding the ID_AA64ISAR1_EL1.{GPI,GPA,API,APA}
fields.
This is further mapped on the arm64.nopauth command-line alias.
Signed-off-by: Marc
As we want to parse more options very early in the kernel lifetime,
let's always map the FDT early. This is achieved by moving that
code out of kaslr_early_init().
No functionnal change expected.
Signed-off-by: Marc Zyngier
Acked-by: Catalin Marinas
Acked-by: David Brazdil
---
arch/arm64
In order to be able to disable BTI at runtime, whether it is
for testing purposes, or to work around HW issues, let's add
support for overriding the ID_AA64PFR1_EL1.BTI field.
This is further mapped on the arm64.nobti command-line alias.
Signed-off-by: Marc Zyngier
Reviewed-by: Catalin Marinas
that needs to know the *real* features of a CPU can still
use read_sysreg_s(), and find the bare, ugly truth.
Signed-off-by: Marc Zyngier
Reviewed-by: Suzuki K Poulose
Acked-by: David Brazdil
---
arch/arm64/include/asm/cpufeature.h | 1 +
arch/arm64/kernel/cpufeature.c | 15 +--
2
For completeness, let's document the HVC_VHE_RESTART stub.
Signed-off-by: Marc Zyngier
Acked-by: David Brazdil
---
Documentation/virt/kvm/arm/hyp-abi.rst | 9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/virt/kvm/arm/hyp-abi.rst
b/Documentation/virt/kvm/arm/hyp
Given that the early cpufeature infrastructure has borrowed quite
a lot of code from the kaslr implementation, let's reimplement
the matching of the "nokaslr" option with it.
Signed-off-by: Marc Zyngier
Acked-by: Catalin Marinas
Acked-by: David Brazdil
---
arch/arm64/kernel/idreg-
y.
Signed-off-by: Marc Zyngier
Acked-by: David Brazdil
---
arch/arm64/kernel/Makefile | 2 +-
arch/arm64/kernel/head.S | 1 +
arch/arm64/kernel/idreg-override.c | 130 +
3 files changed, 132 insertions(+), 1 deletion(-)
create mode 100644
As init_el2_state is now nVHE only, let's simplify it and drop
the VHE setup.
Signed-off-by: Marc Zyngier
Acked-by: David Brazdil
---
arch/arm64/include/asm/el2_setup.h | 36 +++---
arch/arm64/kernel/head.S | 2 +-
arch/arm64/kvm/hyp/nvhe/hyp-init.S | 2
then upgrade the kernel EL to EL2 if possible (the process
is obviously shortened for secondary CPUs).
The resume path is handled similarly to a secondary CPU boot.
Signed-off-by: Marc Zyngier
Acked-by: David Brazdil
---
arch/arm64/kernel/head.S | 38 ++--
arch/arm64
We can now move the initial SCTLR_EL1 setup to be used for both
EL1 and EL2 setup.
Signed-off-by: Marc Zyngier
Acked-by: Catalin Marinas
Acked-by: David Brazdil
---
arch/arm64/kernel/head.S | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/head.S b
On Mon, 18 Jan 2021 13:18:39 +,
David Brazdil wrote:
>
> On Mon, Jan 18, 2021 at 09:45:27AM +, Marc Zyngier wrote:
> > In order to map the override of idregs to options that a user
> > can easily understand, let's introduce yet another option
> > arr
On Mon, 18 Jan 2021 11:25:16 +,
David Brazdil wrote:
>
> On Mon, Jan 18, 2021 at 09:45:16AM +, Marc Zyngier wrote:
> > As we are about to change the way a VHE system boots, let's
> > provide the core helper, in the form of a stub hypercall that
> > enables VHE and
On Mon, 18 Jan 2021 14:46:36 +,
David Brazdil wrote:
>
> On Mon, Jan 18, 2021 at 09:45:30AM +, Marc Zyngier wrote:
> > Given that the early cpufeature infrastructure has borrowed quite
> > a lot of code from the kaslr implementation, let's reimplement
> > the
On Sat, 23 Jan 2021 13:43:52 +,
Catalin Marinas wrote:
>
> On Mon, Jan 18, 2021 at 09:45:24AM +, Marc Zyngier wrote:
> > +struct reg_desc {
> > + const char * const name;
> > + u64 * const val;
> > + u64 * const
On Sat, 23 Jan 2021 14:07:53 +,
Catalin Marinas wrote:
>
> On Mon, Jan 18, 2021 at 09:45:26AM +, Marc Zyngier wrote:
> > diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
> > index 59820f9b8522..bbab2148a2a2 100644
> > --- a/arch/arm64/ker
On Tue, 5 Jan 2021 18:05:33 +, David Brazdil wrote:
> nVHE hyp code is linked into the same kernel binary but executes under
> different memory mappings. If the compiler of hyp code chooses absolute
> addressing for accessing a symbol, the kernel linker will relocate that
> address to a kernel
On Tue, 05 Jan 2021 18:05:41 +,
David Brazdil wrote:
>
> Hyp code used the hyp_symbol_addr helper to force PC-relative addressing
> because absolute addressing results in kernel VAs due to the way hyp
> code is linked. This is not true anymore, so remove the helper and
> update all of its
On Tue, 05 Jan 2021 18:05:36 +,
David Brazdil wrote:
>
> Generating hyp relocations will require referencing positions at a given
> offset from the beginning of hyp sections. Since the final layout will
> not be determined until the linking of `vmlinux`, modify the hyp linker
> script to
Hi Shameer,
On 2021-01-22 09:21, Shameerali Kolothum Thodi wrote:
Hi Marc,
[...]
I find this pretty complicated, and the I'd like to avoid injecting
the PCI
MSI-vs-MSI-X concept in something that is supposed to be bus-agnostic.
Agree. That’s mainly because I was very skeptical(TBH, very
e sure PCI MSIs are activated early")
Reported-by: Shameer Kolothum
Signed-off-by: Marc Zyngier
Cc: sta...@vger.kernel.org
---
include/linux/msi.h | 6 ++
kernel/irq/msi.c| 44
2 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/i
Hi Yanan,
On 2021-01-22 10:13, Yanan Wang wrote:
Hi, Will, Marc,
Is there any further comment on the v3 series I post previously?
None, I was planning to queue them for 5.12 over the weekend.
If they are not fine to you, then I think maybe we should just turn
back to the original solution
On 2021-01-22 08:36, Keqian Zhu wrote:
The MMIO region of a device maybe huge (GB level), try to use block
mapping in stage2 to speedup both map and unmap.
Especially for unmap, it performs TLBI right after each invalidation
of PTE. If all mapping is of PAGE_SIZE, it takes much time to handle
Hi Shameer,
On Thu, 21 Jan 2021 11:02:47 +,
Shameer Kolothum wrote:
>
> We currently do early activation of MSI irqs for PCI/MSI based on
> the MSI_FLAG_ACTIVATE_EARLY flag. Though this activates all the
> allocated MSIs in the case of MSI-X, it only does so for the
> base irq in the case
On Wed, 20 Jan 2021 14:30:06 +0100, Arnd Bergmann wrote:
> A few Arm platforms are getting removed in v5.12, this removes
> the corresponding irqchip drivers.
>
> Link:
> https://lore.kernel.org/linux-arm-kernel/20210120124812.2800027-1-a...@kernel.org/T/
>
>
> Arnd Bergmann (2):
> irqchip:
On Sun, 17 Jan 2021 23:50:30 -0600, Samuel Holland wrote:
> Allwinner sun6i/sun8i/sun50i SoCs (A31 and newer) have two interrupt
> controllers: GIC and R_INTC. GIC does not support wakeup. R_INTC handles
> the external NMI pin, and provides 32+ IRQs to the ARISC. The first 16
> of these correspond
On Wed, 20 Jan 2021 10:10:18 +,
Bert Vermeulen wrote:
>
> Signed-off-by: Bert Vermeulen
Please write a decent commit message.
> ---
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-realtek-rtl.c | 180 ++
> 2 files changed, 181 insertions(+)
On 2021-01-21 17:55, Will Deacon wrote:
On Thu, Jan 21, 2021 at 04:25:54PM +, Marc Zyngier wrote:
On 2021-01-21 15:12, Mohamed Mediouni wrote:
> Please ignore that patch.
>
> It turns out that the PCIe controller on Apple M1 expects posted
> writes and so the memory range
On 2021-01-21 15:12, Mohamed Mediouni wrote:
Please ignore that patch.
It turns out that the PCIe controller on Apple M1 expects posted
writes and so the memory range for it ought to be set nGnRE.
So, we need to use nGnRnE for on-chip MMIO and nGnRE for PCIe BARs.
The MAIR approach isn’t
On 2021-01-21 13:34, Mohamed Mediouni wrote:
On 21 Jan 2021, at 14:22, Marc Zyngier wrote:
On 2021-01-21 12:50, Mohamed Mediouni wrote:
On 21 Jan 2021, at 13:44, Arnd Bergmann wrote:
On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
[...]
+ aic.fast_ipi = of_property_read_bool(node
On 2021-01-21 13:32, Mark Rutland wrote:
On Thu, Jan 21, 2021 at 01:22:37PM +, Marc Zyngier wrote:
On 2021-01-21 12:50, Mohamed Mediouni wrote:
> > On 21 Jan 2021, at 13:44, Arnd Bergmann wrote:
> >
> > On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
[...]
> >
On 2021-01-21 12:50, Mohamed Mediouni wrote:
On 21 Jan 2021, at 13:44, Arnd Bergmann wrote:
On Wed, Jan 20, 2021 at 2:27 PM Mohamed Mediouni
[...]
+ aic.fast_ipi = of_property_read_bool(node, "fast-ipi");
Where is this property documented, and what decides which one to use?
It’s
On 2021-01-21 11:27, Will Deacon wrote:
On Wed, Jan 20, 2021 at 02:27:13PM +0100, Mohamed Mediouni wrote:
Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious
hardware quirk.
On Apple processors, writes using the nGnRE device memory type get
dropped in flight,
getting to
On 2021-01-20 15:48, Greg Kroah-Hartman wrote:
On Wed, Jan 20, 2021 at 03:39:30PM +, Marc Zyngier wrote:
Anyway, I said what I had to say. If platforms break with this
change, I'll expect it to be disabled in 5.12.
I'm thinking we can not change the default and will probably revert
On 2021-01-18 20:38, Saravana Kannan wrote:
On Sun, Jan 17, 2021 at 4:02 AM Marc Zyngier wrote:
Hi Saravana,
Thanks for posting this, much appreciated.
On Sat, 16 Jan 2021 01:14:11 +,
Saravana Kannan wrote:
>
> There are multiple instances of GPIO devictree nodes of the form:
&
On 2021-01-20 13:49, Will Deacon wrote:
On Wed, Jan 20, 2021 at 01:45:24PM +, Andre Przywara wrote:
On Wed, 20 Jan 2021 13:26:26 +
Marc Zyngier wrote:
Hi,
> On 2021-01-20 13:01, Will Deacon wrote:
> > On Wed, 6 Jan 2021 10:34:48 +, Andre Przywara wrote:
> >>
On 2021-01-20 13:01, Will Deacon wrote:
On Wed, 6 Jan 2021 10:34:48 +, Andre Przywara wrote:
a fix to v5, now *really* fixing the wrong priority of SMCCC vs. RNDR
in arch_get_random_seed_long_early(). Apologies for messing this up
in v5 and thanks to broonie for being on the watch!
Will,
Hi Mohamed,
On 2021-01-20 11:36, Mohamed Mediouni wrote:
From: Stan Skowronek
On Apple processors, the timer is wired through FIQ.
Which timer? There are at least 3, potentially 4 timers per CPU
that can fire.
As such, add FIQ support to the kernel.
Signed-off-by: Stan Skowronek
; Justin He ; Mark Rutland
; Gustavo A. R. Silva ;
Richard Henderson ; Dave P Martin
; Steven Price ; Andrew
Morton
; Mike Rapoport ; Ard
Biesheuvel ; Gavin Shan ; Kefeng
Wang
; Mark Brown ; Marc
Zyngier
; Cristian Marussi
Subject: [RFC PATCH 0/2] Avoid booting stall caused by
There is a 10s
On 2021-01-20 09:53, Geert Uytterhoeven wrote:
Hi Saravana,
On Fri, Dec 18, 2020 at 10:11 PM Saravana Kannan
wrote:
Add support for creating device links out of interrupts property.
Cc: Marc Zyngier
Cc: Kevin Hilman
Signed-off-by: Saravana Kannan
Thanks for your patch!
This does
e=protected" option, even when
booting on a VHE system.
Signed-off-by: Marc Zyngier
---
Documentation/admin-guide/kernel-parameters.txt | 3 +++
arch/arm64/kernel/idreg-override.c | 2 ++
arch/arm64/kvm/arm.c| 3 +++
3 files changed, 8 insertions(
As we want to be able to disable VHE at runtime, let's match
"id_aa64mmfr1.vh=" from the command line as an override.
This doesn't have much effect yet as our boot code doesn't look
at the cpufeature, but only at the HW registers.
Signed-off-by: Marc Zyngier
---
arch/arm64/i
-by: Srinivas Ramana
Signed-off-by: Marc Zyngier
Link:
https://lore.kernel.org/r/1610152163-16554-2-git-send-email-sram...@codeaurora.org
---
arch/arm64/include/asm/pointer_auth.h | 10 ++
arch/arm64/include/asm/stackprotector.h | 1 +
arch/arm64/kernel/head.S| 4
3 files
In order to be able to disable Pointer Authentication at runtime,
whether it is for testing purposes, or to work around HW issues,
let's add support for overriding the ID_AA64ISAR1_EL1.{GPI,GPA,API,APA}
fields.
This is further mapped on the arm64.nopauth command-line alias.
Signed-off-by: Marc
For completeness, let's document the HVC_VHE_RESTART stub.
Signed-off-by: Marc Zyngier
---
Documentation/virt/kvm/arm/hyp-abi.rst | 9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/virt/kvm/arm/hyp-abi.rst
b/Documentation/virt/kvm/arm/hyp-abi.rst
index 83cadd8186fa
ad, rewite the EL2 setup macros to use unambiguous labels,
thanks to the usual macro counter trick.
Acked-by: Catalin Marinas
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/el2_setup.h | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm
y.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/Makefile | 2 +-
arch/arm64/kernel/head.S | 1 +
arch/arm64/kernel/idreg-override.c | 119 +
3 files changed, 121 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/kernel/idreg-overri
that needs to know the *real* features of a CPU can still
use read_sysreg_s(), and find the bare, ugly truth.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cpufeature.h | 1 +
arch/arm64/kernel/cpufeature.c | 15 +--
2 files changed, 14 insertions(+), 2 deletions(-)
diff
Finally we can check whether VHE is disabled on the command line,
and not enable it if that's the user's wish.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/hyp-stub.S | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kernel/hyp-stub.S b/arch
Given that the early cpufeature infrastructure has borrowed quite
a lot of code from the kaslr implementation, let's reimplement
the matching of the "nokaslr" option with it.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/idreg-override.c | 17 ++
arch/arm64/kern
As we want to parse more options very early in the kernel lifetime,
let's always map the FDT early. This is achieved by moving that
code out of kaslr_early_init().
No functionnal change expected.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/setup.h | 11 +++
arch/arm64/kernel
In order to map the override of idregs to options that a user
can easily understand, let's introduce yet another option
array, which maps an option to the corresponding idreg options.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/idreg-override.c | 20
1 file changed
On 2021-01-18 19:16, Geert Uytterhoeven wrote:
Hi Marc,
On Mon, Jan 18, 2021 at 6:59 PM Marc Zyngier wrote:
On 2021-01-18 17:39, Geert Uytterhoeven wrote:
> On Fri, Dec 18, 2020 at 4:34 AM Saravana Kannan
> wrote:
>> Cyclic dependencies in some firmware was one of the la
Hi Geert,
On 2021-01-18 17:39, Geert Uytterhoeven wrote:
Hi Saravana,
On Fri, Dec 18, 2020 at 4:34 AM Saravana Kannan
wrote:
Cyclic dependencies in some firmware was one of the last remaining
reasons fw_devlink=on couldn't be set by default. Now that cyclic
dependencies don't block probing,
On 2021-01-18 09:31, Yejune Deng wrote:
In smp_call_function_single(), the 3rd parameter isn't the return value
and it's always positive. But it may return a negative value. So the
'ret' is should be the return value of the smp_call_function_single().
In check_kvm_target_cpu(), 'phys_target' is
In order to be able to disable BTI at runtime, whether it is
for testing purposes, or to work around HW issues, let's add
support for overriding the ID_AA64PFR1_EL1.BTI field.
This is further mapped on the arm64.nobti command-line alias.
Signed-off-by: Marc Zyngier
---
Documentation/admin
calls this new hypercall yet, so no functional change.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/virt.h | 7 +++-
arch/arm64/kernel/hyp-stub.S | 67 +--
2 files changed, 71 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/virt.h b
Turning the MMU on is a popular sport in the arm64 kernel, and
we do it more than once, or even twice. As we are about to add
even more, let's turn it into a macro.
No expected functional change.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/assembler.h | 17 +
arch
The arm64 kernel has long be able to use more than 39bit VAs.
Since day one, actually. Let's rewrite the offending comment.
Signed-off-by: Marc Zyngier
---
arch/arm64/mm/proc.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
As init_el2_state is now nVHE only, let's simplify it and drop
the VHE setup.
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/el2_setup.h | 36 +++---
arch/arm64/kernel/head.S | 2 +-
arch/arm64/kvm/hyp/nvhe/hyp-init.S | 2 +-
3 files changed, 10
We can now move the initial SCTLR_EL1 setup to be used for both
EL1 and EL2 setup.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/head.S | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 36212c05df42
then upgrade the kernel EL to EL2 if possible (the process
is obviously shortened for secondary CPUs).
The resume path is handled similarly to a secondary CPU boot.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/head.S | 38 ++--
arch/arm64/kernel/hyp-stub.S | 24
There isn't much that a VHE kernel needs on top of whatever has
been done for nVHE, so let's move the little we need to the
VHE stub (the SPE setup), and drop the init_el2_state macro.
No expected functional change.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/hyp-stub.S | 28
Signed-off-by: Marc Zyngier
---
arch/arm64/include/asm/cpufeature.h | 2 ++
arch/arm64/kernel/cpufeature.c | 44 +
2 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/cpufeature.h
b/arch/arm64/include/asm/cpufeature.h
index 9a
kernel.org
[3] https://lore.kernel.org/r/2021032811.2455113-1-...@kernel.org
Marc Zyngier (20):
arm64: Fix labels in el2_setup macros
arm64: Fix outdated TCR setup comment
arm64: Turn the MMU-on sequence into a macro
arm64: Provide an 'upgrade to VHE' stub hypercall
arm64: Initialise as nVHE bef
d-up being managed by a
driver that is bound to that particular node.
The node/subnode division is a good way to express some HW boundaries,
but doesn't say anything about the way this should be handled in the
kernel. Assuming that everything containing a "compatible" string will
eventually be bo
On Tue, 29 Dec 2020 16:00:59 +, David Brazdil wrote:
> The KVM/arm64 PSCI relay assumes that SYSTEM_OFF and SYSTEM_RESET should
> not return, as dictated by the PSCI spec. However, there is firmware out
> there which breaks this assumption, leading to a hyp panic. Make KVM
> more robust to
On 2021-01-15 04:01, Samuel Holland wrote:
Hello,
On 1/14/21 3:06 PM, Marc Zyngier wrote:
Hi Samuel,
On 2021-01-12 05:59, Samuel Holland wrote:
[...]
+static void sun6i_r_intc_ack_nmi(void)
+{
+ writel(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0));
writel_relaxed
On Tue, 12 Jan 2021 05:59:44 +,
Samuel Holland wrote:
>
> Maintain bitmaps of wake-enabled IRQs and mux inputs, and program them
> to the hardware during the syscore phase of suspend and shutdown. Then
> restore the original set of enabled IRQs (only the NMI) during resume.
>
> This serves
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