[dropping Jason, whose email address has been bouncing for weeks now]
On 2020-11-07 10:42, Xu Qiang wrote:
On my platform, ITS_FLAGS_SAVE_SUSPEND_STATE is not set,thus do nothing
Which platform?
in its suspend and resuse function.On the other hand,firmware stores
On Tue, 3 Nov 2020 11:30:09 +1100, Gavin Shan wrote:
> The PUD and PMD are folded into PGD when the following options are
> enabled. In that case, PUD_SHIFT is equal to PMD_SHIFT and we fail
> to build with the indicated errors:
>
>CONFIG_ARM64_VA_BITS_42=y
>CONFIG_ARM64_PAGE_SHIFT=16
>
On 2020-11-06 15:30, Ard Biesheuvel wrote:
On Fri, 6 Nov 2020 at 16:30, Marc Zyngier wrote:
[...]
I don't think this cast is safe. At least not on 64bit.
True, but this is arch/arm
I think the glasses theme becomes recurrent. Apologies for the noise.
M.
--
Jazz is not dead
On 2020-11-05 12:56, Andre Przywara wrote:
From: Ard Biesheuvel
Implement arch_get_random_seed_*() for ARM based on the firmware
or hypervisor provided entropy source described in ARM DEN0098.
This will make the kernel's random number generator consume entropy
provided by this interface, at
On 2020-11-04 18:36, David Brazdil wrote:
As we progress towards being able to keep guest state private to the
host running nVHE hypervisor, this series allows the hypervisor to
install itself on newly booted CPUs before the host is allowed to run
on them.
To this end, the hypervisor starts
On 2020-11-05 23:00, Thomas Gleixner wrote:
On Thu, Nov 05 2020 at 09:20, Marc Zyngier wrote:
On 2020-11-04 23:14, Thomas Gleixner wrote:
/* Resource alignment requirements */
resource_size_t (*align_resource)(struct pci_dev *dev,
If that's the direction of travel, we also
On 2020-11-05 15:23, Daniel Palmer wrote:
Hi Marc,
On Thu, 5 Nov 2020 at 21:08, Marc Zyngier wrote:
On 2020-11-05 09:40, Linus Walleij wrote:
> On Mon, Oct 19, 2020 at 4:10 PM Daniel Palmer wrote:
[...]
>> +/* The parent interrupt controller needs the GIC interrupt type set
>
On 2020-11-05 12:56, Andre Przywara wrote:
From: Ard Biesheuvel
Provide a hypervisor implementation of the ARM architected TRNG
firmware
interface described in ARM spec DEN0098. All function IDs are
implemented,
including both 32-bit and 64-bit versions of the TRNG_RND service,
which
is
On 2020-11-05 14:34, Ard Biesheuvel wrote:
On Thu, 5 Nov 2020 at 15:30, Mark Rutland wrote:
On Thu, Nov 05, 2020 at 03:04:57PM +0100, Ard Biesheuvel wrote:
> On Thu, 5 Nov 2020 at 15:03, Mark Rutland wrote:
> > On Thu, Nov 05, 2020 at 01:41:42PM +, Mark Brown wrote:
> > > On Thu, Nov 05,
On 2020-11-05 14:06, xuqiang (M) wrote:
在 2020/11/5 21:12, Marc Zyngier 写道:
Please don't top-post.
On 2020-11-05 11:54, xuqiang (M) wrote:
The kernel sends three commands in the following sequence:
1.mapd(deviceA, ITT_addr1, valid:1)
2.mapti(deviceA):ITS write ITT_addr1 memory;
3.mapd
Please don't top-post.
On 2020-11-05 11:54, xuqiang (M) wrote:
The kernel sends three commands in the following sequence:
1.mapd(deviceA, ITT_addr1, valid:1)
2.mapti(deviceA):ITS write ITT_addr1 memory;
3.mapd(deviceA, ITT_addr1, valid:0) and kfree(ITT_addr1);
4.mapd(deviceA, ITT_addr2,
On 2020-11-05 09:40, Linus Walleij wrote:
On Mon, Oct 19, 2020 at 4:10 PM Daniel Palmer wrote:
[...]
+/* The parent interrupt controller needs the GIC interrupt type set
to GIC_SPI
+ * so we need to provide the fwspec. Essentially
gpiochip_populate_parent_fwspec_twocell
+ * that puts
On 2020-11-04 18:36, David Brazdil wrote:
Add a handler of the CPU_OFF PSCI host SMC trapped in KVM nVHE hyp
code.
When invoked, it changes the recorded state of the core to OFF before
forwarding the call to EL3. If the call fails, it changes the state
back
to ON and returns the error to the
On 2020-11-04 18:36, David Brazdil wrote:
Add handler of host SMCs in KVM nVHE trap handler. Forward all SMCs to
EL3 and propagate the result back to EL1. This is done in preparation
for validating host SMCs.
Signed-off-by: David Brazdil
---
arch/arm64/kvm/hyp/nvhe/hyp-main.c | 36
On 2020-11-04 18:36, David Brazdil wrote:
Function IDs used by PSCI are configurable for v0.1 via DT/APCI. If the
host is using PSCI v0.1, KVM's PSCI proxy needs to use the same IDs.
Expose the array holding the information.
Signed-off-by: David Brazdil
---
drivers/firmware/psci/psci.c | 10
On 2020-11-04 18:36, David Brazdil wrote:
The version of PSCI that the kernel should use to communicate with
firmware is typically obtained from probing PSCI_VERSION. However, that
doesn't work for PSCI v0.1 where the host gets the information from
DT/ACPI, or if PSCI is not supported / was
On 2020-11-04 23:22, Konrad Dybcio wrote:
QCOM KRYO2XX Silver cores are Cortex-A53 based and are
susceptible to the 845719 erratum. Add them to the lookup
list to apply the erratum.
Signed-off-by: Konrad Dybcio
---
arch/arm64/kernel/cpu_errata.c | 2 ++
1 file changed, 2 insertions(+)
diff
On 2020-11-04 23:14, Thomas Gleixner wrote:
[...]
TBH, that's butt ugly. So after staring long enough into the PCI code I
came up with a way to transport that information to the probe code.
That allows a particular device to say 'I can't do MSI' and at the same
time keeps the warning
On Tue, 03 Nov 2020 08:11:23 +,
Xu Qiang wrote:
>
> During wakeup, the ATF restore interface restores the values of
> the cbaser and cwriter registers. As a result, the ITS executes
> the residual commands in the queue, which may cause memory corruption.
>
> To solve this problem, clear all
On 2020-11-03 10:31, Thomas Gleixner wrote:
On Tue, Nov 03 2020 at 09:54, Marc Zyngier wrote:
On 2020-11-02 22:18, Thomas Gleixner wrote:
So we really need some other solution and removing the warning is not
an option. If MSI is enabled then we want to get a warning when a PCI
device has
On 2020-11-03 10:16, Thomas Gleixner wrote:
On Tue, Nov 03 2020 at 09:54, Marc Zyngier wrote:
On 2020-11-02 22:18, Thomas Gleixner wrote:
On Mon, Nov 02 2020 at 17:16, Thomas Gleixner wrote:
On Mon, Nov 02 2020 at 11:30, Marc Zyngier wrote:
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
On 2020-11-02 22:18, Thomas Gleixner wrote:
On Mon, Nov 02 2020 at 17:16, Thomas Gleixner wrote:
On Mon, Nov 02 2020 at 11:30, Marc Zyngier wrote:
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -871,6 +871,8 @@ static void pci_set_bus_msi_domain(struct pci_bus
*bus)
d
On 2020-11-03 05:22, Dongjiu Geng wrote:
On 2020/10/31 17:55, Marc Zyngier wrote:
Dongjiu,
On Sat, 31 Oct 2020 02:19:19 +,
Dongjiu Geng wrote:
Hi Marc,
Sorry to disturb you, Currently the LPI number is not fixed for the
device. The LPI number is dynamically allocated start from 8092
On 2020-11-02 11:56, Frank Wunderlich wrote:
looks good on bananapi-r2, no warning, pcie-card and hdd recognized
Thanks for giving it a shot. Still needs a bit of tweaking, as I expect
it to break configurations that select CONFIG_PCI_MSI_ARCH_FALLBACKS
(we have to assume that MSIs can be
On 2020-11-01 22:27, Thomas Gleixner wrote:
On Sun, Nov 01 2020 at 21:47, Marc Zyngier wrote:
On Sun, 01 Nov 2020 18:27:13 +,
Frank Wunderlich wrote:
Thinking of it a bit more, I think this is the wrong solution.
PCI MSIs are optional, and not a requirement. I can trivially spin a
VM
On Sun, 01 Nov 2020 18:27:13 +,
Frank Wunderlich wrote:
>
> > Gesendet: Sonntag, 01. November 2020 um 18:54 Uhr
> > Von: "Ryder Lee"
>
> > Yea, mt7623 (mtk_pcie_soc_v1) does not support MSI, so that's a way to
> > handle it.
> >
> > @Frank, could you help to test it?
> >
> > Ryder
>
>
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: d26dd4131d0d6ad7aa294a7f8d18782b47c27c93
Gitweb:
https://git.kernel.org/tip/d26dd4131d0d6ad7aa294a7f8d18782b47c27c93
Author:Marc Zyngier
AuthorDate:Fri, 16 Oct 2020 09:28:23 +01:00
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: 893a7cfb6b0bea650fafa43838d7f7f8f0f076bc
Gitweb:
https://git.kernel.org/tip/893a7cfb6b0bea650fafa43838d7f7f8f0f076bc
Author:Marc Zyngier
AuthorDate:Thu, 15 Oct 2020 22:26:26 +01:00
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: 57733e009f0c7e0526e10a18be12f56996c5460e
Gitweb:
https://git.kernel.org/tip/57733e009f0c7e0526e10a18be12f56996c5460e
Author:Marc Zyngier
AuthorDate:Sun, 25 Oct 2020 11:10:29
Committer
The following commit has been merged into the irq/urgent branch of tip:
Commit-ID: 151a535171be6ff824a0a3875553ea38570f4c05
Gitweb:
https://git.kernel.org/tip/151a535171be6ff824a0a3875553ea38570f4c05
Author:Marc Zyngier
AuthorDate:Thu, 15 Oct 2020 21:41:44 +01:00
this. It will do the wrong
thing on normal interrupts.
Signed-off-by: Marc Zyngier
---
include/linux/irq.h | 4 +++-
kernel/irq/debugfs.c | 1 +
kernel/irq/irqdesc.c | 17 -
kernel/irq/settings.h | 7 +++
4 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/include/linux
[1]
https://lore.kernel.org/r/cakftptdjppri5gt6klefp_b_zjuz5dyxeqtj+0vkohu-y9b...@mail.gmail.com
Marc Zyngier (2):
genirq: Allow an interrupt to be marked as 'naked'
arm64: Mark the recheduling IPI as naked interrupt
arch/arm64/kernel/smp.c | 4
include/linux/irq.h | 4 +++-
kernel/irq/debugfs.c| 1 +
Flag the rescheduling IPI as 'naked', making sure such interrupt
doesn't trigger a rescheduling event by itself.
Signed-off-by: Marc Zyngier
---
arch/arm64/kernel/smp.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 82e75fc2c903
irqchip/renesas-intc-irqpin: Merge irlm_bit and needs_irlm
Greentime Hu (2):
irqchip/sifive-plic: Fix broken irq_set_affinity() callback
irqchip/sifive-plic: Fix chip_data access within a hierarchy
Marc Zyngier (4):
genirq: Let GENERIC_IRQ_IPI select IRQ_DOMAIN_HIERARCHY
On Thu, 29 Oct 2020 10:37:38 +0800, Greentime Hu wrote:
> This oops is caused by a wrong chip_data and it is because plic_irq_unmask
> uses irq_get_chip_data(irq_data->irq) to get the chip_data. However it may
> get another irq_data with the same irq_data->irq if it is hierarchy.
>
> In this
On Wed, 28 Oct 2020 16:39:55 +0100, Geert Uytterhoeven wrote:
> Get rid of the separate flag to indicate if the IRLM bit is present in
> the INTC/Interrupt Control Register 0, by considering -1 an invalid
> irlm_bit value.
Applied to irq/irqchip-next, thanks!
[1/1] irqchip/renesas-intc-irqpin:
On Tue, 20 Oct 2020 10:32:41 +0300, Peter Ujfalusi wrote:
> Changes since v2:
> - Extended the block diagram of INTA in the DT documentation
> - Use less creative variable names for unmapped events in the driver
> - Short comment section to describe the unmapped event handling in driver
> - Use
On Sun, 01 Nov 2020 09:25:04 +,
Frank Wunderlich wrote:
>
> Am 31. Oktober 2020 22:49:14 MEZ schrieb Thomas Gleixner :
>
> >That's not a fix. It's just supressing the warning.
>
> Ok sorry
>
> >So it needs to be figured out why the domain association is not there.
>
> It looks like for
On Sat, 31 Oct 2020 03:10:24 +,
Dongjiu Geng wrote:
[...]
> Sorry for the noise, Because Marc rarely uses the ARM email address,
> so I replace to use Marc's kernel.org address instead of ARM email address.
Rarely is quite the understatement. I left ARM over a year ago, so the
Dongjiu,
On Sat, 31 Oct 2020 02:19:19 +,
Dongjiu Geng wrote:
>
> Hi Marc,
> Sorry to disturb you, Currently the LPI number is not fixed for the
> device. The LPI number is dynamically allocated start from 8092.
> For two OS which shares the ITS, One OS needs to configure the
> device
On Mon, 26 Oct 2020 14:44:23 +, Will Deacon wrote:
> For consistency with the rest of the stage-2 page-table page allocations
> (performing using a kvm_mmu_memory_cache), ensure that __GFP_ACCOUNT is
> included in the GFP flags for the PGD pages.
Applied to next, thanks!
[1/1] KVM: arm64:
On Mon, 26 Oct 2020 16:54:06 +0530, Santosh Shukla wrote:
> Description of the Reproducer scenario as asked in the thread [1].
>
> Tried to create the reproducer scenario with vfio-pci driver using
> nvidia GPU in PT mode, As because vfio-pci driver now supports
> vma faulting
On Thu, 29 Oct 2020 14:47:16 +, Will Deacon wrote:
> stage2_pte_cacheable() tries to figure out whether the mapping installed
> in its 'pte' parameter is cacheable or not. Unfortunately, it fails
> miserably because it extracts the memory attributes from the entry using
> FIELD_GET(), which
On Mon, 26 Oct 2020 10:06:26 +1100, Gavin Shan wrote:
> The huge page could be mapped through multiple contiguous PMDs or PTEs.
> The corresponding huge page sizes aren't supported by the page table
> walker currently.
>
> This fails the unsupported huge page sizes to the near one. Otherwise,
>
lean this up so that KVM tells the guest this mapping:
0 is SPECTRE_MITIGATED
1 is SPECTRE_UNAFFECTED
SMCCC_RET_NOT_SUPPORTED is SPECTRE_VULNERABLE
Note: SMCCC_RET_NOT_AFFECTED is 1 but isn't part of the SMCCC spec
Cc: Andre Przywara
Cc: Steven Price
Cc: Marc Zyngier
Cc: sta...@vger.ke
Hi Alexey,
On 2020-10-27 09:06, Alexey Kardashevskiy wrote:
PCI devices share 4 legacy INTx interrupts from the same PCI host
bridge.
Device drivers map/unmap hardware interrupts via irq_create_mapping()/
irq_dispose_mapping(). The problem with that these interrupts are
shared and when
On 2020-10-27 11:21, Vincent Guittot wrote:
On Tue, 27 Oct 2020 at 11:50, Vincent Guittot
wrote:
On Tue, 27 Oct 2020 at 11:37, Marc Zyngier wrote:
>
> On 2020-10-27 10:12, Vincent Guittot wrote:
> > HI Marc,
> >
> > On Mon, 19 Oct 2020 at 17:43, Vincent Guittot
>
On 2020-10-27 10:35, Biwen Li (OSS) wrote:
On 2020-10-27 04:46, Biwen Li wrote:
> From: Hou Zhiqiang
>
> Add an new IRQ chip declaration for LS1043A and LS1088A
> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A.
> SCFG_INTPCR[31:0]
> of these SoCs is stored/read as SCFG_INTPCR[0:31]
On 2020-10-27 10:12, Vincent Guittot wrote:
HI Marc,
On Mon, 19 Oct 2020 at 17:43, Vincent Guittot
wrote:
On Mon, 19 Oct 2020 at 15:04, Marc Zyngier wrote:
>
...
> >>
> >> One of the major difference is that we end up, in some cases
> >> (such as when
On 2020-10-27 04:46, Biwen Li wrote:
From: Hou Zhiqiang
Add an new IRQ chip declaration for LS1043A and LS1088A
- compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A.
SCFG_INTPCR[31:0]
of these SoCs is stored/read as SCFG_INTPCR[0:31] defaultly(bit
reverse)
- compatible
On 2020-10-27 08:51, ba...@kernel.org wrote:
From: Felipe Balbi
Fix the following warning:
WARNING: modpost: vmlinux.o(.text.unlikely+0x17b2c): Section mismatch
in reference from the function bcm2836_arm_irqchip_smp_init() to the
function .init.text:set_smp_ipi_range()
The function
that will just WARN_ON_ONCE() if ever used.
Signed-off-by: Zhen Lei
[maz: commit message]
Signed-off-by: Marc Zyngier
Link:
https://lore.kernel.org/r/20200924071754.4509-2-thunder.leiz...@huawei.com
Signed-off-by: Sasha Levin
---
include/linux/irq.h | 6 ++
1 file changed, 6 insertions(+)
diff
On 2020-10-26 17:28, Kevin Hilman wrote:
Marc Zyngier writes:
On 2020-10-26 16:18, Kevin Hilman wrote:
Marc Zyngier writes:
On Tue, 20 Oct 2020 08:25:30 +0100,
Neil Armstrong wrote:
In order to reduce the kernel Image size on multi-platform
distributions,
make it possible to build
On 2020-10-26 16:18, Kevin Hilman wrote:
Marc Zyngier writes:
On Tue, 20 Oct 2020 08:25:30 +0100,
Neil Armstrong wrote:
In order to reduce the kernel Image size on multi-platform
distributions,
make it possible to build the Amlogic GPIO IRQ controller as a module
by switching
On 2020-10-26 15:06, Leo Li wrote:
-Original Message-
From: Marc Zyngier
Sent: Monday, October 26, 2020 4:23 AM
To: Rasmus Villemoes
Cc: Biwen Li (OSS) ; shawn...@kernel.org;
robh...@kernel.org; mark.rutl...@arm.com; Leo Li ;
Z.q. Hou ; t...@linutronix.de;
ja...@lakedaemon.net; devicet
On 2020-10-26 09:06, Rasmus Villemoes wrote:
On 26/10/2020 09.44, Marc Zyngier wrote:
On 2020-10-26 08:01, Biwen Li wrote:
From: Hou Zhiqiang
Add an new IRQ chip declaration for LS1043A and LS1088A
- compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
- compatible "fsl
On 2020-10-25 23:04, Gavin Shan wrote:
Hi Marc,
On 10/25/20 9:48 PM, Marc Zyngier wrote:
On Sun, 25 Oct 2020 01:27:39 +0100,
Gavin Shan wrote:
The huge page could be mapped through multiple contiguous PMDs or
PTEs.
The corresponding huge page sizes aren't supported by the page table
On 2020-10-25 22:23, Gavin Shan wrote:
Hi Marc,
On 10/25/20 8:52 PM, Marc Zyngier wrote:
On Sun, 25 Oct 2020 01:27:37 +0100,
Gavin Shan wrote:
The 52-bits physical address is disabled until
CONFIG_ARM64_PA_BITS_52
is chosen. This uses option for that check, to avoid the
unconditional
On 2020-10-26 08:01, Biwen Li wrote:
From: Hou Zhiqiang
Add an new IRQ chip declaration for LS1043A and LS1088A
- compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
- compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
Three things:
- This commit message doesn't describe the
On Tue, 20 Oct 2020 16:15:32 +0800, Greentime Hu wrote:
> It will always enable the interrupt after calling plic_set_affinity()
> however it should set to it previous setting. Staying disabled or enabled.
>
> This patch can also fix this pwm hang issue in Unleashed board.
>
> [ 919.015783] rcu:
On Fri, 16 Oct 2020 16:40:16 +0200, Fabrice Gasnier wrote:
> STM32 LP timer that's available on STM32MP15x can wakeup the platform
> using EXTI interrupts.
>
> This series add:
> - LP timer EXTI - GIC interrupt events to EXTI driver and device-tree
> - LP timer wakeup-source to device-tree
>
>
On Tue, 20 Oct 2020 08:25:30 +0100,
Neil Armstrong wrote:
>
> In order to reduce the kernel Image size on multi-platform distributions,
> make it possible to build the Amlogic GPIO IRQ controller as a module
> by switching it to a platform driver.
>
> The second patch removes MESON_IRQ_GPIO
On Sun, 25 Oct 2020 01:09:21 +0100,
kernel test robot wrote:
>
> [1 ]
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> master
> head: d76913908102044f14381df865bb74df17a538cb
> commit: 0809ae724904c3c5dbdddf4169d48aac9c6fcdc8 irqchip/bcm2836: Configure
>
On Sun, 25 Oct 2020 01:27:39 +0100,
Gavin Shan wrote:
>
> The huge page could be mapped through multiple contiguous PMDs or PTEs.
> The corresponding huge page sizes aren't supported by the page table
> walker currently.
>
> This fails the unsupported huge page sizes to the near one. Otherwise,
On Sun, 25 Oct 2020 01:27:38 +0100,
Gavin Shan wrote:
>
> PUD huge page isn't available when CONFIG_ARM64_4K_PAGES is disabled.
> In this case, we needn't try to map the memory through PUD huge pages
> to save some CPU cycles in the hot path.
>
> This also corrects the code style issue, which
On Sun, 25 Oct 2020 01:27:37 +0100,
Gavin Shan wrote:
>
> The 52-bits physical address is disabled until CONFIG_ARM64_PA_BITS_52
> is chosen. This uses option for that check, to avoid the unconditional
> check on PAGE_SHIFT in the hot path and thus save some CPU cycles.
PAGE_SHIFT is known at
t_name = irqchip_fwnode_get_name,
> +};
> EXPORT_SYMBOL_GPL(irqchip_fwnode_ops);
>
> /**
Acked-by: Marc Zyngier
--
Without deviation from the norm, progress is not possible.
Hi Santosh,
Thanks for this.
On 2020-10-21 17:16, Santosh Shukla wrote:
The Commit:6d674e28 introduces a notion to detect and handle the
device mapping. The commit checks for the VM_PFNMAP flag is set
in vma->flags and if set then marks force_pte to true such that
if force_pte is true then
On 2020-10-20 10:13, Sumit Garg wrote:
On Mon, 19 Oct 2020 at 17:50, Marc Zyngier wrote:
On 2020-10-14 12:12, Sumit Garg wrote:
> Enable NMI backtrace support on arm64 using IPI turned as an NMI
> leveraging pseudo NMIs support. It is now possible for users to get a
> backtrace of a
On 2020-10-20 12:22, Sumit Garg wrote:
On Tue, 20 Oct 2020 at 15:38, Marc Zyngier wrote:
On 2020-10-20 07:43, Sumit Garg wrote:
> On Mon, 19 Oct 2020 at 17:07, Marc Zyngier wrote:
[...]
>> > +{
>> > + if (!ipi_desc)
>> > + return
UPPORTED return value means we are vulnerable, but
really
it means we have no idea and should assume we can't do anything about
mitigation. Put another way, it better be unaffected because it can't
be
mitigated in the firmware (in this case kvm) as the call isn't
implemented!
Cc: Andre Przywara
Cc:
On 2020-10-20 13:25, Daniel Thompson wrote:
On Tue, Oct 20, 2020 at 04:52:43PM +0530, Sumit Garg wrote:
[...]
So in general, IPI as a normal IRQ is still useful for debugging but
it can't debug a core which is stuck in deadlock with interrupts
disabled.
And since we choose override default
On 2020-10-20 07:43, Sumit Garg wrote:
On Mon, 19 Oct 2020 at 17:07, Marc Zyngier wrote:
[...]
> +{
> + if (!ipi_desc)
> + return;
> +
> + if (is_nmi) {
> + if (!prepare_percpu_nmi(ipi_id))
> + enable_percpu_nmi(
Hi Vincent,
On 2020-10-19 13:42, Vincent Guittot wrote:
Hi Marc,
On Tue, 1 Sep 2020 at 16:44, Marc Zyngier wrote:
In order to deal with IPIs as normal interrupts, let's add
a new way to register them with the architecture code.
set_smp_ipi_range() takes a range of interrupts, and allows
On 2020-10-19 13:24, Mark Rutland wrote:
On Tue, Oct 06, 2020 at 05:13:31PM +0100, Alexandru Elisei wrote:
Hi Marc,
Thank you for having a look at the patch!
On 10/6/20 4:32 PM, Marc Zyngier wrote:
> Hi Alex,
>
> On Tue, 06 Oct 2020 16:05:20 +0100,
> Alexandru Elisei wrote:
>
On 2020-10-14 12:12, Sumit Garg wrote:
Enable NMI backtrace support on arm64 using IPI turned as an NMI
leveraging pseudo NMIs support. It is now possible for users to get a
backtrace of a CPU stuck in hard-lockup using magic SYSRQ.
Signed-off-by: Sumit Garg
---
arch/arm64/include/asm/irq.h |
On 2020-10-14 12:12, Sumit Garg wrote:
arm64 platforms with GICv3 or later supports pseudo NMIs which can be
leveraged to round up CPUs which are stuck in hard lockup state with
interrupts disabled that wouldn't be possible with a normal IPI.
So instead switch to round up CPUs using IPI turned
On 2020-10-14 12:12, Sumit Garg wrote:
Add support to handle SGIs as regular NMIs. As SGIs or IPIs defaults to
a
There is nothing "regular" about NMIs. Drop "or IPIs".
s/defaults/default/
special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI
handler update in case of SGIs.
On 2020-10-14 12:12, Sumit Garg wrote:
Allocate an unused IPI that can be turned as NMI using ipi_nmi
framework.
This doesn't do any allocation, as far as I can see. It relies on
the initial grant from the interrupt controller to be larger than
what the kernel currently uses.
Also, invoke
On 2020-10-14 12:12, Sumit Garg wrote:
Introduce framework to turn an IPI as NMI using pseudo NMIs. In case a
particular platform doesn't support pseudo NMIs, then request IPI as a
regular IRQ.
The main motivation for this feature is to have an IPI that can be
leveraged to invoke NMI functions
On 2020-10-14 12:12, Sumit Garg wrote:
Introduce framework to turn an IPI as NMI using pseudo NMIs. In case a
particular platform doesn't support pseudo NMIs, then request IPI as a
regular IRQ.
The main motivation for this feature is to have an IPI that can be
leveraged to invoke NMI functions
On 2020-10-16 00:24, Thomas Gleixner wrote:
On Thu, Oct 15 2020 at 20:41, Marc Zyngier wrote:
On 2020-10-15 18:18, Pavel Machek wrote:
diff --git a/kernel/irq/Kconfig b/kernel/irq/Kconfig
index 10a5aff4eecc..db923e0da162 100644
--- a/kernel/irq/Kconfig
+++ b/kernel/irq/Kconfig
@@ -81,6 +81,7
On Wed, 14 Oct 2020 15:17:03 +0200, Geert Uytterhoeven wrote:
> The MStar interrupt controller is only found on MStar, SigmaStar, and
> Mediatek SoCs. Hence add dependencies on ARCH_MEDIATEK and
> ARCH_MSTARV7, to prevent asking the user about the MStar interrupt
> controller driver when
On 2020-10-12 14:57, Greentime Hu wrote:
In commit 2ca0b460bbcb ("genirq/affinity: Make affinity setting if
activated opt-in"),
it added irqd_affinity_on_activate() checking in the function
irq_set_affinity_deactivated() so it will return false here.
In that case, it will call
On 2020-10-15 18:18, Pavel Machek wrote:
Hi!
> > I'm getting build problems in 5.10-rc0 in config for n900. ARM board.
> >
> > CONFIG_SMP=y
> > CONFIG_SMP_ON_UP=y
On its own, this doesn't break anything with multi_v7_defconfig.
I sent config off-list. Let me know if it does not arrive or if
On 2020-10-15 15:23, Thomas Gleixner wrote:
On Thu, Oct 15 2020 at 12:12, Pavel Machek wrote:
Cc+ Marc
Thanks Thomas.
I'm getting build problems in 5.10-rc0 in config for n900. ARM board.
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
On its own, this doesn't break anything with multi_v7_defconfig.
On 2020-10-13 13:56, limingwang (A) wrote:
Hi Li,
On 2020-10-12 02:08, l00484210 wrote:
From: MingWang Li
When testing the ARMv8.2-TTS2UXN feature, setting bits of XN is
unavailable.
Because the control bit CTR_EL0.DIC is set by default on system.
But when CTR_EL0.DIC is set, software does
Add the description of CPU PMUs for both the Denver and A57 clusters,
which enables the perf subsystem.
Signed-off-by: Marc Zyngier
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 +++-
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts
[8.752230] Code: a9bd7bfd 910003fd a90153f3 aa0003f3 (3940f000)
[8.752232] ---[ end trace 90f6c89d62d85ff5 ]---
Reset the pointer on probe failure fixes the issue.
Fixes: 53d2a715c2403 ("phy: Add Tegra XUSB pad controller support")
Signed-off-by: Marc Zyngier
---
drivers/phy/tegra/xusb.
/0x180
[9.680324] ---[ end trace 90f6c89d62d85ff6 ]---
Instead, let's register a callback that will disable the regulators
on teardown. This allows for the removal of the .remove callbacks,
which are not needed anymore.
Signed-off-by: Marc Zyngier
---
drivers/gpu/drm/tegra/sor.c | 59
On 2020-10-09 09:58, Peter Ujfalusi wrote:
Marc,
[...]
The design of irqchip/irq-ti-sci-inta.c, soc/ti/ti_sci_inta_msi.c and
irqchip/irq-ti-sci-intr.c created to handle the interrupt needs present
in K3 devices with NAVSS.
DMSS of newer K3 devices extends and simplifies the NAVSS components
Hi Li,
On 2020-10-12 02:08, l00484210 wrote:
From: MingWang Li
When testing the ARMv8.2-TTS2UXN feature, setting bits of XN is
unavailable.
Because the control bit CTR_EL0.DIC is set by default on system.
But when CTR_EL0.DIC is set, software does not need to flush icache
actively,
The following commit has been merged into the irq/core branch of tip:
Commit-ID: ac15a54e03d13686d2fc016a88311801b0734046
Gitweb:
https://git.kernel.org/tip/ac15a54e03d13686d2fc016a88311801b0734046
Author:Marc Zyngier
AuthorDate:Fri, 18 Sep 2020 17:19:46 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 986ec63d4482292570b579ac98b151acf8bdd1de
Gitweb:
https://git.kernel.org/tip/986ec63d4482292570b579ac98b151acf8bdd1de
Author:Marc Zyngier
AuthorDate:Mon, 05 Oct 2020 10:27:27 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 55567976629e58fde28fb70612ca73228271eef2
Gitweb:
https://git.kernel.org/tip/55567976629e58fde28fb70612ca73228271eef2
Author:Marc Zyngier
AuthorDate:Tue, 06 Oct 2020 10:10:20 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 0809ae724904c3c5dbdddf4169d48aac9c6fcdc8
Gitweb:
https://git.kernel.org/tip/0809ae724904c3c5dbdddf4169d48aac9c6fcdc8
Author:Marc Zyngier
AuthorDate:Tue, 05 May 2020 12:59:04 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 64b499d8df40dadb1818ad9f74c4546951b37a8f
Gitweb:
https://git.kernel.org/tip/64b499d8df40dadb1818ad9f74c4546951b37a8f
Author:Marc Zyngier
AuthorDate:Sat, 25 Apr 2020 15:24:01 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 8594c3b85171b6f68e34e07b533ec2f1bf7fb065
Gitweb:
https://git.kernel.org/tip/8594c3b85171b6f68e34e07b533ec2f1bf7fb065
Author:Marc Zyngier
AuthorDate:Tue, 15 Sep 2020 14:03:51 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 5cebfd2d47c214f69d918e3d34ad183c061eddb2
Gitweb:
https://git.kernel.org/tip/5cebfd2d47c214f69d918e3d34ad183c061eddb2
Author:Marc Zyngier
AuthorDate:Sat, 09 May 2020 14:00:23 +01:00
Committer
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 8aa837cb7a032884c787b15de81f7d9de8af0869
Gitweb:
https://git.kernel.org/tip/8aa837cb7a032884c787b15de81f7d9de8af0869
Author:Marc Zyngier
AuthorDate:Mon, 22 Jun 2020 22:15:54 +01:00
Committer
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