Thanks Anton for the reupload.
I tested this series with a 6.1 kernel guest on a proprietary hypervisor. The
controls exposed by the host (BOOLEAN/INTEGER ones, as that was all I could
get) worked as expected when adjusted via ALSA APIs.
Reviewed-by: Marcin Radomski
Tested-By: Marcin Radomski
ure still under development, or are there some
concerns that need to be addressed?
I'd be more than happy to help with testing.
Thanks for any insights or updates you can offer.
Regards,
Marcin Radomski
[0]
https://patchwork.kernel.org/project/alsa-devel/patch/20230209115916.9
> >
> > > Thanks.
> >
> > Due to missed parser support for IP header length > 20, RX IPv4 checksum
> > offload fail.
> >
> > Regards.
>
> Currently driver set skb->ip_summed = CHECKSUM_NONE and checksum done by
> software.
> So this just improve performance for packets with IP header length > 20.
> IMO we can keep it in net-next.
>
> Stefan.
Please update the commit message in v2 with the explanation.
Also - is there an easy way to test it? L3 forwarding with forced header length?
Thanks,
Marcin
Hi Jon,
Thank you for your answer.
czw., 25 mar 2021 o 22:12 Jon Masters napisał(a):
>
> Hi Marcin,
>
> Many thanks for your thoughtful, heartfelt response, and I don't
> disagree with your sentiments.
>
> The truth is that we have a messy situation. As a collective
story with a real
candidate for such device (SolidRun Honeycomb) - similar DWC
controller and the same problems. We want people to use arm64
workstations outside of the passionate-developer-bubble, we want to
standardize (great SystemReady program!), but due to arbitrary
decisions we don't push it forward, least to say. Don't get me wrong,
I would love all HW to use proper IP and "just work" without hacks,
but this takes time and apparently is not that easy, so maybe an
option to mitigate the limitations with SW (to some extent and even
temporary) should be considered. This patch was a chance for that IMO,
without adding a burden of maintaining quirks.
Also I am not in a position to reach out to vendors and convince to
anything, but I read about this need 4 years ago and now I see that
there is a *plan* to do it. DWC is as broken as it was, with a lot new
platforms in the tree, but fully functional in ECAM mode only with
DT...
But I left the best to the end - below are 2 quirks merged despite the embargo:
Ampere:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/acpi/pci_mcfg.c?h=v5.12-rc4&id=877c1a5f79c6984bbe3f2924234c08e2f4f1acd5
Amazon (Annapurna):
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/acpi/pci_mcfg.c?h=v5.12-rc4&id=4166bfe53093b687a0b1b22e5d943e143b8089b2
I must admit the second one rose my blood pressure and triggered this
email - it's a quirk for DWC, 1:1 to what was NACKed for Marvell
almost 2 years earlier.
So what we have after 4 years:
* Direct convincing of IP vendors still being a plan.
* Reverting the original approach towards MCFG quirks.
* Double-standards in action as displayed by 2 cases above.
I'm sorry for my bitter tone, but I think this time could and should
have been spent better - I doubt it managed to push us in any
significant way towards wide fully-standard compliant PCIE IP
adoption.
Best regards,
Marcin
the problem
with backward compatibility by restoring a previous compatible
string as secondary one.
Signed-off-by: Marcin Wojtas
---
arch/arm64/boot/dts/marvell/armada-ap807.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
b
_port_config(port);
>
> - if (mvpp22_rss_is_supported())
> + if (mvpp22_rss_is_supported(port))
> mvpp22_port_rss_init(port);
>
> /* Provide an initial Rx packet size */
> @@ -6861,7 +6864,7 @@ static int mvpp2_port_probe(struct platform_device
> *pdev,
> dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
> NETIF_F_HW_VLAN_CTAG_FILTER;
>
> - if (mvpp22_rss_is_supported()) {
> + if (mvpp22_rss_is_supported(port)) {
> dev->hw_features |= NETIF_F_RXHASH;
> dev->features |= NETIF_F_NTUPLE;
> }
> --
> 1.9.1
>
Reviewed-by: Marcin Wojtas
Thanks!
add PPv23 version definition.
> > > PPv23 is new packet processor in CP115.
> > > Everything that supported by PPv22, also supported by PPv23.
> > > No functional changes in this stage.
> > >
> > > Signed-off-by: Stefan Chulski
> > > Acked-b
just making it all simpler for the user to
> use.
I think of 2 alternatives:
* `ethtool --set-priv-flags` - in such case there is a question if
switching this particular feature in runtime is a good idea.
* New DT/ACPI property - it is a hardware feature after all, so maybe
let the user decide whether to enable it on the platform description
level.
What do you think?
Best regards,
Marcin
śr., 10 lut 2021 o 14:16 napisał(a):
>
> From: Stefan Chulski
>
> This patch enables eth0 10G interface on CN9130-DB paltforms and
> eth0 10G and eth3 10G interfaces on CN9131-DB.
Thank you.
Reviewed-by: Marcin Wojtas
>
> Signed-off-by: Stefan Chulski
> Signed-off-b
ot/dts/marvell/cn9130-db.dtsi
> @@ -125,7 +125,7 @@
>
> /* SLM-1521-V2, CON9 */
> &cp0_eth0 {
> - status = "disabled";
> + status = "okay";
> phy-mode = "10gbase-kr";
> /* Generic PHY, providing serdes lanes */
>
flow control
> net: mvpp2: set 802.3x GoP Flow Control mode
> net: mvpp2: add TX FC firmware check
>
> Documentation/devicetree/bindings/net/marvell-pp2.txt | 6 +-
> arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +-
> drivers/net/ethernet/marvell/mvpp2/mvpp2.h| 124 -
> drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 526
> ++--
> 4 files changed, 609 insertions(+), 49 deletions(-)
>
For the series:
Acked-by: Marcin Wojtas
Thanks,
Marcin
er, PPv2.2 and PPv2.3 needs 16
> * bytes per buffer pointer
> */
> if (priv->hw_version == MVPP21)
> @@ -1172,7 +1172,7 @@ static void mvpp2_interrupts_unmask(void *arg)
> u32 val;
> int i;
>
> - if (port->priv->hw_v
Hi,
pon., 8 lut 2021 o 09:33 napisał(a):
>
> From: Stefan Chulski
>
> This patch adds CM3 memory map and CM3 read/write callbacks.
The read/write callbacks are not added in this patch, please correct
the commit message.
Best regards,
Marcin
>
> Signed-off-by: Stefan Chul
I was wondering why I can't set the resolution to 2560x1080,
while in windows 7 I can without a problem. I looked at the radeon driver
code and found it doesn't support this resolution. So I made some changes. I
added the hdmi_mhz parameter. In cmdline I set radeon.hdmi_mhz=190
Only tested on
---
drivers/gpu/drm/radeon/radeon_benchmark.c | 5 ++--
drivers/gpu/drm/radeon/radeon_connectors.c | 30 ++
drivers/gpu/drm/radeon/radeon_drv.c| 5
drivers/gpu/drm/radeon/radeon_encoders.c | 6 +++--
4 files changed, 32 insertions(+), 14 deletions(-)
diff --
---
drivers/gpu/drm/radeon/radeon_benchmark.c | 5 ++--
drivers/gpu/drm/radeon/radeon_connectors.c | 30 ++
drivers/gpu/drm/radeon/radeon_drv.c| 5
drivers/gpu/drm/radeon/radeon_encoders.c | 6 +++--
4 files changed, 32 insertions(+), 14 deletions(-)
diff --
is safe and
will boost IO performance.
Thanks,
Marcin
> Signed-off-by: Stefan Chulski
> Signed-off-by: Konstantin Porotchkin
> ---
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
ll versions of AP806
there - I believe this place requires revisiting, to start relying
explicitly on the `marvell,xenon-phy-slow-mode` setting, rather than
the compatible string. I can handle this one.
4. Please move armada-8040-db.dts changes to a separate patch, please.
Thanks,
Marcin
>
flow control for RXQs condition */
> +static void mvpp2_rxq_enable_fc(struct mvpp2_port *port)
> +{
> + int val, cm3_state, host_id, q;
> + int fq = port->first_rxq;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&port->priv->mss_spin
thods */
>
> void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
> @@ -424,6 +429,21 @@ static int mvpp2_bm_pool_create(struct device *dev,
> struct mvpp2 *priv,
>
> val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
> val |=
Hi,
wt., 2 lut 2021 o 09:18 napisał(a):
>
> From: Stefan Chulski
>
> New FIFO flow control feature were added in PPv23.
s/were/was/
Thanks,
Marcin
> PPv2 FIFO polled by HW and trigger pause frame if FIFO
> fill level is below threshold.
> FIFO HW flow control enabled
n9131-db.dts
index 3c975f98b2a3..5c081d68941d 100644
--- a/arch/arm64/boot/dts/marvell/cn9131-db.dts
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dts
@@ -85,7 +85,7 @@ &cp1_ethernet {
/* CON50 */
&cp1_eth0 {
- status = "disabled";
+ status = "okay";
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
phys = <&cp1_comphy4 0>;
Best regards,
Marcin
, PPv2.2 and PPv2.3 needs 16
s/needs 16/need 16/
> * bytes per buffer pointer
> */
> if (priv->hw_version == MVPP21)
> @@ -1173,7 +1173,7 @@ static void mvpp2_interrupts_unmask(void *arg)
> u32 val;
> int i;
>
> - if (port->priv->hw_version != MVPP22)
> + if (port->priv->hw_version == MVPP21)
> return;
This change should go to "net: mvpp2: always compare hw-version vs
MVPP21" patch. Please also swap order of those 2 commits - the
preparation patch should go before MVPP23 addition.
Thanks,
Marcin
AUSE_REG(port->id), 0);
> }
>
> /* Unmask the current thread's Rx/Tx interrupts.
> @@ -1151,20 +1156,25 @@ static void mvpp2_interrupts_mask(void *arg)
> static void mvpp2_interrupts_unmask(void *arg)
> {
> struct mvpp2_port *port = arg;
> - u32 val;
"if equal/notEqual MVPP21" for all cases instead of "if MVPP22".
>
> This patch does not change any functionality.
> It is not intended to introduce PP2v3.
This is a preparation patch and it should be commited before "net:
mvpp2: add PPv23 version definition"
4/boot/dts/marvell/armada-cp11x.dtsi
The commit message mentions CP115, but the patch updates both CP110
and CP115 - please update one of those (either message or the patch),
so that it is consistent.
Thanks,
Marcin
> @@ -69,6 +69,8 @@
> statu
iate firmware.
This should happen after the weekend, as I don't have an immediate
access to our lab in order to replug the cables. I'll update here
about the results.
Best regards,
Marcin
t(mask, Autoneg);
> phylink_set_port_modes(mask);
> - phylink_set(mask, Pause);
> - phylink_set(mask, Asym_Pause);
>
> switch (state->interface) {
> case PHY_INTERFACE_MODE_10GBASER:
> --
> 1.9.1
>
Acked-by: Marcin Wojtas
Thanks!
TXDONE_COAL_USEC;
>
> port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
> --
I confirm the patch fixes issue - tested on CN913x-DB and RGMII port.
Other boards there I see no regression.
Acked-by: Marcin Wojtas
Thanks,
Marcin
GMII;
> else if (port->gop_id == 3)
> - val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
> + val &= ~GENCONF_CTRL0_PORT3_RGMII_MII;
> regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
> }
> }
> --
I tested the patch and LGTM.
Acked-by: Marcin Wojtas
Thanks,
Marcin
djacent to the Signed-off-by
> > tag.
>
> netdev patches should not be Cc: sta...@vger.kernel.org. David and
> Jakub handle stable patches directly.
>
Thanks for clarification.
Marcin
nd it may be
good to add 'Cc: sta...@vger.kernel.org' adjacent to the Signed-off-by
tag.
Thanks,
Marcin
> drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_m
wt., 15 gru 2020 o 09:04 Adrian Hunter napisał(a):
>
> On 11/12/20 4:16 pm, Marcin Wojtas wrote:
> > From: Alex Leibovich
> >
> > Automatic Clock Gating is a feature used for the power
> > consumption optimisation. It turned out that
> > during early init pha
Since its creation Marvell NIC driver for Armada 375/7k8k and
CN913x SoC families mvpp2 has been lacking an entry in MAINTAINERS,
which sometimes lead to unhandled bugs that persisted
across several kernel releases.
Signed-off-by: Marcin Wojtas
---
MAINTAINERS | 8
1 file changed, 8
pt., 11 gru 2020 o 16:42 Russell King - ARM Linux admin
napisał(a):
>
> On Fri, Dec 11, 2020 at 03:41:47PM +0100, Marcin Wojtas wrote:
> > Since its creation Marvell NIC driver for Armada 375/7k8k and
> > CN913x SoC families mvpp2 has been lacking an entry in MAINTAINERS,
> &
Since its creation Marvell NIC driver for Armada 375/7k8k and
CN913x SoC families mvpp2 has been lacking an entry in MAINTAINERS,
which sometimes lead to unhandled bugs that persisted
across several kernel releases.
Signed-off-by: Marcin Wojtas
---
MAINTAINERS | 7 +++
1 file changed, 7
lator output did not became stable"
Fix the problem by disabling the ACG at very beginning
of the sdhci_init and let that be enabled later.
Fixes: 3a3748dba881 ("mmc: sdhci-xenon: Add Marvell Xenon SDHC core
functionality")
Signed-off-by: Alex Leibovich
Signed-off-by: Ma
pt., 11 gru 2020 o 14:47 Ulf Hansson napisał(a):
>
> On Fri, 4 Dec 2020 at 18:17, Marcin Wojtas wrote:
> >
> > Hi,
> >
> > The fourth version of the sdhci-xenon ACPI support
> > addresses a comment regarding clk handling in xenon_runtime_resume.
> >
>
As a preparation for supporting ACPI, modify the driver
to use the clk framework only when booting with DT -
otherwise rely on the configuration done by firmware.
For that purpose introduce also a custom SDHCI get_max_clock
callback.
Signed-off-by: Marcin Wojtas
---
drivers/mmc/host/sdhci
pt., 4 gru 2020 o 14:51 Ulf Hansson napisał(a):
>
> On Wed, 2 Dec 2020 at 19:51, Marcin Wojtas wrote:
> >
> > As a preparation for supporting ACPI, modify the driver
> > to use the clk framework only when booting with DT -
> > otherwise rely on the configuration
Previous patches dropped the strict dependency on the OF_*
in the sdhci-xenon driver. As a result the ACPI support
can be introduced (except for the XENON_A3700 variant)
by adding the necessary ID's in the acpi_match_table.
Signed-off-by: Marcin Wojtas
---
drivers/mmc/host/sdhci-xenon.c
In order to support both ACPI and DT, modify the driver
to use device_* routines for obtaining the properties
values.
Signed-off-by: Marcin Wojtas
---
drivers/mmc/host/sdhci-xenon.h | 4 +--
drivers/mmc/host/sdhci-xenon-phy.c | 36 +++-
drivers/mmc/host/sdhci-xenon.c
As a part of the ACPI support preparation resign from checking
compatible strings in the driver. Instead of that use a new
enum and assign the values to match data accordingly.
Signed-off-by: Marcin Wojtas
---
drivers/mmc/host/sdhci-xenon.h | 8
drivers/mmc/host/sdhci-xenon-phy.c
ID's per controller
variant
Marcin Wojtas (4):
mmc: sdhci-xenon: use match data for controllers variants
mmc: sdhci-xenon: switch to device_* API
mmc: sdhci-xenon: use clk only with DT
mmc: sdhci-xenon: introduce ACPI support
drivers/mmc/host/sdhci-xenon.h | 12 ++-
drivers/mmc/hos
Previous patches dropped the strict dependency on the OF_*
in the sdhci-xenon driver. As a result the ACPI support
can be introduced (except for the XENON_A3700 variant)
by adding the necessary ID's in the acpi_match_table.
Signed-off-by: Marcin Wojtas
Acked-by: Adrian Hunter
---
driver
In order to support both ACPI and DT, modify the driver
to use device_* routines for obtaining the properties
values.
Signed-off-by: Marcin Wojtas
Acked-by: Adrian Hunter
---
drivers/mmc/host/sdhci-xenon.h | 4 +--
drivers/mmc/host/sdhci-xenon-phy.c | 36 +++-
drivers/mmc
As a preparation for supporting ACPI, modify the driver
to use the clk framework only when booting with DT -
otherwise rely on the configuration done by firmware.
For that purpose introduce also a custom SDHCI get_max_clock
callback.
Signed-off-by: Marcin Wojtas
Acked-by: Adrian Hunter
all clk_disable_unprepare unconditionally.
* Add Adrian's Acked-by to all patches.
v1->v2
* Split single commit to 4
* Use device_match_data and dedicated ACPI ID's per controller
variant
Marcin Wojtas (4):
mmc: sdhci-xenon: use match data for controllers variants
mmc: sdhci-xenon: switch
As a part of the ACPI support preparation resign from checking
compatible strings in the driver. Instead of that use a new
enum and assign the values to match data accordingly.
Signed-off-by: Marcin Wojtas
Acked-by: Adrian Hunter
---
drivers/mmc/host/sdhci-xenon.h | 8
drivers
śr., 2 gru 2020 o 09:30 Adrian Hunter napisał(a):
>
> On 20/11/20 5:26 am, Marcin Wojtas wrote:
> > Hi,
> >
> > The second version of the sdhci-xenon ACPI support
> > is now split into 4 patches instead of a single one.
> > There are minor functional differenc
Hi Ulf
wt., 24 lis 2020 o 12:31 Ulf Hansson napisał(a):
>
> On Fri, 20 Nov 2020 at 04:27, Marcin Wojtas wrote:
> >
> > As a preparation for supporting ACPI, modify the driver
> > to use the clk framework only when booting with DT -
> > otherwise rely on the
In order to support both ACPI and DT, modify the driver
to use device_* routines for obtaining the properties
values.
Signed-off-by: Marcin Wojtas
---
drivers/mmc/host/sdhci-xenon.h | 4 +--
drivers/mmc/host/sdhci-xenon-phy.c | 36 +++-
drivers/mmc/host/sdhci-xenon.c
Previous patches dropped the strict dependency on the OF_*
in the sdhci-xenon driver. As a result the ACPI support
can be introduced (except for the XENON_A3700 variant)
by adding the necessary ID's in the acpi_match_table.
Signed-off-by: Marcin Wojtas
---
drivers/mmc/host/sdhci-xenon.c
As a part of the ACPI support preparation resign from checking
compatible strings in the driver. Instead of that use a new
enum and assign the values to match data accordingly.
Signed-off-by: Marcin Wojtas
---
drivers/mmc/host/sdhci-xenon.h | 8
drivers/mmc/host/sdhci-xenon-phy.c
As a preparation for supporting ACPI, modify the driver
to use the clk framework only when booting with DT -
otherwise rely on the configuration done by firmware.
For that purpose introduce also a custom SDHCI get_max_clock
callback.
Signed-off-by: Marcin Wojtas
---
drivers/mmc/host/sdhci
://drive.google.com/file/d/1Y8BhyaCrksQgT_GPfpqqiYHpQ41kP8Kp
Changelog:
v1->v2
* Split single commit to 4
* Use device_match_data and dedicated ACPI ID's per controller
variant
Marcin Wojtas (4):
mmc: sdhci-xenon: use match data for controllers variants
mmc: sdhci-xenon: switch to
Hi Adrian,
niedz., 15 lis 2020 o 21:43 Adrian Hunter napisał(a):
>
> On 14/11/20 11:08 am, Marcin Wojtas wrote:
> > This patch introduces an alternative way of obtaining resources - via
> > ACPI tables provided by firmware. In addition to the of_* -> device_
is firmware responsibility to enable them.
Signed-off-by: Marcin Wojtas
---
Hi,
In case anyone would like to test the patch, I share the EDK2
firmware for MacchiatoBin board, which has relevant ACPI
description https://drive.google.com/file/d/1ygdHGl30ww9LAqZAQlTsz2nnhN3Od9GG
Looking forward to y
o get pcie state addr: -16
> [8.814032] ath10k_pci :01:00.0: failed to setup init config: -16
> [8.820605] ath10k_pci :01:00.0: could not power on hif bus (-16)
> [8.827111] ath10k_pci :01:00.0: could not probe fw (-16)
>
> Thank you!
The PCIE was validate
Add the "seeed" vendor prefix for Seeed Technology Co., Ltd
Website: https://www.seeedstudio.com/
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/
Document device tree bindings of Seeed SoM and carrier board.
Signed-off-by: Marcin Sloniewski
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
b
card and on-board eMMC.
Signed-off-by: Marcin Sloniewski
---
Changes in v7:
- fix eth: added clock assignement for phy.
It gets clock from PLL4_P which must be configured
in u-boot/ATF as stmicroelectronics suggests.
Changes in v6:
- add reset pin for eth phy
- move pinctrl for sdmmc2 to stm3
card and on-board eMMC.
Signed-off-by: Marcin Sloniewski
---
Changes in v6:
- add reset pin for eth phy
- move pinctrl for sdmmc2 to stm32mp15-pinctrl.dtsi
Changes in v5:
- fix schema for board's dts
Changes in v4:
- add seeed,stm32mp157c-odyssey-som in compatible
for carrier board
-
Document device tree bindings of Seeed SoM and carrier board.
Signed-off-by: Marcin Sloniewski
---
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
b/Documentation/devicetree
Add the "seeed" vendor prefix for Seeed Technology Co., Ltd
Website: https://www.seeedstudio.com/
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/
Document device tree bindings of Seeed SoM and carrier board.
Signed-off-by: Marcin Sloniewski
---
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
b/Documentation/devicetree
Add the "seeed" vendor prefix for Seeed Technology Co., Ltd
Website: https://www.seeedstudio.com/
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/
card and on-board eMMC.
Signed-off-by: Marcin Sloniewski
---
Changes in v5:
- fix schema for board's dts
Changes in v4:
- add seeed,stm32mp157c-odyssey-som in compatible
for carrier board
- fix sdmmc2 interface by changing one of the pins
to use
- change eth phy address to 7
Changes in
Hi,
pt., 24 lip 2020 o 11:17 Ahmad Fatoum napisał(a):
>
> Hi,
>
> On 7/23/20 9:43 PM, Marcin Słoniewski wrote:
> > Hello Ahmad,
> >
> > First of all thank you very much for your feedback, it was very helpful!
> >
> > śr., 22 lip 2020 o 08:40 Ahmad Fatoum
Hello Ahmad,
First of all thank you very much for your feedback, it was very helpful!
śr., 22 lip 2020 o 08:40 Ahmad Fatoum napisał(a):
>
> On 7/21/20 8:53 PM, Marcin Sloniewski wrote:
> > Add support for Seeed Studio's stm32mp157c odyssey board.
> > Board consists of So
Add the "seeed" vendor prefix for Seeed Technology Co., Ltd
Website: https://www.seeedstudio.com/
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/
Document device tree bindings of Seeed SoM and carrier board.
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
b
card and on-board eMMC.
Signed-off-by: Marcin Sloniewski
---
Changes in v4:
- add seeed,stm32mp157c-odyssey-som in compatible
for carrier board
- fix sdmmc2 interface by changing one of the pins
to use
- change eth phy address to 7
Changes in v3:
- fix compilation on tip of stm32-next
d
= <&v3v3>;
> > + mmc-ddr-3_3v;
> > + status = "okay";
> > +};
>
> Based on the pins muxed, 8 data lines are configured, but the bus width
> is set to 4. What is the reason of not setting this property to 8?
Yes, it was workaround, because sdmmc2 interface was working only
with width set to 4. It turned out there was one wrong pin used in
sdmmc2_d47_pins_a.
It will be fixed in v4.
Regards,
Marcin Sloniewski
Document device tree bindings of Seeed SoM and carrier board.
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
b
card and on-board eMMC.
Signed-off-by: Marcin Sloniewski
---
Changes in v3:
- fix compilation on tip of stm32-next
due to change in names for pinctrl
- fix deprecated binding for led node
- fix redundant "okay" statuses
- add phy part number for eth in comment
Changes in v2:
- add new
Add the "seeed" vendor prefix for Seeed Technology Co., Ltd
Website: https://www.seeedstudio.com/
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/
Document device tree bindings of Seeed SoM and carrier board.
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
b
card and on-board eMMC.
Signed-off-by: Marcin Sloniewski
---
Changes in v2:
- add new odyssey dts to Makefile
arch/arm/boot/dts/Makefile| 3 +-
.../arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 276 ++
arch/arm/boot/dts/stm32mp157c-odyssey.dts | 72 +++
Add the "seeed" vendor prefix for Seeed Technology Co., Ltd
Website: https://www.seeedstudio.com/
Signed-off-by: Marcin Sloniewski
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/
mada-AP806 SoC erratum
> > #582743
> > https://git.kernel.org/will/c/f2d9848aeb9f
> > [3/3] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806
> > SMMU-500
> > https://git.kernel.org/will/c/e85e84d19b9d
>
> (note that I left patch 4 for arm-soc, as that's just updating .dts files)
>
Hi Gregory,
Can you please help with the review/merge of patch #4?
Best regards,
Marcin
Document device tree bindings of Seeed SoM and carrier board.
Signed-off-by: Marcin Sloniewski
---
Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml
b/Documentation/devicetree
card and on-board eMMC.
Signed-off-by: Marcin Sloniewski
---
.../arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 276 ++
arch/arm/boot/dts/stm32mp157c-odyssey.dts | 72 +
2 files changed, 348 insertions(+)
create mode 100644 arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
c
Add the "seeed" vendor prefix for Seeed Technology Co., Ltd
Website: https://www.seeedstudio.com/
Signed-off-by: Marcin Sloniewski
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindi
Hi Tomasz,
pt., 3 lip 2020 o 11:33 Tomasz Nowicki napisał(a):
>
> On 03.07.2020 11:16, Robin Murphy wrote:
> > On 2020-07-02 21:16, Tomasz Nowicki wrote:
> >> From: Marcin Wojtas
> >>
> >> Add IOMMU node for Marvell AP806 based SoCs together with platfor
Commit-ID: 5e83cfe947444c7f201f8c39ce0189922ec9f578
Gitweb: https://git.kernel.org/tip/5e83cfe947444c7f201f8c39ce0189922ec9f578
Author: Marcin Benka
AuthorDate: Thu, 28 Mar 2019 20:34:27 +0100
Committer: Ingo Molnar
CommitDate: Fri, 29 Mar 2019 07:35:00 +0100
efi/arm: Show SMBIOS bank
On 3/14/19 2:56 PM, Matias Bjørling wrote:
On 3/14/19 6:41 AM, Marcin Dziegielewski wrote:
Open channel devices are not able to handle traditional
IO requests addressed by LBA, so following current
approach to exposing special nvme devices as zero size
(e.g. with namespace formatted to use
Open channel devices are not able to handle traditional
IO requests addressed by LBA, so following current
approach to exposing special nvme devices as zero size
(e.g. with namespace formatted to use metadata) also
open channel devices should be exposed as zero size
to OS.
Signed-off-by: Marcin
Hi Russell,
czw., 28 lut 2019 o 10:36 Russell King - ARM Linux admin
napisał(a):
>
> On Wed, Feb 27, 2019 at 06:47:32PM +0100, Marcin Wojtas wrote:
> > Current version of the driver was configuring XLG MAC
> > in a way to wait 3 IDLE frames before allowing for the
> >
ylink support")
Signed-off-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 16066c2..f1378f9 10
On Tue, Feb 19, 2019 at 11:20:10AM +0100, Greg Kroah-Hartman wrote:
> On Wed, Feb 13, 2019 at 08:40:35PM +0100, Marcin Ciupak wrote:
> > This patch adds driver for Nordic Semiconductor nRF24L01+ radio
> > transceiver.
> >
> > Signed-off-by: Marcin Ciupak
> > -
This patch adds driver for Nordic Semiconductor nRF24L01+ radio
transceiver.
Signed-off-by: Marcin Ciupak
---
Changes in v2:
- add terminating newlines to all logging formats
Changes in v3:
- patch subject
- comments cleanup
- goto labels cleanup
- scnprintf bugfix
Hi Jisheng,
śr., 19 gru 2018 o 04:11 Jisheng Zhang napisał(a):
>
>
> On Mon, 17 Dec 2018 08:37:35 +0100 Thomas Petazzoni wrote:
>
> > Hello Marcin,
> >
> > On Mon, 17 Dec 2018 00:25:58 +0100, Marcin Wojtas wrote:
> >
> > > Thanks. Indeed, the patc
Hi David,
niedz., 16 gru 2018 o 21:41 David Miller napisał(a):
>
> From: Marcin Wojtas
> Date: Tue, 11 Dec 2018 13:56:49 +0100
>
> > Recent changes in the mvneta driver reworked allocation
> > and handling of the ingress buffers to use entire pages.
> > Apart from
Hi Jisheng,
śr., 12 gru 2018 o 10:25 Jisheng Zhang napisał(a):
>
> Hi Marcin,
>
> On Wed, 12 Dec 2018 09:22:57 +0100 Marcin Wojtas wrote:
>
> > Hi Jisheng,
> >
> > śr., 12 gru 2018 o 03:48 Jisheng Zhang
> > napisał(a):
> > >
> > >
Hi Jisheng,
śr., 12 gru 2018 o 03:48 Jisheng Zhang napisał(a):
>
> Hi,
>
> On Tue, 11 Dec 2018 13:56:49 +0100 Marcin Wojtas wrote:
>
> > Recent changes in the mvneta driver reworked allocation
> > and handling of the ingress buffers to use entire pages.
> > Apar
unused frag_size field of the mvneta_port
structure.
Fixes: 562e2f467e71 ("net: mvneta: Improve the buffer allocation
method for SWBM")
Signed-off-by: Marcin Wojtas
---
drivers/net/ethernet/marvell/mvneta.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/d
gt; Signed-off-by: Mao Han
>> Cc: Arnd Bergmann
>> ---
>
> Thanks for the reminder!
>
> Marcin had already sent me the same patch a while ago
> and I forgot to apply it. I applied your version now, which
> as a slightly better changelog, so it will be in linux-n
W dniu 05.11.2018 o 15:26, David Abdurachmanov pisze:
> Marcin Juszkiewicz reported issues while generating syscall table for riscv
> using 4.20-rc1. The patch refactors our unistd.h files to match some other
> architectures.
>
> - Add asm/unistd.h UAPI header, which has __ARC
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