s as it applies to all entries. 'contains' is the correct schema
> to use in the case of multiple entries.
>
> Cc: Herbert Xu
> Cc: "David S. Miller"
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc: Eric Anholt
> Cc: Nicolas Saenz Julienne
> Cc: Florian Fainelli
&g
On Tue, Feb 02, 2021 at 04:23:38AM -0800, Bernard Zhao wrote:
> remove unneeded variable: "ret".
>
> Signed-off-by: Bernard Zhao
Applied, thanks
maxime
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On Mon, Feb 01, 2021 at 01:08:03PM +0100, Hermann Lauer wrote:
> On Thu, Jan 28, 2021 at 03:59:37PM +0100, Maxime Ripard wrote:
> > On Thu, Jan 28, 2021 at 12:18:42PM +0100, hermann.la...@uni-heidelberg.de
> > wrote:
> > > BPi Pro needs TX and RX delay for Gbit to work
On Sun, Jan 31, 2021 at 01:33:32PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Sun, Jan 31, 2021 at 12:54 AM Corentin Labbe
> wrote:
> >
> > Hello
> >
> > When booting next-20210128, I got the following warning on by bpim3
> > 6.148421] [ cut here ]
> > [6.153145]
Hi,
On Sun, Jan 24, 2021 at 08:39:03PM +0100, Alexandre GRIVEAUX wrote:
> Add Inet 86V Rev 2 support, based upon Inet 86VS.
>
> The Inet 86V use SL1536 touchpanel controller, the Inet 86VS a GSL1680,
> which make them both incompatible.
>
> Missing things:
> - Accelerometer (MXC6225X)
> -
On Thu, Jan 28, 2021 at 12:18:42PM +0100, hermann.la...@uni-heidelberg.de wrote:
> BPi Pro needs TX and RX delay for Gbit to work reliable and avoid high
> packet loss rates. The realtek phy driver overrides the settings of the
> pull ups for the delays, so fix this for BananaPro.
>
> Fix the
On Wed, Jan 27, 2021 at 02:03:03PM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Fri 15 Jan 21, 18:58, Paul Kocialkowski wrote:
> > The DE2 display engine hardware takes physical addresses that do not
> > need PHYS_BASE subtracted. As a result, they should not be present
> > on the mbus driver
add a parameter
> to our syscon phandle. The driver will use this value as an index into
> the regmap, so that we can address more than the first register, if
> needed.
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Maxime
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ob Herring
Acked-by: Maxime Ripard
maxime
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evices together.
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Maxime
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is
> registration, to avoid the driver to bail out completely.
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Maxime
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to the CPU, so make the "interrupts" property optional.
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Maxime
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Hi!
On Mon, Jan 25, 2021 at 10:03:44PM +0100, Nicolas Saenz Julienne wrote:
> Hi,
>
> On Mon, 2021-01-11 at 15:22 +0100, Maxime Ripard wrote:
> > Hi,
> >
> > Here's a series introducing the CEC support for the BCM2711 found on the
> > RaspberryPi4.
> >
Hi Ville,
On Fri, Jan 22, 2021 at 02:15:07PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 21, 2021 at 05:35:33PM +0100, Maxime Ripard wrote:
> > Some drivers are storing the plane->state pointer in atomic_update and
> > atomic_disable in a variable simply called state, whil
ot;
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc: Jernej Skrabec
> Cc: Boris BREZILLON
> Cc: linux-...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Signed-off-by: Lee Jones
> ---
> drivers/clk/sunxi/
On Tue, Jan 26, 2021 at 04:03:29PM +0100, Linus Walleij wrote:
> On Tue, Jan 26, 2021 at 7:31 AM liu xiang wrote:
>
> > > Liu can you make a patch to Kconfig to just select REGULATOR?
> > > Possibly even the specific regulator driver this SoC is using
> > > if it is very specific for this
Hi,
On Mon, Jan 25, 2021 at 03:17:50PM +, Andre Przywara wrote:
> Hi,
>
> an update from the v3 last week, to add support for the Allwinner H616
> SoC. Still based on the (updated) sunxi/for-next branch.
> I am omitting the MMC and pinctrl patches now, as they have been taken
> by Ulf and
On Sat, Jan 23, 2021 at 12:26:26AM -0600, Samuel Holland wrote:
> On 1/22/21 4:47 AM, Maxime Ripard wrote:
> > On Thu, Jan 21, 2021 at 07:33:54PM -0600, Samuel Holland wrote:
> >> On 1/21/21 2:35 PM, Marc Zyngier wrote:
> >>> On Sun, 17 Jan 2021 23:50:
Hi Ville,
On Fri, Jan 22, 2021 at 02:07:22PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 21, 2021 at 05:35:31PM +0100, Maxime Ripard wrote:
> > Many drivers reference the plane->state pointer in order to get the
> > current plane state in their atomic_check hook, which would be
On Thu, Jan 21, 2021 at 07:33:54PM -0600, Samuel Holland wrote:
> On 1/21/21 2:35 PM, Marc Zyngier wrote:
> > On Sun, 17 Jan 2021 23:50:30 -0600, Samuel Holland wrote:
> >> Allwinner sun6i/sun8i/sun50i SoCs (A31 and newer) have two interrupt
> >> controllers: GIC and R_INTC. GIC does not support
ne->state
+ old_plane_state
...
}
@ include depends on adds_old_state || replaces_old_state @
@@
#include
@ no_include depends on !include && (adds_old_state || replaces_old_state) @
@@
+ #include
#include
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/imx/ipuv3-plane.c
.
Signed-off-by: Maxime Ripard
---
Changes from v1:
- New patch
---
Documentation/gpu/todo.rst | 46 --
1 file changed, 46 deletions(-)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 009d8e6c7e3c..609794108f5a 100644
e
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 4 +++-
drivers/gpu/drm/arm/hdlcd_crtc.c| 3 ++-
drivers/gpu/drm/arm/malidp_planes.c | 3 ++-
drivers/gpu/drm/armada/armada_overlay.c | 3 ++-
drivers/gpu/drm/armada/armada_plane.c
t;state
+ state
...+>
}
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Reintroduce the old_plane_state check in zynqmp_disp_crtc_atomic_disable
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 2 +-
drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 2 +-
drive
Hi Andre,
On Mon, Jan 18, 2021 at 03:52:28PM +, Andre Przywara wrote:
> On Mon, 18 Jan 2021 14:28:54 +0100
> Maxime Ripard wrote:
>
> Hi Maxime,
>
> > On Mon, Jan 18, 2021 at 02:08:29AM +, Andre Przywara wrote:
> > > From: Yangtao Li
> > >
>
Hi,
On Tue, Jan 19, 2021 at 02:29:08PM +0800, Liu Xiang wrote:
> When CONFIG_REGULATOR is not set, sunxi_pmx_request() always return
> success. Even a group of pins call sunxi_pmx_request(), the refcount
> is only 1. This can cause a use-after-free warning in sunxi_pmx_free().
> To solve this
c(struct drm_plane *plane, struct drm_plane_state *old_pstate)
{
<...
- state
+ new_pstate
...>
}
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/arm/malidp_planes.c | 34 +++---
drivers/gpu/drm/armada/armada_overlay.c | 104 +-
ane_state = drm_atomic_get_new_plane_state(state,
plane);
<...
- plane_state->state
+ state
...>
}
Reviewed-by: Laurent Pinchart
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Fixed the formatting in zynqmp_disp
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/
s;
@@
func(struct drm_plane *plane, struct drm_plane_state *old_s)
{
+ struct drm_plane_state *new_s = plane->state;
<+...
- plane->state
+ new_s
...+>
}
Reviewed-by: Laurent Pinchart
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Wrapping cha
}
Reviewed-by: Laurent Pinchart
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Updated the variable name in the comment in omapdrm
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++---
.../gpu/drm/arm/display/komeda/komeda_plane.c | 11 ++---
drivers/gpu/drm/arm/hdlcd_crtc.c
@ no_include depends on !include && adds_new_state @
@@
+ #include
#include
Reviewed-by: Laurent Pinchart
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Rewording and removal of a coccinelle rule suggested by Laurent
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |
<+...
- plane_state->state
+ state
...+>
}
Acked-by: Thomas Zimmermann
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Updated the comment according to Thomas suggestions
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++-
drivers/gpu/drm/drm_atomic_helper.c
Subsequent reworks will pass the global atomic state in the function
prototype, and atomic_check and atomic_update already have such a
variable already. Let's change them to ease the rework.
Acked-by: Sam Ravnborg
Signed-off-by: Maxime Ripard
---
.../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c
Hi Laurent,
On Fri, Jan 15, 2021 at 11:20:21PM +0200, Laurent Pinchart wrote:
> Hi Maxime,
>
> Thank you for the patch.
>
> On Fri, Jan 15, 2021 at 01:57:02PM +0100, Maxime Ripard wrote:
> > Many drivers reference the plane->state pointer in order to get the
gt; Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: Maxime Ripard
> Cc: Chen-Yu Tsai
> Cc: Jernej Skrabec
> Cc: linux-...@vger.kernel.org
> Cc: linux-arm-ker...@lists.infradead.org
> Signed-off-by: Lee Jones
Applied all three sunxi patches
Maxime
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On Mon, Jan 18, 2021 at 12:09:12AM +, Andre Przywara wrote:
> While comparing clocks between the H6 and H616, some of the M factor
> ranges were found to be wrong: the manual says they are only covering
> two bits [1:0], but our code had "5" in the number-of-bits field.
>
> By writing 0xff
On Fri, Jan 15, 2021 at 08:12:09PM +0100, Nicolas Saenz Julienne wrote:
> User-space ALSA matches a card's driver name against an internal list of
> aliases in order to select the correct configuration for the system.
> When the driver name isn't defined, the match is performed against the
>
Hi Sam
On Fri, Jan 15, 2021 at 09:43:24PM +0100, Sam Ravnborg wrote:
> On Fri, Jan 15, 2021 at 01:56:55PM +0100, Maxime Ripard wrote:
> > Subsequent reworks will pass the global atomic state in the function
> > prototype, and atomic_check and atomic_update already have such a
>
gned-off-by: Andre Przywara
Acked-by: Maxime Ripard
Maxime
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On Mon, Jan 18, 2021 at 02:08:41AM +, Andre Przywara wrote:
> The H616 has four PHYs as the H3, along with their respective clock
> gates and resets, so the property description is identical.
>
> However the PHYs itself need some special bits, so we need a new
> compatible string for it.
>
>
On Mon, Jan 18, 2021 at 02:08:42AM +, Andre Przywara wrote:
> The H616 MUSB peripheral is presumably compatible to the H3 one.
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Maxime
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NK1 register like the A100.
>
> Name all those properties in a new config struct and assign a new
> compatible name to it.
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Maxime
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ter.
> Let's put proper names to those "unknown" variables and symbols.
>
> While we are at it, generalise the existing code by allowing a bitmap
> of bits to clear, to cover newer SoCs: The A100 and H616 use a different
> bit for the SIDDQ control.
>
> Sign
On Mon, Jan 18, 2021 at 02:08:31AM +, Andre Przywara wrote:
> Port A is used for an internal connection to some analogue circuitry
> which looks like an AC200 IP (as in the H6), though this is not
> mentioned in the manual.
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime
On Mon, Jan 18, 2021 at 02:08:34AM +, Andre Przywara wrote:
> The clocks itself are identical to the H6 R-CCU, it's just that the H616
> has not all of them implemented (or connected).
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Maxime
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Desc
On Mon, Jan 18, 2021 at 02:08:33AM +, Andre Przywara wrote:
> Signed-off-by: Andre Przywara
> Acked-by: Rob Herring
Acked-by: Maxime Ripard
Maxime
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On Mon, Jan 18, 2021 at 02:08:30AM +, Andre Przywara wrote:
> A new SoC, a new compatible string.
> Also we were too miserly with just allowing seven interrupt banks.
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Maxime
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Hi,
On Mon, Jan 18, 2021 at 02:08:29AM +, Andre Przywara wrote:
> From: Yangtao Li
>
> This patch adds support for A100 MMC controller, which use word address
> for internal dma.
>
> Signed-off-by: Yangtao Li
> Signed-off-by: Andre Przywara
We should also disable the timings setup in
.
>
> Since this was the last user of the helper, it should now be safe to
> remove.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
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On Sat, Jan 16, 2021 at 11:37:10AM +0100, Jernej Skrabec wrote:
> Bluetooth module on BananaPi M2 Zero can also be used for streaming
> audio. However, for that case higher UART speed is required.
>
> Add a max-speed property.
>
> Signed-off-by: Jernej Skrabec
Applied, thanks
Maxime
On Sat, Jan 16, 2021 at 11:52:28AM +0100, Jernej Skrabec wrote:
> Bluetooth module on BananaPi M2 Plus can also be used for streaming
> audio. However, for that case higher UART speed is required.
>
> Add a max-speed property.
>
> Signed-off-by: Jernej Skrabec
Applied, thanks
Maxime
Hi,
On Fri, Jan 15, 2021 at 02:46:36PM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 15.01.21 um 13:56 schrieb Maxime Ripard:
> > diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
> > b/drivers/gpu/drm/imx/ipuv3-plane.c
> > index 8a4235d9d9f1..2cb09e9d9306 100644
> >
..
- plane_state->state
+ state
...+>
}
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 2 +-
.../gpu/drm/arm/display/komeda/komeda_plane.c | 2 +-
drivers/gpu/drm/arm/hdlcd_crtc.c | 2 +-
drivers/gpu/drm/arm/malidp_planes.c |
c(struct drm_plane *plane, struct drm_plane_state *old_pstate)
{
<...
- state
+ new_pstate
...>
}
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/arm/malidp_planes.c | 34 +++---
drivers/gpu/drm/armada/armada_overlay.c | 104 +-
s;
@@
func(struct drm_plane *plane, struct drm_plane_state *old_s)
{
+ struct drm_plane_state *new_s = plane->state;
<+...
- plane->state
+ new_s
...+>
}
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 7 ++--
dr
e
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/arc/arcpgu_crtc.c | 4 +++-
drivers/gpu/drm/arm/hdlcd_crtc.c| 3 ++-
drivers/gpu/drm/arm/malidp_planes.c | 3 ++-
drivers/gpu/drm/armada/armada_overlay.c | 3 ++-
drivers/gpu/drm/armada/armada_plane.c
ne->state
+ old_plane_state
...
}
@ include depends on adds_old_state || replaces_old_state @
@@
#include
@ no_include depends on !include && (adds_old_state || replaces_old_state) @
@@
+ #include
#include
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/imx/ipuv3-plane.c
<+...
- plane_state->state
+ state
...+>
}
Signed-off-by: Maxime Ripard
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++-
drivers/gpu/drm/drm_atomic_helper.c | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 26 +
drivers/gpu/drm/msm/disp/md
Signed-off-by: Maxime Ripard
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++---
.../gpu/drm/arm/display/komeda/komeda_plane.c | 11 ++---
drivers/gpu/drm/arm/hdlcd_crtc.c | 18
drivers/gpu/drm/arm/malidp_planes.c | 36
drivers/gp
ane_state = drm_atomic_get_new_plane_state(state,
plane);
<...
- plane_state->state
+ state
...>
}
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 2 +-
drivers/gpu/drm/arm/hdlcd_crtc.c | 2 +
!include && adds_new_state @
@@
+ #include
#include
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++-
drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 4 +++-
drivers/gpu/drm/arm/hdlcd_crtc.c | 4 +++-
drivers/gpu/drm/arm
Subsequent reworks will pass the global atomic state in the function
prototype, and atomic_check and atomic_update already have such a
variable already. Let's change them to ease the rework.
Signed-off-by: Maxime Ripard
---
.../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 118
ith appropriate firmware and configuration, this series allows waking
> from (and it has been tested with) the RTC, NMI/PMIC (power button, A/C
> plug, etc.), all GPIO ports (button, lid switch, modem, etc.), LRADC,
> and UARTs. I have tested this patch set on the H3, A64, H5, and H6 So
On Thu, Jan 14, 2021 at 12:45:12AM +, Andre Przywara wrote:
> On Mon, 14 Dec 2020 10:37:28 +0100
> Maxime Ripard wrote:
>
> > On Fri, Dec 11, 2020 at 01:19:15AM +, Andre Przywara wrote:
> > > A new SoC, a new compatible string.
> > > Also we were too
ls polarity.
>
> Fixes: 88bc4178568b ("drm: Use new
> DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags")
> Suggested-by: Maxime Ripard
> Signed-off-by: Giulio Benetti
> ---
> V2->V3:
> - squash 2 patches into 1
> V3->V4:
> - add SUN4I_TCON0_IO_POL_DCLK_POSITIVE t
> Signed-off-by: Samuel Holland
Acked-by: Maxime Ripard
Thanks!
Maxime
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ls polarity.
>
> Fixes: 88bc4178568b ("drm: Use new
> DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags")
> Suggested-by: Maxime Ripard
> Signed-off-by: Giulio Benetti
> ---
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +---
> drivers/gpu/drm/sun4i/sun4i_tcon.h
On Sun, Jan 10, 2021 at 09:19:44PM +0100, Jernej Skrabec wrote:
> This short series reworks CSC handling to remove duplicated constants
> (patch 1 and 2) and adds BT2020 encoding to DE3 (patch 3).
>
> Please take a look.
Applied, thanks
Maxime
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Hi,
On Wed, Jan 06, 2021 at 09:46:30PM +0100, Jernej Skrabec wrote:
> From: Roman Stratiienko
>
> To set blending channel order register software needs to know state and
> position of each channel, which impossible at plane commit stage.
>
> Move this procedure to atomic_flush stage, where all
On Sun, Jan 10, 2021 at 10:16:06PM +0100, Jernej Skrabec wrote:
> PineH64 model B has wifi+bt combo module. Wifi is already supported, so
> lets add also bluetooth node.
>
> Signed-off-by: Jernej Skrabec
Applied, thanks
Maxime
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Hi,
On Wed, Jan 13, 2021 at 12:06:09AM -0600, Samuel Holland wrote:
> Increase sound-dai-cells to 1 to allow using the DAIs in the codec
> corresponding to AIF2 and AIF3.
>
> The generic ASoC OF code supports a #sound-dai-cells value of 0 or 1
> with no impact to the driver, so this is a
.../input/allwinner,sun4i-a10-lradc-keys.yaml | 2 ++
> .../dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
> drivers/input/keyboard/sun4i-lradc-keys.c | 22 +++
> 3 files changed, 21 insertions(+), 4 deletions(-)
Acked-by: Maxime Ripard
I've applied patch 3
Maxime
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On Tue, Jan 12, 2021 at 10:51:28PM -0600, Samuel Holland wrote:
> This series cleans up some dead code in the sunxi-cir driver and adds
> system power management hooks.
Acked-by: Maxime Ripard
Thanks!
Maxime
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On Fri, Jan 08, 2021 at 11:38:19AM +0100, Sergio Sota wrote:
> The A10s/A13 mali gpu was not defined in device tree
> Add A10 mali gpu as a fallback for A10s/A13
> Tested with Olimex-A13-SOM / Olimex-A13-OlinuXino-MICRO
> "kmscube" 3d cube on screen (60fps / 10%cpu)
> Versions: Lima:1.1.0 EGL:1.4
On Fri, Jan 08, 2021 at 03:34:52PM +0100, Giulio Benetti wrote:
> Hi,
>
> On 1/8/21 10:23 AM, Maxime Ripard wrote:
> > Hi,
> >
> > Thanks for those patches
> >
> > On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote:
> > > From: G
t HSM clock rate depending on pixel
rate")
Reviewed-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index c3a301396aad..50
assert.
Fixes: 15b4511a4af6 ("drm/vc4: add HDMI CEC support")
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drive
From: Dom Cobley
Now that our HDMI controller supports CEC for the BCM2711, let's remove
that flag.
Reviewed-by: Dave Stevenson
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 ---
2 files changed, 7
on an external irqchip.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 42 ++
drivers/gpu/drm/vc4/vc4_hdmi.h | 7 ++
2 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 5a606b6f2917..eee9751009c2 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4
The CEC and hotplug interrupts go through an interrupt controller shared
between the two HDMI controllers.
Let's add that interrupt controller and the interrupts for both HDMI
controllers
Reviewed-by: Florian Fainelli
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/bcm2711.dtsi | 18
The CEC and hotplug interrupts were missing when that binding was
introduced, let's add them in now that we've figured out how it works.
Signed-off-by: Maxime Ripard
---
.../bindings/display/brcm,bcm2711-hdmi.yaml | 20 ++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff
The BSC controllers used for the HDMI DDC have an interrupt controller
shared between both instances. Let's add it to avoid polling.
Reviewed-by: Florian Fainelli
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/bcm2711.dtsi | 12
1 file changed, 12 insertions(+)
diff --git
While the BCM2835 had the CEC clock derived from the HSM clock, the
BCM2711 has a dedicated parent clock for it.
Let's introduce a separate clock for it so that we can handle both
cases.
Reviewed-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 9
.
Fixes: cd4cb49dc5bb ("drm/vc4: hdmi: Adjust HSM clock rate depending on pixel
rate")
Reviewed-by: Dave Stevenson
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 39 +-
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/drive
the code as much as possible, yet
still allowing to register independant handlers.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 86 +-
1 file changed, 65 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4
READ macro is now taking an enum,
and the offset doesn't increment by 4 but 1 now. Divide the index by 4
to fix this.
Fixes: 311e305fdb4e ("drm/vc4: hdmi: Implement a register layout abstraction")
Reviewed-by: Dave Stevenson
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
;)
Reviewed-by: Dave Stevenson
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
index 401863cb8c98.
The BCM2711 has a number of instances of interrupt controllers handled
by the driver behind the BRCMSTB_L2_IRQ Kconfig option (irq-brcmstb-l2).
Let's select that driver as part of the ARCH_BCM2835 Kconfig option.
Signed-off-by: Maxime Ripard
---
arch/arm/mach-bcm/Kconfig| 1 +
arch/arm64
registers
drm/vc4: hdmi: Restore cec physical address on reconnect
drm/vc4: hdmi: Remove cec_available flag
Maxime Ripard (10):
ARM: bcm: Select BRCMSTB_L2_IRQ for bcm2835
drm/vc4: hdmi: Compute the CEC clock divider from the clock rate
drm/vc4: hdmi: Update the CEC clock divider on HSM rate
registers are in a separate
block
Fixes: 9045e91a476b ("drm/vc4: hdmi: Add reset callback")
Reviewed-by: Dave Stevenson
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a
Hi Dave,
Thanks for your review
On Fri, Dec 18, 2020 at 02:45:54PM +, Dave Stevenson wrote:
> On Fri, 18 Dec 2020 at 14:21, Dave Stevenson
> wrote:
> >
> > Hi Maxime & Dom
> >
> > On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
> > >
>
by: Kévin L'hôpital
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Thanks!
Maxime
signature.asc
Description: PGP signature
onfiguration.
>
> Signed-off-by: Paul Kocialkowski
There's a couple of checkpatch --strict warnings here as well
Once fixed,
Acked-by: Maxime Ripard
Thanks!
Maxime
signature.asc
Description: PGP signature
d 10-bit Bayer formats are currently supported.
> While up to 4 internal channels to the CSI controller exist, only one
> is currently supported by this implementation.
>
> Signed-off-by: Paul Kocialkowski
CHECK: Alignment should match open parenthesis :)
Once fixed,
Acked-by: Maxime
On Thu, Dec 31, 2020 at 03:29:41PM +0100, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
Reviewed-by: Maxime Ripard
Thanks!
Maxime
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Description: PGP signature
not be linked in
> the fwnode graph unless they have a sensor subdev attached.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
signature.asc
Description: PGP signature
ated as fwnode port 0.
>
> Note that additional ports may be added in the future, especially to
> support feeding the CSI controller's output to the ISP.
>
> Signed-off-by: Paul Kocialkowski
> Reviewed-by: Rob Herring
Reviewed-by: Maxime Ripard
Maxime
Hi Samuel,
Thanks a lot for working on this
I'm fine with the rest of the work, but I have a couple of questions
On Sun, Jan 03, 2021 at 04:30:52AM -0600, Samuel Holland wrote:
> The R_INTC in the A31 and newer sun8i/sun50i SoCs has additional
> functionality compared to the sun7i/sun9i NMI
efore. So let's handle DCLK polarity by adding
> SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to
> bus_flags the same way is done for all the other signals.
>
> Cc: Maxime Ripard
Suggested-by would be nice here :)
> Signed-off-by: Giulio Benetti
> ---
>
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