Hi,
On Thu, Jan 07, 2021 at 11:59:27AM +0100, Sergio Sota wrote:
> The A10s/A13 display frontend driver is not implemented
> Set A10 display frontend driver as a fallback for A10s/A13
> Tested with Olimex-A13-SOM / Olimex-A13-OlinuXino-MICRO
> "modetest -M sun4i-drm -s 49@47:800x480-60" ( 7.0"
On Thu, Jan 07, 2021 at 12:00:35PM +0100, Sergio Sota wrote:
> The A10s/A13 mali gpu was not defined in device tree
> Add A10 mali gpu as a fallback for A10s/A13
> Tested with Olimex-A13-SOM / Olimex-A13-OlinuXino-MICRO
> "kmscube" 3d cube on screen (60fps / 10%cpu)
With Lima or the ARM blob, if
On Thu, Jan 07, 2021 at 09:43:14AM +0100, Wilken Gottwalt wrote:
> On Wed, 6 Jan 2021 11:15:42 +0100
> Maxime Ripard wrote:
>
> > On Wed, Dec 23, 2020 at 12:35:10PM +0100, Wilken Gottwalt wrote:
> > > Adds the sun6i_hwspinlock driver for the hardware spinlock
On Wed, Jan 06, 2021 at 07:25:23PM +0100, Jernej Skrabec wrote:
> Deinterlace core is completely compatible to H3.
>
> Add a node for it.
>
> Signed-off-by: Jernej Skrabec
> ---
> Note: I didn't add H5 fallback, since the only reason why this node
> is not in common H3/H5 dtsi is that it's
On Wed, Jan 06, 2021 at 07:18:59PM +0100, Jernej Skrabec wrote:
> These two patches add support for deinterlace core found on R40. It's
> compatible to H3 one, so only DT node is needed.
>
> Please take a look.
Applied, thanks
Maxime
signature.asc
Description: PGP signature
On Wed, Dec 30, 2020 at 11:42:05AM +0100, Dylan Van Assche wrote:
> All revisions of the PinePhone share most of the hardware.
> This patch makes it easier to detect PinePhone hardware without
> having to check for each possible revision.
>
> Signed-off-by: Dylan Van Assche
Applied, thanks
On Thu, Dec 24, 2020 at 10:41:38AM +0800, Icenowy Zheng wrote:
> As the original PineTab DT (which uses sun50i-a64-pinetab name) is only
> for development samples, document this.
>
> Signed-off-by: Icenowy Zheng
Applied all three patches, thanks for your persistence on this
Maxime
Hi,
On Wed, Dec 23, 2020 at 09:08:47PM +0100, Sergio Sota wrote:
> From c45753026b4868e32132348f8f2bf59e6ce5c820 Mon Sep 17 00:00:00 2001
> From: Sergio Sota
> Date: Wed, 23 Dec 2020 21:00:35 +0100
> Subject: [PATCH] ARM: dts sunxi: add A10s/A13 mali gpu support
>
> The A10s/A13 mali gpu was
Hi!
Thanks for your patch
The prefix in your commit title should be ARM: dts: sun5i
It looks like your patch has been wrapped. Make sure you send it through
git send-email, or at least that your mailer don't mangle it.
On Wed, Dec 23, 2020 at 08:58:15PM +0100, Sergio Sota wrote:
> From
On Mon, Jan 04, 2021 at 10:54:19AM +, André Przywara wrote:
> On 03/01/2021 10:00, Samuel Holland wrote:
> > On boards where the only peripheral connected to PL0/PL1 is an X-Powers
> > PMIC, configure the connection to use the RSB bus rather than the I2C
> > bus. Compared to the I2C controller
: h6-r: Add s_rsb pin functions
> arm64: dts: allwinner: h6: Add RSB controller node
> arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection
For the whole series,
Acked-by: Maxime Ripard
Thanks!
Maxime
signature.asc
Description: PGP signature
), 61 deletions(-)
For the whole series,
Acked-by: Maxime Ripard
Thanks!
Maxime
signature.asc
Description: PGP signature
- dropped unnecessary entries
> >
> > Changes in v4:
> > - changed binding to sun8i-a33-hwpinlock
> > - added changes suggested by Maxime Ripard
> >
> > Changes in v3:
> > - changed symbols from sunxi to sun8i
> >
> > Changes in v2:
> >
r supports only the 32 first locks. This is the reason the
> first way (lock read/write) approach is used to be able to cover all 256
> locks in future devices. The driver also reports the amount of supported
> locks via debugfs.
>
> Signed-off-by: Wilken Gottwalt
Reviewed-by: Maxime Ripard
Thanks!
Maxime
signature.asc
Description: PGP signature
On Mon, Jan 04, 2021 at 09:58:08AM -0700, Rob Herring wrote:
> Now that we have graph and video-interfaces schemas, rework the media
> related schemas to use them.
>
> Cc: Maxime Ripard
> Cc: Mauro Carvalho Chehab
> Cc: Jacopo Mondi
> Cc: Laurent Pinchart
> Cc: lin
Hi Dave,
On Fri, Dec 18, 2020 at 11:37:50AM +, Dave Stevenson wrote:
> Hi Maxime
>
> On Thu, 10 Dec 2020 at 13:47, Maxime Ripard wrote:
> >
> > While the BCM2835 had the CEC clock derived from the HSM clock, the
> > BCM2711 has a dedicated parent clock for
Hi,
On Thu, Dec 17, 2020 at 12:20:31PM +0100, Paul Kocialkowski wrote:
> This introduces definitions for the PWM controller found in the V3s,
> as well as associated pins. This fashion of the controller has two PWM
> outputs and is register-compatible with the A20.
>
> Both PWM outputs were
Hi Hans,
On Thu, Dec 17, 2020 at 11:53:42AM +0100, Hans Verkuil wrote:
> On 17/12/2020 11:49, Maxime Ripard wrote:
> > Hi Hans,
> >
> > On Wed, Dec 16, 2020 at 01:35:43PM +0100, Hans Verkuil wrote:
> >> Hi Maxime,
> >>
> >> On 10/12/2020 14:46, M
Hi Hans,
On Wed, Dec 16, 2020 at 01:35:43PM +0100, Hans Verkuil wrote:
> Hi Maxime,
>
> On 10/12/2020 14:46, Maxime Ripard wrote:
> > Hi,
> >
> > Here's a series introducing the CEC support for the BCM2711 found on the
> > RaspberryPi4.
> >
> > The
On Wed, Dec 16, 2020 at 09:22:12PM +0800, Zheng Yongjun wrote:
> Replace a comma between expression statements by a semicolon.
>
> Signed-off-by: Zheng Yongjun
Acked-by: Maxime Ripard
Thanks!
Maxime
signature.asc
Description: PGP signature
On Tue, Dec 15, 2020 at 06:59:33AM +0800, Icenowy Zheng wrote:
> 于 2020年12月14日 GMT+08:00 下午6:37:04, Maxime Ripard 写到:
> >On Thu, Dec 10, 2020 at 04:42:32PM +0800, Icenowy Zheng wrote:
> >> Early adopters' PineTabs (and all further releases) will have a new
> >LCD
> >
On Tue, Dec 15, 2020 at 07:18:48PM +0100, Christophe JAILLET wrote:
> Le 15/12/2020 à 12:37, Maxime Ripard a écrit :
> > On Tue, Dec 15, 2020 at 12:11:53PM +0300, Dan Carpenter wrote:
> > > On Tue, Dec 15, 2020 at 09:56:55AM +0100, Maxime Ripard wrote:
> > > > Hi,
&
Acked-by: Thierry Reding
Acked-by: Julia Lawall
Reviewed-by: Wolfram Sang
Reviewed-by: Mark Brown
Signed-off-by: Maxime Ripard
---
Changes from v1:
- Collected the tags
scripts/coccinelle/api/ptr_ret.cocci | 97
1 file changed, 97 deletions(-)
delete mode
On Tue, Dec 15, 2020 at 09:52:36AM +0100, Julia Lawall wrote:
>
>
> On Tue, 15 Dec 2020, Maxime Ripard wrote:
>
> > Hi,
> >
> > On Tue, Jan 07, 2020 at 11:29:54AM +0100, Wolfram Sang wrote:
> > > On Tue, Jan 07, 2020 at 11:06:56AM +0100, Julia Lawall wrote
On Tue, Dec 15, 2020 at 12:11:53PM +0300, Dan Carpenter wrote:
> On Tue, Dec 15, 2020 at 09:56:55AM +0100, Maxime Ripard wrote:
> > Hi,
> >
> > On Mon, Dec 14, 2020 at 09:21:17PM +0100, Christophe JAILLET wrote:
> > > 'irq_of_parse_and_map()' should
Hi,
On Mon, Dec 14, 2020 at 09:21:17PM +0100, Christophe JAILLET wrote:
> 'irq_of_parse_and_map()' should be balanced by a corresponding
> 'irq_dispose_mapping()' call. Otherwise, there is some resources leaks.
Do you have a source to back that? It's not clear at all from the
documentation for
Hi,
On Tue, Dec 15, 2020 at 10:16:11AM +0800, Tian Tao wrote:
> Fixes coccicheck warning:
> drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c:281:1-3: WARNING: PTR_ERR_OR_ZERO
> can be used
>
> Signed-off-by: Tian Tao
That script shouldn't be there anymore, see:
Hi,
On Tue, Jan 07, 2020 at 11:29:54AM +0100, Wolfram Sang wrote:
> On Tue, Jan 07, 2020 at 11:06:56AM +0100, Julia Lawall wrote:
> >
> >
> > On Tue, 7 Jan 2020, Maxime Ripard wrote:
> >
> > > The ptr_ret script script addresses a number of situations wh
On Mon, Dec 14, 2020 at 11:19:48PM +0800, Icenowy Zheng wrote:
>
>
> 于 2020年12月14日 GMT+08:00 下午10:21:18, Maxime Ripard 写到:
> >On Sat, Dec 12, 2020 at 12:04:23PM +0800, Icenowy Zheng wrote:
> >> V831/V833 are new chips from Allwinner. They're the same die wit
Hi Marc,
On Thu, Dec 10, 2020 at 05:59:09PM +, Marc Zyngier wrote:
> On 2020-12-10 13:46, Maxime Ripard wrote:
> > The BCM2711 uses a number of instances of the bcmstb-l2 controller in
> > its
> > display engine. Let's allow the driver to be enabled through KConfig
Hi Samuel,
On Sun, Dec 13, 2020 at 05:55:03PM -0600, Samuel Holland wrote:
> While no information about the H6 RSB controller is included in the
> datasheet or manual, the vendor BSP and power management blob both
> reference the RSB clock parent and register address. These values were
> verified
On Sat, Dec 12, 2020 at 01:12:01PM +0800, Icenowy Zheng wrote:
> + spi0: spi@501 {
> + compatible = "allwinner,sun8i-v831-spi",
> + "allwinner,sun50i-h6-spi",
> + "allwinner,sun8i-h3-spi";
That's
On Sat, Dec 12, 2020 at 01:03:42PM +0800, Icenowy Zheng wrote:
> V831 has MMC controllers similar to the ones on H6.
>
> Add a compatible string for them.
>
> The eMMC controller compatible is not added, because the eMMC controller
> is not available on V831, only V833.
>
> Cc: Ulf Hansson
>
On Sat, Dec 12, 2020 at 12:04:23PM +0800, Icenowy Zheng wrote:
> V831/V833 are new chips from Allwinner. They're the same die with
> different package.
>
> Add a pinctrl driver for them.
>
> The difference between V831/V833 pinctrl is implemented based on the
> user manual.
>
> Cc: Linus
On Mon, Dec 14, 2020 at 09:28:36PM +0800, Chen-Yu Tsai wrote:
> On Mon, Dec 14, 2020 at 8:53 PM Andre Przywara wrote:
> >
> > On Mon, 14 Dec 2020 10:58:31 +0100
> > Maxime Ripard wrote:
> >
> > Hi,
> >
> > > On Fri, Dec 11, 2020 at 01:19:32AM +
On Mon, Dec 14, 2020 at 12:53:43PM +, Andre Przywara wrote:
> On Mon, 14 Dec 2020 10:58:31 +0100
> Maxime Ripard wrote:
> > On Fri, Dec 11, 2020 at 01:19:32AM +, Andre Przywara wrote:
> > > + reserved-memory {
> > > + #address-cells = <2&g
On Fri, Dec 11, 2020 at 04:57:06PM +0100, Paul Kocialkowski wrote:
> The A83T supports MIPI CSI-2 with a composite controller, covering
> both the protocol logic and the D-PHY implementation. This controller
> seems to be found on the A83T only and probably was abandoned since.
>
> This
On Fri, Dec 11, 2020 at 04:57:02PM +0100, Paul Kocialkowski wrote:
> +#define sun6i_mipi_csi2_subdev_video(subdev) \
> + container_of(subdev, struct sun6i_mipi_csi2_video, subdev)
> +
> +#define sun6i_mipi_csi2_video_dev(video) \
> + container_of(video, struct sun6i_mipi_csi2_dev, video)
On Fri, Dec 11, 2020 at 04:57:01PM +0100, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
> ---
> .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 149 ++
> 1 file changed, 149
On Fri, Dec 11, 2020 at 04:57:00PM +0100, Paul Kocialkowski wrote:
> The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
> its own dedicated port in the fwnode graph.
>
> Support for this input is added with this change:
> - two pads are defined for the media entity instead of
On Thu, Dec 10, 2020 at 04:45:58PM +0800, Icenowy Zheng wrote:
> As the old LCD panel used by PineTab developer samples are discontinued,
> there won't be furtherly any more units of the sample, and this should
> be noted in the document.
>
> Signed-off-by: Icenowy Zheng
> ---
>
On Thu, Dec 10, 2020 at 04:42:32PM +0800, Icenowy Zheng wrote:
> Early adopters' PineTabs (and all further releases) will have a new LCD
> panel different with the one that is used when in development (because
> the old panel's supply discontinued).
>
> Add a new DT compatible for it.
>
>
On Fri, Dec 11, 2020 at 10:13:11AM +0100, Wilken Gottwalt wrote:
> On Fri, 11 Dec 2020 09:57:57 +0100
> Maxime Ripard wrote:
>
> > Hi,
> >
> > On Fri, Dec 11, 2020 at 09:23:48AM +0100, Wilken Gottwalt wrote:
> > > Adds documentation on how to use t
Hi Sebastian,
On Sun, Dec 13, 2020 at 12:41:16AM +0100, Sebastian Reichel wrote:
> Hi,
>
> On Fri, Dec 11, 2020 at 04:14:43PM +0100, Michael Klein wrote:
> > This driver registers a pm_power_off function to turn off the board
> > by force-disabling a devicetree-defined regulator.
> >
> >
On Fri, Dec 11, 2020 at 04:14:45PM +0100, Michael Klein wrote:
> Add add devicetree information for the regulator-poweroff driver.
>
> Signed-off-by: Michael Klein
Queued for 5.12, thanks!
Maxime
signature.asc
Description: PGP signature
On Fri, Dec 11, 2020 at 01:19:34AM +, Andre Przywara wrote:
> The OrangePi Zero 2 is a development board with the new H616 SoC.
>
> It features the usual connectors used on those small boards, and comes
> with the AXP305, which seems to be compatible with the AXP805.
>
> For more details
On Fri, Dec 11, 2020 at 01:19:32AM +, Andre Przywara wrote:
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* 512KiB reserved for ARM Trusted Firmware (BL31) */
> + secmon_reserved:
On Fri, Dec 11, 2020 at 01:19:28AM +, Andre Przywara wrote:
> The USB PHY used in the Allwinner H616 SoC inherits some traits from its
> various predecessors: it has four full PHYs like the H3, needs some
> extra bits to be set like the H6, and clears a different bit in the
> PMU_UNK1 register
On Fri, Dec 11, 2020 at 01:19:16AM +, Andre Przywara wrote:
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "h_i2s2"),/* MCLK */
> +
On Fri, Dec 11, 2020 at 01:19:15AM +, Andre Przywara wrote:
> A new SoC, a new compatible string.
> Also we were too miserly with just allowing seven interrupt banks.
>
> Signed-off-by: Andre Przywara
> ---
> .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 18 --
> 1 file
to sun8i
> - improved driver description
> - further simplified driver
> - fully switched to devm_* and devm_add_action_* functions
>
> Changes in v2:
> - added suggestions from Bjorn Andersson and Maxime Ripard
> - provided better driver and test descriptio
added changes suggested by Maxime Ripard
>
> Changes in v3:
> - changed symbols from sunxi to sun8i
>
> Changes in v2:
> - fixed memory ranges
> ---
> .../bindings/hwlock/sun8i-hwspinlock.yaml | 56 +++
> 1 file changed, 56 insertions(+)
> c
Hi
On Tue, Dec 08, 2020 at 01:52:14PM +0100, Michael Klein wrote:
> Thanks for reviewing!
>
> On Tue, Dec 08, 2020 at 11:13:58AM +0100, Maxime Ripard wrote:
> > On Mon, Dec 07, 2020 at 03:27:55PM +0100, Michael Klein wrote:
> > > Add devicetree binding documentation for r
assert.
Fixes: 15b4511a4af6 ("drm/vc4: add HDMI CEC support")
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drive
The BSC controllers used for the HDMI DDC have an interrupt controller
shared between both instances. Let's add it to avoid polling.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/bcm2711.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b
READ macro is now taking an enum,
and the offset doesn't increment by 4 but 1 now. Divide the index by 4
to fix this.
Fixes: 311e305fdb4e ("drm/vc4: hdmi: Implement a register layout abstraction")
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm
the code as much as possible, yet
still allowing to register independant handlers.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 86 +-
1 file changed, 65 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4
.
Fixes: cd4cb49dc5bb ("drm/vc4: hdmi: Adjust HSM clock rate depending on pixel
rate")
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 39 +-
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/d
rate depending on pixel
rate")
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index eff3bac562c6..0c53d7427d15 100644
--- a/drivers/gpu/drm/vc4/
on an external irqchip.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 42 ++
drivers/gpu/drm/vc4/vc4_hdmi.h | 7 ++
2 files changed, 39 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 327638d93032..69217c68d3a4 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1655,9
The CEC and hotplug interrupts go through an interrupt controller shared
between the two HDMI controllers.
Let's add that interrupt controller and the interrupts for both HDMI
controllers
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/bcm2711.dtsi | 18 ++
1 file changed
From: Dom Cobley
Now that our HDMI controller supports CEC for the BCM2711, let's remove
that flag.
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4
drivers/gpu/drm/vc4/vc4_hdmi.h | 3 ---
2 files changed, 7 deletions(-)
diff --git
The CEC and hotplug interrupts were missing when that binding was
introduced, let's add them in now that we've figured out how it works.
Signed-off-by: Maxime Ripard
---
.../bindings/display/brcm,bcm2711-hdmi.yaml | 20 ++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff
While the BCM2835 had the CEC clock derived from the HSM clock, the
BCM2711 has a dedicated parent clock for it.
Let's introduce a separate clock for it so that we can handle both
cases.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 9 -
drivers/gpu/drm/vc4
)
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h
index 013fd57febd8..20a1438a72cb 100644
--- a
registers are in a separate
block
Fixes: 9045e91a476b ("drm/vc4: hdmi: Add reset callback")
Signed-off-by: Dom Cobley
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b
/vc4: hdmi: Fix up CEC registers
drm/vc4: hdmi: Restore cec physical address on reconnect
drm/vc4: hdmi: Remove cec_available flag
Maxime Ripard (10):
irqchip: Allow to compile bcmstb on other platforms
drm/vc4: hdmi: Compute the CEC clock divider from the clock rate
drm/vc4: hdmi: Update
The BCM2711 uses a number of instances of the bcmstb-l2 controller in its
display engine. Let's allow the driver to be enabled through KConfig.
Signed-off-by: Maxime Ripard
---
drivers/irqchip/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/Kconfig b
On Mon, Dec 07, 2020 at 03:27:55PM +0100, Michael Klein wrote:
> Add devicetree binding documentation for regulator-poweroff driver.
>
> Signed-off-by: Michael Klein
> ---
> .../power/reset/regulator-poweroff.yaml | 53 +++
> 1 file changed, 53 insertions(+)
> create mode
On Mon, Dec 07, 2020 at 03:27:54PM +0100, Michael Klein wrote:
> This driver registers a pm_power_off function to disable a set of
> regulators defined in the devicetree to turn off the board.
>
> Signed-off-by: Michael Klein
> ---
> drivers/power/reset/Kconfig | 7 ++
>
On Sun, Dec 06, 2020 at 05:51:26PM +0100, Paul Kocialkowski wrote:
> This series adds support for the Allwinner V3-based SL631 family of
> Action Cameras, starting with the IMX179 fashion.
>
> A few fixes to V3 support are added along the way, most notably support
> for the NMI IRQ controller
On Sun, Dec 06, 2020 at 05:41:19PM +0100, Paul Kocialkowski wrote:
> Add documentation about the Allwinner system-control bindings used
> for the V3s SoC. The bindings are already in use in the device-tree
> files and produced warnings in dt bindings checks.
>
> Signed-off-by: Paul Kocialkowski
On Tue, Dec 08, 2020 at 03:21:38PM +0800, Shuosheng Huang wrote:
> Enable cpufreq for all CPU cores on a100.
>
> Signed-off-by: Shuosheng Huang
> ---
> .../allwinner/sun50i-a100-allwinner-perf1.dts| 16
> arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 6 +++---
> 2
On Tue, Dec 08, 2020 at 03:20:46PM +0800, Shuosheng Huang wrote:
> Add an Operating Performance Points table for the CPU cores to
> enable Dynamic Voltage & Frequency Scaling on the A100.
>
> Signed-off-by: Shuosheng Huang
> ---
> .../allwinner/sun50i-a100-allwinner-perf1.dts | 1 +
>
Hi,
On Tue, Dec 08, 2020 at 03:19:28PM +0800, Shuosheng Huang wrote:
> It's better to use efuse_xlate to extract the differentiated part
> regarding different SoC.
>
> Signed-off-by: Shuosheng Huang
Please wait a bit for reviews before sending a new version. You've sent
three versions in a
On Mon, Dec 07, 2020 at 05:05:34PM +0100, Wilken Gottwalt wrote:
> + io_base = devm_platform_ioremap_resource(pdev, SPINLOCK_BASE_ID);
> + if (IS_ERR(io_base)) {
> + err = PTR_ERR(io_base);
> + dev_err(>dev, "unable to request MMIO (%d)\n", err);
There's already a
Hi,
On Mon, Dec 07, 2020 at 05:05:03PM +0100, Wilken Gottwalt wrote:
> Adds documentation on how to use the sun8i_hwspinlock driver for sun8i
> compatible SoCs.
>
> Signed-off-by: Wilken Gottwalt
> ---
> .../bindings/hwlock/sun8i-hwspinlock.yaml | 63 +++
> 1 file changed,
On Wed, Dec 02, 2020 at 05:06:40PM +0100, Paul Kocialkowski wrote:
> > > +static void logicvc_crtc_atomic_begin(struct drm_crtc *drm_crtc,
> > > + struct drm_atomic_state *state)
> > > +{
> > > + struct logicvc_crtc *crtc = logicvc_crtc(drm_crtc);
> > > + struct
On Sun, Dec 06, 2020 at 10:03:16PM +0100, Clément Péron wrote:
> Hi Maxime
>
> On Tue, 1 Dec 2020 at 11:35, Maxime Ripard wrote:
> >
> > On Sat, Nov 28, 2020 at 10:07:27PM +0100, Clément Péron wrote:
> > > Hi Maxime, Icenowy,
> > >
> > > On
On Wed, Dec 02, 2020 at 08:51:47PM +0100, Michael Klein wrote:
> Add gpio-line-names as documented on gitbooks [1] and in the
> schematics [2].
>
> [1]: https://bananapi.gitbook.io/bpi-m2/en/bpi-m2_gpio_pin_define
> [2]: https://drive.google.com/file/d/0B4PAo2nW2KfnRERWNnJGSGxJbmM/view
>
>
On Fri, Dec 04, 2020 at 06:07:25PM +0100, Wilken Gottwalt wrote:
> On Fri, 4 Dec 2020 17:21:17 +0100
> Maxime Ripard wrote:
>
> > On Fri, Dec 04, 2020 at 04:35:12PM +0100, Wilken Gottwalt wrote:
> > > Adds the sunxi_hwspinlock driver for the hardware spinlock
On Fri, Dec 04, 2020 at 04:35:12PM +0100, Wilken Gottwalt wrote:
> Adds the sunxi_hwspinlock driver for the hardware spinlock unit found in
> most of the sun8i and sun50i based SoCs.
>
> This unit provides at least 32 spinlocks in hardware. The implementation
> supports 32, 64, 128 or 256 32bit
San.
>
> Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
> Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
> Signed-off-by: Jernej Skrabec
Acked-by: Maxime Ripard
Mike, Stephen, it's the only patch we're going to send your way for this
release, could you pick
On Wed, Dec 02, 2020 at 01:54:09PM +, Andre Przywara wrote:
> The OrangePi Zero 2 is a development board with the new H616 SoC.
>
> It features the usual connectors used on those small boards, and comes
> with the AXP305, which seems to be compatible with the AXP805.
>
> For more details
On Wed, Dec 02, 2020 at 01:54:08PM +, Andre Przywara wrote:
> This (relatively) new SoC is similar to the H6, but drops the (broken)
> PCIe support and the USB 3.0 controller. It also gets the management
> controller removed, which in turn removes *some*, but not all of the
> devices formerly
Hi
On Wed, Dec 02, 2020 at 01:54:06PM +, Andre Przywara wrote:
> While the clocks are fairly similar to the H6, many differ in tiny
> details, so a separate clock driver seems indicated.
>
> Derived from the H6 clock driver, and adjusted according to the manual.
>
> Signed-off-by: Andre
bunch of issues with wrapped lines alignment reported by
checkpatch --patch.
Once fixed,
Acked-by: Maxime Ripard
Maxime
signature.asc
Description: PGP signature
On Wed, Dec 02, 2020 at 01:54:04PM +, Andre Przywara wrote:
> There are only two pins left now, used to connect to the PMIC via I2C.
>
> Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Maxime
signature.asc
Description: PGP signature
On Wed, Dec 02, 2020 at 03:44:47PM +0100, Paul Kocialkowski wrote:
> > > +static int __maybe_unused sun6i_mipi_csi2_suspend(struct device *dev)
> > > +{
> > > + struct sun6i_mipi_csi2_dev *cdev = dev_get_drvdata(dev);
> > > +
> > > + clk_disable_unprepare(cdev->clk_mod);
> > > +
On Wed, Dec 02, 2020 at 04:02:09PM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Tue 01 Dec 20, 13:14, Maxime Ripard wrote:
> > On Sat, Nov 28, 2020 at 03:28:29PM +0100, Paul Kocialkowski wrote:
> > > Since the CSI controller binding is getting a bit more complex due
>
On Wed, Dec 02, 2020 at 03:19:11PM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Tue 01 Dec 20, 13:12, Maxime Ripard wrote:
> > Hi,
> >
> > On Sat, Nov 28, 2020 at 03:28:27PM +0100, Paul Kocialkowski wrote:
> > > The A31 CSI controller supports a MIPI CSI-2 b
river")
> Signed-off-by: Nicolas Saenz Julienne
Reviewed-by: Maxime Ripard
Maxime
signature.asc
Description: PGP signature
On Sat, Nov 28, 2020 at 08:18:16PM +, André Przywara wrote:
> On 11/11/2020 22:50, Rob Herring wrote:
>
> Hi,
>
> > On Tue, Nov 10, 2020 at 02:39:42PM +0800, Frank Lee wrote:
> >> From: Yangtao Li
> >>
> >> Add a device tree binding for the A100's USB PHY.
>
> Not your fault, Yangto, but
Hi,
On Sat, Nov 28, 2020 at 03:28:33PM +0100, Paul Kocialkowski wrote:
> The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
> found on Allwinner SoCs such as the A31 and V3/V3s.
>
> It is a standalone block, connected to the CSI controller on one side
> and to the MIPI D-PHY block on
On Sat, Nov 28, 2020 at 03:28:32PM +0100, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the A31 MIPI CSI-2
> controller.
>
> Signed-off-by: Paul Kocialkowski
> ---
> .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 151 ++
> 1 file changed, 151
On Sat, Nov 28, 2020 at 03:28:29PM +0100, Paul Kocialkowski wrote:
> Since the CSI controller binding is getting a bit more complex due
> to the addition of MIPI CSI-2 bridge support, make the ports node
> explicit with the parallel port.
>
> This way, it's clear that the controller only supports
Hi,
On Sat, Nov 28, 2020 at 03:28:27PM +0100, Paul Kocialkowski wrote:
> The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
> its own dedicated port in the fwnode graph.
>
> Support for this input is added with this change:
> - two pads are defined for the media entity instead
On Sat, Nov 28, 2020 at 03:28:26PM +0100, Paul Kocialkowski wrote:
> The A31 CSI controller supports two distinct input interfaces:
> parallel and an external MIPI CSI-2 bridge. The parallel interface
> is often connected to a set of hardware pins while the MIPI CSI-2
> bridge is an internal
ion is inspired by Allwinner's V3s Linux SDK
> implementation, which was used as a documentation base.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
signature.asc
Description: PGP signature
201 - 300 of 12711 matches
Mail list logo
