sun6i: Add support for Allwinner CSI V3s")
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
signature.asc
Description: PGP signature
On Sat, Nov 28, 2020 at 03:28:21PM +0100, Paul Kocialkowski wrote:
> Besides giving pointers to the relevant functions for PHY mode and
> submode configuration, this clarifies the need to set them before
> powering on the PHY.
>
> Signed-off-by: Paul Kocialkowski
Reviewed-by
; > >
> > >On Sat, 28 Nov 2020 at 12:28, Icenowy Zheng wrote:
> > >>
> > >> 在 2020-11-28星期六的 11:38 +0100，Maxime Ripard写道：
> > >> > On Mon, Nov 23, 2020 at 09:10:38PM +0800, Icenowy Zheng wrote:
> > >> > > > > > > &g
On Mon, Nov 30, 2020 at 07:38:43PM +0100, Michael Klein wrote:
> Add regulator nodes vcc-dram and vcc1v2 to the devicetree. These
> regulators correspond to U4 and U5 in the schematics:
>
> http://forum.banana-pi.org/t/bpi-m2-zero-schematic-diagram-public/4111
>
> Signed-off-by: Michael Klein
On Sun, Nov 29, 2020 at 08:45:12PM +0100, Heinrich Schuchardt wrote:
> Since commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
> delay config") network is broken on the NanoPi Neo Plus2.
>
> This patch changes the phy-mode to use internal delays both for RX and TX
> as has been done for
On Sun, Nov 29, 2020 at 05:26:27PM +0100, Heinrich Schuchardt wrote:
> Since commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
> delay config") iSCSI booting fails on the Pine A64 LTS.
>
> This patch changes the phy-mode to use internal delays both for RX and TX
> as has been done for
On Mon, Nov 23, 2020 at 09:10:38PM +0800, Icenowy Zheng wrote:
> >> >> > Okay. But I'm not satisfied with a non-public sample occupies
> >> >> > the pinetab name. Is rename it to pinetab-dev and add a
> >> >> > pinetab-retail okay?
> >> >>
> >> >> To me, naming the production version anything but
On Tue, Nov 24, 2020 at 11:31:59PM +0100, Michael Klein wrote:
> On Tue, Nov 24, 2020 at 03:26:56PM +0100, Maxime Ripard wrote:
> > On Tue, Nov 24, 2020 at 02:36:33PM +0100, Michael Klein wrote:
> > > Add poweroff node to allow the board to power itself off after shutdown
On Mon, Nov 23, 2020 at 09:35:52PM -0600, Samuel Holland wrote:
> On 11/23/20 12:32 PM, Wilken Gottwalt wrote:
> > On Sat, 21 Nov 2020 17:44:18 +0100
> > Maxime Ripard wrote:
> >
> >> On Sat, Nov 21, 2020 at 08:22:55PM +0800, fuyao wrote:
> >>> On Fri
On Tue, Nov 24, 2020 at 02:36:33PM +0100, Michael Klein wrote:
> Add poweroff node to allow the board to power itself off after shutdown
> by disabling the SYSTEM and CPUX regulators (U5 resp. U6). The RST
> button can be used to restart the board.
>
> Signed-off-by: Michael Klein
> ---
>
On Mon, Nov 23, 2020 at 12:45:35PM +0100, Michael Klein wrote:
> Add gpio-line-names as documented in the Banana Pi wiki [1] and in the
> schematics [2].
>
> [1]: http://wiki.banana-pi.org/Banana_Pi_BPI-M2_ZERO#GPIO_PIN_define
> [2]:
On Tue, Nov 24, 2020 at 12:41:37PM +0800, Chen-Yu Tsai wrote:
> On Tue, Nov 24, 2020 at 12:14 PM Samuel Holland wrote:
> >
> > On 11/23/20 10:10 AM, Michael Klein wrote:
> > > Add gpio-poweroff node to allow the board to power itself off after
> > > shutdown by disabling the SYSTEM and CPUX
On Mon, Nov 23, 2020 at 05:10:41PM +0100, Michael Klein wrote:
> Add gpio-poweroff node to allow the board to power itself off after
> shutdown by disabling the SYSTEM and CPUX regulators (U5 resp. U6).
> The RST button can be used to restart the board.
>
> Signed-off-by: Michael Klein
> ---
>
On Tue, Nov 24, 2020 at 10:18:04AM +0100, Christoph Hellwig wrote:
> On Tue, Nov 24, 2020 at 09:31:15AM +1100, Stephen Rothwell wrote:
> > Hi all,
> >
> > After merging the arm-soc tree, today's linux-next build (arm
> > multi_v7_defconfig) failed like this:
> >
> >
On Mon, Nov 23, 2020 at 07:25:47PM +0800, Icenowy Zheng wrote:
>
>
> 于 2020年11月23日 GMT+08:00 下午7:15:12, Maxime Ripard 写到:
> >Hi!
> >
> >On Fri, Nov 20, 2020 at 08:51:48PM -0600, Samuel Holland wrote:
> >> On 11/20/20 5:30 PM, Icenowy Zheng wrote:
>
Hi!
On Fri, Nov 20, 2020 at 08:51:48PM -0600, Samuel Holland wrote:
> On 11/20/20 5:30 PM, Icenowy Zheng wrote:
> >>> +/ {
> >>> + model = "PineTab Developer Sample";
> >>> + compatible = "pine64,pinetab-dev", "allwinner,sun50i-a64";
> >>> +};
> >>
> >> Changing
On Sat, Nov 21, 2020 at 08:22:55PM +0800, fuyao wrote:
> On Fri, Nov 20, 2020 at 05:42:31PM +0100, Maxime Ripard wrote:
> > Hi,
> >
> > On Thu, Nov 19, 2020 at 11:13:43AM +0100, Wilken Gottwalt wrote:
> > > On Thu, 19 Nov 2020 08:15:23 +0100
> > > Maxime R
On Fri, Nov 20, 2020 at 01:08:51PM +0800, Icenowy Zheng wrote:
> Currently the GIC node in V3s DTSI follows some old DT examples, and
> being broken. This leads a warning at boot.
>
> Fix this.
>
> Fixes: f989086ccbc6 ("ARM: dts: sunxi: add dtsi file for V3s SoC")
> Signed-off-by: Icenowy Zheng
Hi,
On Thu, Nov 19, 2020 at 11:13:43AM +0100, Wilken Gottwalt wrote:
> On Thu, 19 Nov 2020 08:15:23 +0100
> Maxime Ripard wrote:
> > > can you help me here a bit? I still try to figure out how to do patch sets
> > > properly. Some kernel submitting documentat
Hi!
On Thu, Nov 19, 2020 at 02:44:51PM +0800, fu...@allwinnertech.com wrote:
> From: fuyao
>
> this series add hwspinlock of sunxi. it provides hardware assistance for
> synchronization between the multiple processors in the system.
> (Or1k, Cortex-A7, Cortex-A53, Xtensa)
Xtensa? Which SoC has
On Tue, Nov 17, 2020 at 02:36:48AM +0800, Icenowy Zheng wrote:
>
>
> 于 2020年11月16日 GMT+08:00 下午11:55:08, Maxime Ripard 写到:
> >On Tue, Nov 10, 2020 at 06:41:37PM +0800, Icenowy Zheng wrote:
> >>
> >>
> >> 于 2020年11月10日 GMT+08:00 下午6:39:25, Maxime Ripar
Hi!
On Sun, Nov 15, 2020 at 11:24:25PM +0100, Michael Klein wrote:
> Add gpio-line-names as documented in the Banana Pi wiki [1] and in the
> schematics [2].
>
> [1]: http://wiki.banana-pi.org/Banana_Pi_BPI-M2_ZERO#GPIO_PIN_define
> [2]:
On Mon, Nov 09, 2020 at 01:33:57PM +0800, Icenowy Zheng wrote:
> According to the user manual, PLL-CPUX have two dividers, in which P is
> only allowed when the desired rate is less than 240MHz. As the CCU
> framework have no such feature yet and the clock rate that allows P is
> much lower than
On Mon, Nov 09, 2020 at 01:33:56PM +0800, Icenowy Zheng wrote:
> According to Ondrej Jirman, switching of the mux of CPUX clock is one of
> the sources of timer jumps on A64 (and maybe this will also lead to
> timer jump on H3).
Isn't the arch timer supposed to be clocked directly for the 24MHz
Hi Christoph,
On Thu, Nov 19, 2020 at 08:59:59AM +0100, Christoph Hellwig wrote:
> On Mon, Nov 09, 2020 at 10:43:03AM +0100, Maxime Ripard wrote:
> > Hi Christoph, Chen-Yu, Hans,
> >
> > On Fri, Nov 06, 2020 at 05:07:37PM +0100, Christoph Hellwig wrote:
> > > Thanks
On Wed, Nov 18, 2020 at 08:36:24PM +0100, Wilken Gottwalt wrote:
> On Wed, 18 Nov 2020 16:37:33 +0100
> Maxime Ripard wrote:
> > Hi Wilken,
> >
> > On Wed, Nov 18, 2020 at 11:02:40AM +0100, Wilken Gottwalt wrote:
> > > Adds the sunxi_hwspinlock driver
])
>
> /usr/bin/mips-linux-gnu-ld: drivers/clk/clk.o: in function `clk_set_rate':
> (.text+0xaeb4): multiple definition of `clk_set_rate';
> arch/mips/ralink/clk.o:(.text+0x88): first defined here
>
> Signed-off-by: Krzysztof Kozlowski
> Reviewed-by: Samuel Holland
Ac
Hi Wilken,
On Wed, Nov 18, 2020 at 11:02:40AM +0100, Wilken Gottwalt wrote:
> Adds the sunxi_hwspinlock driver and updates makefiles/maintainers.
>
> Signed-off-by: Wilken Gottwalt
A more descriptive commit log would be welcome here, for example
containing on which SoC this driver can be used,
On Tue, Nov 17, 2020 at 08:06:19PM +0300, Sergey Suloev wrote:
> Hi, ChenYu,
>
> I have tried to build and run linux-next by tag "next-20201117".
> Now the boot log looks different but the kernel still hangs. See
> https://pastebin.com/gFk7XuBc
This one looks like you just had the wrong boot
On Tue, Nov 10, 2020 at 06:41:37PM +0800, Icenowy Zheng wrote:
>
>
> 于 2020年11月10日 GMT+08:00 下午6:39:25, Maxime Ripard 写到:
> >On Sat, Nov 07, 2020 at 08:53:32PM +0800, Icenowy Zheng wrote:
> >> Some developers received PineTab samples that used an old LCD panel.
&g
Hi,
On Sat, Nov 14, 2020 at 08:20:54PM +0300, Sergey Suloev wrote:
> Hi,
>
> I noticed that BananaPi M2 (A31 SoC) does not boot anymore on modern
> kernels. The problem arises somewhere between 5.7.19 - 5.8.18. I have saved
> boot logs for both versions https://pastebin.com/DTRZi8R7 and
>
On Thu, Nov 12, 2020 at 08:26:52PM +, Corentin Labbe wrote:
> Lot of sunxi boards has a Realtek PHY, so let's enable it.
>
> Signed-off-by: Corentin Labbe
Applied, thanks!
Maxime
signature.asc
Description: PGP signature
Hi Sakari,
On Wed, Nov 11, 2020 at 03:18:57PM +0200, Sakari Ailus wrote:
> Hi Paul,
>
> On Thu, Nov 05, 2020 at 04:35:34PM +0100, Paul Kocialkowski wrote:
> > Hi Sakari,
> >
> > On Thu 05 Nov 20, 10:19, Sakari Ailus wrote:
> > > Hi Paul,
> > >
> > > On Wed, Nov 04, 2020 at 11:26:43AM +0100,
Hi,
On Tue, Nov 10, 2020 at 03:00:02PM +0800, Frank Lee wrote:
> From: Yangtao Li
>
> Add myself to sunxi maintainer so the mail can cc me.
>
> Signed-off-by: Yangtao Li
Unfortunately, this is not really the process for doing so, and being in
Cc of the patches isn't what a maintainer is
Hi,
On Mon, Nov 09, 2020 at 08:21:01PM +0800, Frank Lee wrote:
> From: Yangtao Li
>
> Sid should be an efuse type device accurately. And no one
> needs sid label, so delete it.
>
> Signed-off-by: Yangtao Li
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +-
> 1 file changed, 1
On Tue, Nov 10, 2020 at 09:44:37PM -0600, Samuel Holland wrote:
> On 11/9/20 6:12 AM, Frank Lee wrote:
> > From: Yangtao Li
> >
> > The debounce and poll time is generally quite long and the work not
> > performance critical so allow the scheduler to run the work anywhere
> > rather than in the
On Wed, Oct 28, 2020 at 08:15:45PM +0800, Frank Lee wrote:
> On Wed, Jul 29, 2020 at 9:06 PM Maxime Ripard wrote:
> >
> > Hi,
> >
> > On Sat, Jul 25, 2020 at 02:18:39PM -0500, Samuel Holland wrote:
> > > On 7/17/20 11:07 AM, Maxime Ripard wrote:
> > &g
On Sat, Nov 07, 2020 at 08:53:32PM +0800, Icenowy Zheng wrote:
> Some developers received PineTab samples that used an old LCD panel.
>
> Add device tree for these samples.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm64/boot/dts/allwinner/Makefile| 1 +
>
igned-off-by: Yangtao Li
Acked-by: Maxime Ripard
Thanks!
Maxime
signature.asc
Description: PGP signature
On Mon, Nov 09, 2020 at 07:46:24PM +0800, Frank Lee wrote:
> From: Yangtao Li
>
> The bitmap_* API is the standard way to access data in the bitfield.
> So convert irq_ack to return an unsigned long, and make things to use
> bitmap API.
>
> Signed-off-by: Yangtao Li
Ac
Hi Christoph, Chen-Yu, Hans,
On Fri, Nov 06, 2020 at 05:07:37PM +0100, Christoph Hellwig wrote:
> Thanks,
>
> this looks good to me:
>
> Reviewed-by: Christoph Hellwig
>
> Can you include this patch at the end of your series to that it gets
> picked up with the other patches?
I guess the
Now that the MBUS quirks are applied by our global notifier, we can
remove them from our CSI driver for the A31.
Suggested-by: Christoph Hellwig
Signed-off-by: Maxime Ripard
---
.../media/platform/sunxi/sun6i-csi/sun6i_csi.c | 17 -
1 file changed, 17 deletions(-)
diff --git
Hi,
Here's an attempt to removing the dma_direct_set_offset calls we have in
numerous drivers and move all those quirks into a global notifier as suggested
by Robin.
Let me know what you think,
Maxime
Maxime Ripard (7):
drm/sun4i: backend: Fix probe failure with multiple backends
soc: sunxi
Now that the MBUS quirks are applied by our global notifier, we can
remove them from our CSI driver for the A10.
Suggested-by: Christoph Hellwig
Signed-off-by: Maxime Ripard
---
.../platform/sunxi/sun4i-csi/sun4i_csi.c | 27 ---
1 file changed, 27 deletions(-)
diff --git
temporary measure to get it back working, before
removing that call entirely.
Fixes: e0d072782c73 ("dma-mapping: introduce DMA range map, supplanting
dma_pfn_offset")
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 8 +++-
1 file changed, 7 insertions(+),
of_dma_configure is called by the core before probe gets called so this
is redundant.
Signed-off-by: Maxime Ripard
---
drivers/media/platform/sunxi/sun8i-di/sun8i-di.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c
b/drivers/media
.
Suggested-by: Robin Murphy
Signed-off-by: Maxime Ripard
---
drivers/soc/sunxi/Kconfig | 8 ++
drivers/soc/sunxi/Makefile | 1 +
drivers/soc/sunxi/sunxi_mbus.c | 132 +
3 files changed, 141 insertions(+)
create mode 100644 drivers/soc/sunxi/sunxi_mbus.c
Now that the MBUS quirks are applied by our global notifier, we can
remove them from Cedrus. Since the only quirk was whether or not we had
to apply that DMA quirk, we can also remove the quirks infrastructure.
Suggested-by: Christoph Hellwig
Signed-off-by: Maxime Ripard
---
drivers/staging
Now that the MBUS quirks are applied by our global notifier, we can
remove them from our DRM driver.
Suggested-by: Christoph Hellwig
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 19 ---
1 file changed, 19 deletions(-)
diff --git a/drivers/gpu/drm
On Fri, Nov 06, 2020 at 10:10:10AM +0800, Chen-Yu Tsai wrote:
> On Fri, Nov 6, 2020 at 10:03 AM Yu-Tung Chang wrote:
> >
> > Maxime Ripard 于2020年11月6日周五 上午1:10写道：
> > >
> > > On Wed, Nov 04, 2020 at 04:07:48PM +0800, Yu-Tung Chang wrote:
> > > > >
On Thu, Nov 05, 2020 at 09:20:55PM -0600, Samuel Holland wrote:
> Instead of duplicating part of the compatible string in the node name,
> use generic names as recommended by (and listed in) section 2.2.2 of the
> Devicetree Specification.
>
> Suggested-by: Maxime Ripard
> Sig
On Thu, Nov 05, 2020 at 01:24:14PM -0800, Eric Anholt wrote:
> On Thu, Nov 5, 2020 at 12:21 PM Deepak R Varma wrote:
> >
> > idr_init() uses base 0 which is an invalid identifier for this driver.
> > The idr_alloc for this driver uses VC4_PERFMONID_MIN as start value for
> > ID range and it is
On Thu, Nov 05, 2020 at 06:32:31PM +, Matteo Scordino wrote:
> The Elimo Engineering Initium is an Open Source Hardware Single Board
> Computer based on the Elimo Impetus SoM.
>
> It is meant as the first development platform for the Impetus, providing
> convenient access to the peripherals
On Wed, Nov 04, 2020 at 04:07:48PM +0800, Yu-Tung Chang wrote:
> > > + {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <_pins>;
> >
> > This should be already set in the DTSI
> >
> uart0 as the debugging interface, uart1 as the external uart port,
> uart3 as the bluetooth.
What I
On Thu, Nov 05, 2020 at 02:49:45PM +, Matteo Scordino wrote:
> The Elimo Engineering Initium is an Open Source Hardware Single Board
> Computer based on the Elimo Impetus SoM.
>
> It is meant as the first development platform for the Impetus, providing
> convenient access to the peripherals
On Wed, Nov 04, 2020 at 11:41:29PM -0600, Samuel Holland wrote:
> This series fixes a couple of small issues with the PinePhone device
> tree, and collects some patches adding support for peripherals that
> recently received driver or DT binding support.
Applied all those patches, thanks!
Maxime
Hi,
On Wed, Nov 04, 2020 at 11:41:33PM -0600, Samuel Holland wrote:
> From: Ondrej Jirman
>
> Pinephone has STK3311-X proximity sensor. Add support for it.
>
> Signed-off-by: Ondrej Jirman
> Signed-off-by: Samuel Holland
> ---
> .../arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 10
On Wed, Nov 04, 2020 at 11:41:34PM -0600, Samuel Holland wrote:
> From: Ondrej Jirman
>
> The PinePhone has a Realtek rtl8723cs WiFi module.
>
> On mainboard revisions 1.0 and 1.1, the reset input is always pulled
> high, so no power sequence is needed. On mainboard revision 1.2, the
> reset
On Tue, Nov 03, 2020 at 04:33:26PM +, Matteo Scordino wrote:
> >
> > > sun8i-t3-cqa3t-bv3.dtb \
> > > sun8i-v3s-licheepi-zero.dtb \
> > > sun8i-v3s-licheepi-zero-dock.dtb \
> > > diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts
> > >
Hi
On Tue, Nov 03, 2020 at 04:28:27PM +, Matteo Scordino wrote:
> --
> Matteo Scordino / Embedded Software Consultant
> Mobile: +44 (0)7463701446
>
> On Mon, 2020-11-02 at 11:05 +0100, Maxime Ripard wrote:
> > Hi!
> >
> > On Fri, Oct 30, 2020 at 11:43:
On Wed, Nov 04, 2020 at 12:34:58PM +0100, Paul Kocialkowski wrote:
> > > + regmap_write(regmap, SUN6I_MIPI_CSI2_CFG_REG,
> > > + SUN6I_MIPI_CSI2_CFG_CHANNEL_MODE(1) |
> > > + SUN6I_MIPI_CSI2_CFG_LANE_COUNT(lanes_count));
> >
> > It's not really clear what the channel is
On Wed, Nov 04, 2020 at 01:38:08PM -0300, Helen Koike wrote:
>
>
> On 11/4/20 8:17 AM, Paul Kocialkowski wrote:
> > Hi,
> >
> > On Mon 02 Nov 20, 10:21, Maxime Ripard wrote:
> >> On Fri, Oct 30, 2020 at 07:45:18PM -0300, Helen Koike wrote:
> >>&
On Wed, Nov 04, 2020 at 11:48:27AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Tue 27 Oct 20, 19:44, Maxime Ripard wrote:
> > On Tue, Oct 27, 2020 at 10:52:21AM +0100, Paul Kocialkowski wrote:
> > > Hi,
> > >
> > > On Mon 26 Oct 20, 17:14, Maxime Ripar
On Wed, Nov 04, 2020 at 10:15:49AM +, Robin Murphy wrote:
> On 2020-11-04 08:14, Maxime Ripard wrote:
> > Hi Christoph,
> >
> > On Tue, Nov 03, 2020 at 10:55:38AM +0100, Christoph Hellwig wrote:
> > > Linux 5.10-rc1 switched from having a single dma offset i
Hi Christoph,
On Tue, Nov 03, 2020 at 10:55:38AM +0100, Christoph Hellwig wrote:
> Linux 5.10-rc1 switched from having a single dma offset in struct device
> to a set of DMA ranges, and introduced a new helper to set them,
> dma_direct_set_offset.
>
> This in fact surfaced that a bunch of
Hi!
On Mon, Nov 02, 2020 at 06:01:57PM +0800, Yu-Tung Chang wrote:
> The NanoPi R1 is a complete open source board developed
> by FriendlyElec for makers, hobbyists, fans and etc.
>
> NanoPi R1 key features
> - Allwinner H3, Quad-core Cortex-A7@1.2GHz
> - 512MB/1GB DDR3 RAM
> - 8GB eMMC
> -
Hi!
On Tue, Nov 03, 2020 at 11:55:08AM +0100, Daniel Vetter wrote:
> On Tue, Nov 03, 2020 at 11:38:32AM +0100, Maxime Ripard wrote:
> > On Tue, Nov 03, 2020 at 11:10:27AM +0100, Thomas Zimmermann wrote:
> > > Hi
> > >
> > > Am 03.11.20 um 10:52 schrieb Maxime
On Tue, Nov 03, 2020 at 11:10:27AM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 03.11.20 um 10:52 schrieb Maxime Ripard:
> > On Tue, Nov 03, 2020 at 10:10:41AM +0800, Tian Tao wrote:
> >> Add new api devm_drm_irq_install() to register interrupts,
> >> no need
On Tue, Nov 03, 2020 at 10:10:41AM +0800, Tian Tao wrote:
> Add new api devm_drm_irq_install() to register interrupts,
> no need to call drm_irq_uninstall() when the drm module is removed.
>
> v2:
> fixed the wrong parameter.
>
> Signed-off-by: Tian Tao
> ---
> drivers/gpu/drm/drm_drv.c | 23
logicvc_layer_buffer_find_setup for specifics.
>
> Version 4 allows configuring each buffer address directly, which
> guarantees that any buffer can be configured.
>
> Signed-off-by: Paul Kocialkowski
> Reviewed-by: Maxime Ripard
There's a bunch of checkpatch issues he
Hi Stephen,
On Tue, Nov 03, 2020 at 11:31:21AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> After merging the drm-misc-fixes tree, today's linux-next build (arm
> multi_v7_defconfig) produced this warning:
>
> drivers/gpu/drm/vc4/vc4_drv.c: In function 'vc4_drm_unbind':
>
On Mon, Nov 02, 2020 at 11:19:29AM -0300, Pablo Greco wrote:
> Ethernet PHY on BananaPi M2 Berry provides RX and TX delays. Fix ethernet
> node to reflect that fact.
>
> Fixes: 27e81e1970a8 ("ARM: dts: sun8i: v40: bananapi-m2-berry: Enable GMAC
> ethernet controller")
> Signed-off-by: Pablo
On Mon, Nov 02, 2020 at 11:19:14AM -0300, Pablo Greco wrote:
> DCDC1 regulator powers many different subsystems. While some of them can
> work at 3.0 V, some of them can not. For example, VCC-HDMI can only work
> between 3.24 V and 3.36 V. According to OS images provided by the board
>
On Mon, Nov 02, 2020 at 11:16:40AM -0300, Pablo Greco wrote:
> The Ethernet PHY on the Bananapi M1 has the RX and TX delays enabled on
> the PHY, using pull-ups on the RXDLY and TXDLY pins.
>
> Fix the phy-mode description to correct reflect this so that the
> implementation doesn't reconfigure
On Mon, Nov 02, 2020 at 11:33:40AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Mon 02 Nov 20, 11:13, Maxime Ripard wrote:
> > On Sat, Oct 31, 2020 at 07:21:36PM +0100, Paul Kocialkowski wrote:
> > > Document the compatible strings for the SL631 Action Camera with IMX179.
On Fri, Oct 30, 2020 at 07:41:21PM +, Mark Brown wrote:
> On Fri, 30 Oct 2020 15:46:33 +0100, Clément Péron wrote:
> > This series add H6 I2S support and the I2S node missing to support
> > HDMI audio in different Allwinner SoC.
> >
> > As we first use some TDM property to make the I2S
Hi,
On Sat, Oct 31, 2020 at 09:34:15PM -0300, Pablo Greco wrote:
> The Ethernet PHY on the Bananapi M1 has the RX and TX delays enabled on
> the PHY, using pull-ups on the RXDLY and TXDLY pins.
>
> Fix the phy-mode description to correct reflect this so that the
> implementation doesn't
On Mon, Nov 02, 2020 at 11:25:22AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Mon 02 Nov 20, 11:12, Maxime Ripard wrote:
> > On Sat, Oct 31, 2020 at 07:21:34PM +0100, Paul Kocialkowski wrote:
> > > The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209.
&
On Fri, Oct 30, 2020 at 06:25:30PM +0100, Jernej Skrabec wrote:
> PineH64 model B contains RTL8723CS wifi+bt combo module.
>
> Since bluetooth support is not yet squared away, only wifi is enabled
> for now.
>
> Acked-by: Chen-Yu Tsai
> Signed-off-by: Jernej Skrabec
Applied, thanks!
Maxime
On Sun, Nov 01, 2020 at 04:27:05PM +0100, Clément Péron wrote:
> On Wed, 30 Sep 2020 at 12:19, Maxime Ripard wrote:
> >
> > On Mon, Sep 28, 2020 at 04:27:42PM +0200, Clément Péron wrote:
> > > On Mon, 28 Sep 2020 at 10:43, Maxime Ripard wrote:
> > > >
> &
On Sat, Oct 31, 2020 at 07:21:37PM +0100, Paul Kocialkowski wrote:
> The SL631 is a family of Allwinner V3 action cameras sold under
> various names, such as SJCAM SJ4000 Air or F60 Action Camera.
>
> Devices in this family share a common board design but can be found
> with different image
On Sat, Oct 31, 2020 at 07:21:36PM +0100, Paul Kocialkowski wrote:
> Document the compatible strings for the SL631 Action Camera with IMX179.
>
> Signed-off-by: Paul Kocialkowski
> ---
> Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff
On Sat, Oct 31, 2020 at 07:21:34PM +0100, Paul Kocialkowski wrote:
> The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209.
> Its address follows the sytsem controller block, which was previously
> incorrectly described as spanning over 0x1000 address bytes.
Is it after, or right
ult, a specific compatible and register description is required
> for the V3s. This was tested with an AXP209 on a V3 board.
>
> Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
Maxime
signature.asc
Description: PGP signature
On Sat, Oct 31, 2020 at 07:21:32PM +0100, Paul Kocialkowski wrote:
> The NMI interrupt controller takes a specific compatible for the V3s.
Why?
> Add it to the device-tree bindings documentation.
>
> Signed-off-by: Paul Kocialkowski
> ---
>
On Sat, Oct 31, 2020 at 07:21:31PM +0100, Paul Kocialkowski wrote:
> I2C1 can be exposed through PB pins in addition to PE pins on the V3s.
> Add the device-tree description for these pins.
>
> Signed-off-by: Paul Kocialkowski
Applied, thanks!
Maxime
signature.asc
Description: PGP signature
On Fri, Oct 30, 2020 at 11:43:25PM +, Matteo Scordino wrote:
> The compatible string in the Pine64 Pincube dts diverges from the ones
> used in other S3 based boards, like the LicheePi and the Elimo Impetus
> and Initium. Discussion on LKML decided the PineCube should align to the
> others.
>
On Fri, Oct 30, 2020 at 11:43:24PM +, Matteo Scordino wrote:
> The Elimo Engineering Initium is an Open Source Hardware Single Board
> Computer based on the Elimo Impetus SoM.
>
> It is meant as the first development platform for the Impetus, providing
> convenient access to the peripherals
Hi!
On Fri, Oct 30, 2020 at 11:43:22PM +, Matteo Scordino wrote:
> The Elimo Engineering Impetus is an Open Source Hardware System-on-Module
> based on the SoChip S3 SoC.
>
> It is meant for integration into carrier boards or, more generally,
> larger designs, and uses an M2 connector to
On Fri, Oct 30, 2020 at 11:43:21PM +, Matteo Scordino wrote:
> The Allwinner V3 and S3 can use PG6/7 as RX/TX for UART1. Since no other
> functions are assigned to those pins, they are a convenient choice for
> a debugging or application UART.
> This is specific to V3/S3 as the V3s's non-BGA
On Fri, Oct 30, 2020 at 11:43:20PM +, Matteo Scordino wrote:
> Add elimo as vendor prefix for dt bindings, since we are adding a dtsi
> for a SoM and a dts for an SBC
>
> Signed-off-by: Matteo Scordino
Applied, thanks!
Maxime
signature.asc
Description: PGP signature
On Sat, Oct 31, 2020 at 07:21:29PM +0100, Paul Kocialkowski wrote:
> The Allwinner V3 SoC shares the same base as the V3s but comes with
> extra pins and features available. As a result, it has its dedicated
> compatible string (already used in device trees), which is added here.
>
>
On Sun, Nov 01, 2020 at 08:26:09AM +0100, Jernej Skrabec wrote:
> RX/TX delay on OrangePi One Plus board is set on PHY. Reflect that in
> ethernet node.
>
> Fixes: 7ee32a17e0d6 ("arm64: dts: allwinner: h6: orangepi-one-plus: Enable
> ethernet")
> Signed-off-by: Jernej Skrabec
Applied. It's not
On Fri, Oct 30, 2020 at 07:45:18PM -0300, Helen Koike wrote:
> On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller
> > found on Allwinner SoCs such as the A31 and V3/V3s.
> >
> > It is a standalone block, connected to the CSI
Hi
On Fri, Oct 30, 2020 at 07:44:28PM -0300, Helen Koike wrote:
> On thing that is confusing me is the name csi2 with csi (that makes me
> think of csi vesun6i-csirsion one, which is not the case), I would
> rename it to sun6i-video (or maybe it is just me who gets confused).
>
> I know this
ght) channel width.
> I2S/Left-Justified/Right-Justified Mode: Number of BCLKs within each
> individual channel width(Left or Right)
>
> Fix this by using the same formula as the I2S mode.
>
> Fixes: 7ae7834ec446 ("ASoC: sun4i-i2s: Add support for DSP formats")
> Signe
Hi!
On Fri, Oct 30, 2020 at 12:06:10PM +0100, Hans Verkuil wrote:
> Maxime,
>
> Are you OK with this series? It looks good to me.
I am, you can take it. I'll merge the dt patches through arm-soc
Thanks!
Maxime
signature.asc
Description: PGP signature
Hi,
On Tue, Oct 27, 2020 at 04:48:03PM +0800, Yu-Tung Chang wrote:
> The NanoPi R1 is a complete open source board developed
> by FriendlyElec for makers, hobbyists, fans and etc.
>
> NanoPi R1 key features
> - Allwinner H3, Quad-core Cortex-A7@1.2GHz
> - 512MB/1GB DDR3 RAM
> - 8GB eMMC
> -
Hi,
On Thu, Oct 29, 2020 at 02:19:59AM +, Matteo Scordino wrote:
> Document board compatible names for Elimo Engineering Impetus and Initium
>
> Signed-off-by: Matteo Scordino
> ---
> Documentation/devicetree/bindings/arm/sunxi.yaml | 10 ++
> 1 file changed, 10 insertions(+)
>
>
On Wed, Oct 28, 2020 at 12:58:17PM +0100, Nenad Peric wrote:
> RX and TX delay are provided by ethernet PHY. Reflect that in ethernet
> node.
>
> Fixes: 44a94c7ef989 ("arm64: dts: allwinner: H5: Restore EMAC changes")
> Signed-off-by: Nenad Peric
Applied, thanks!
Maxime
signature.asc
301 - 400 of 12711 matches
Mail list logo
