On Fri, 2020-07-10 at 10:52 +0530, Pratik Rajesh Sampat wrote:
> Additional registers DAWR0, DAWRX0 may be lost on Power 10 for
> stop levels < 4.
> Therefore save the values of these SPRs before entering a "stop"
> state and restore their values on wakeup.
>
> Signed-off-by: Pratik Rajesh Sampat
The Linux kernel for powerpc since v4.15 has a bug in it's TM handling during
interrupts where any user can read the FP/VMX registers of a difference user's
process. Users of TM + FP/VMX can also experience corruption of their FP/VMX
state.
To trigger the bug, a process starts a transaction with F
The Linux kernel for powerpc since v4.12 has a bug in it's TM handling where any
user can read the FP/VMX registers of a difference user's process. Users of TM +
FP/VMX can also experience corruption of their FP/VMX state.
To trigger the bug, a process starts a transaction and reads a FP/VMX regis
The Linux kernel for powerpc since v3.9 has a bug in the TM handling where any
unprivileged local user may crash the operating system.
This bug affects machines using 64-bit CPUs where Transactional Memory (TM) is
not present or has been disabled (see below for more details on affected CPUs).
To
On Tue, 2019-06-18 at 09:57 +0530, Ravi Bangoria wrote:
> Watchpoint match range is always doubleword(8 bytes) aligned on
> powerpc. If the given range is crossing doubleword boundary, we
> need to increase the length such that next doubleword also get
> covered. Ex,
>
> address len =
On Tue, 2019-06-18 at 08:01 +0200, Christophe Leroy wrote:
>
> Le 18/06/2019 à 06:27, Ravi Bangoria a écrit :
> > patch 1-3: Code refactor
> > patch 4: Speedup disabling breakpoint
> > patch 5: Fix length calculation for unaligned targets
>
> While you are playing with hw breakpoints, did you hav
On Tue, 2019-06-18 at 09:57 +0530, Ravi Bangoria wrote:
> Directly setting dawr and dawrx with 0 should be enough to
> disable watchpoint. No need to reset individual bits in
> variable and then set in hw.
This seems like a pointless optimisation to me.
I'm all for adding more code/complexity if
This is going to collide with this patch
https://patchwork.ozlabs.org/patch/1109594/
Mikey
On Tue, 2019-06-18 at 09:57 +0530, Ravi Bangoria wrote:
> Remove unnecessary comments. Code itself is self explanatory.
> And, ISA already talks about MRD field. I Don't think we need
> to re-describe it.
> Subject: Powerpc/hw-breakpoint: Replace stale do_dabr() with do_break()
Can you add the word "comment" to this subject. Currently it implies there are
code changes here.
Mikey
On Tue, 2019-06-18 at 09:57 +0530, Ravi Bangoria wrote:
> do_dabr() was renamed with do_break() long ago. But I still
On Thu, 2019-06-06 at 12:59 +0530, Ravi Bangoria wrote:
> Powerpc hw triggers watchpoint before executing the instruction.
> To make trigger-after-execute behavior, kernel emulates the
> instruction. If the instruction is 'load something into non-
> volatile register', exception handler should rest
On Tue, 2018-07-24 at 16:27 -0300, Murilo Opsfelder Araujo wrote:
> Hi, everyone.
>
> This series was inspired by the need to modernize and display more
> informative messages about unhandled signals.
>
> The "unhandled signal NN" is not very informative. We thought it would
> be helpful adding
On Wed, 2018-07-18 at 13:42 +0530, Gautham R Shenoy wrote:
> Hello Mikey,
>
> On Wed, Jul 18, 2018 at 09:24:19AM +1000, Michael Neuling wrote:
> >
> > > DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
> > > diff --git a/arch/powerpc/kernel/idle_book3s.S
> >
On Fri, 2018-05-11 at 16:47 +0530, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> Each of the SMT4 cores forming a fused-core are more or less
> independent units. Thus when multiple tasks are scheduled to run on
> the fused core, we get the best performance when the tasks are spread
>
Thanks for posting this... A couple of comments below.
On Fri, 2018-05-11 at 16:47 +0530, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> A pair of IBM POWER9 SMT4 cores can be fused together to form a
> big-core with 8 SMT threads. This can be discovered via the
> "ibm,thread-groups" C
+0x124/0x170
[c00ff50f3dc0] c008fed0 kthread+0x14c/0x154
[c00ff50f3e30] c000b594 ret_from_kernel_thread+0x5c/0xc8
This fixes the NULL ptr deref.
Signed-off-by: Michael Neuling
---
drivers/nvme/host/pci.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/nvme
@ -1924,6 +1987,7 @@ struct ppc_emulated ppc_emulated = {
> WARN_EMULATED_SETUP(mfdscr),
> WARN_EMULATED_SETUP(mtdscr),
> WARN_EMULATED_SETUP(lq_stq),
> + WARN_EMULATED_SETUP(paste),
You'll need to rebase this on powerpc/next as this has changed upstream.
Mikey
gt; vas_paste_crb() calls in drivers/crypto/nx/nx-842-powernv.c.
> See also PATCH 10/10.
>
> Git Tree:
>
> https://github.com/sukadev/linux/
> Branch: vas-kern-v8
>
> Thanks to input from Ben Herrenschmidt, Michael Neuling, Michael Ellerm
kernel.
> >
> >
> > Mikulas reported he's able to trigger the same crash on Linux 4.10:
> > https://www.spinics.net/lists/kernel/msg2440637.html
> > https://lists.gt.net/linux/kernel/2664604?search_string=ldisc%20reopened;#26
> > 64604
> >
> >
On Tue, 2017-08-08 at 16:07 -0700, Sukadev Bhattiprolu wrote:
> Document the usage of the VAS Fast thread-wakeup API.
>
> Thanks for input/comments from Benjamin Herrenschmidt, Michael Neuling,
> Michael Ellerman, Robert Blackmore, Ian Munsie, Haren Myneni, Paul Mackerras.
>
On Tue, 2017-08-08 at 16:06 -0700, Sukadev Bhattiprolu wrote:
> We need the SPRN_TIDR to bet set for use with fast thread-wakeup
> (core-to-core wakeup). Each thread in a process needs to have a
> unique id within the process but as explained below, for now, we
> assign globally unique thread ids
On Wed, 2017-04-12 at 17:16 +0530, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> The idle-exit code assumes that if Timebase is not lost, then neither
> are the per-core hypervisor resources lost.
Double negative! How about:
The idle-exit code assumes that if the timebase is restor
On Wed, 2017-04-12 at 17:16 +0530, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> This patch ensures that POWER8 and POWER9 processors use the correct
> value of IDLE_THREAD_BITS as POWER8 has 8 threads per core and hence
> the IDLE_THREAD_BITS should be 0xFF while POWER9 has only 4 thr
On Thu, 2017-04-13 at 14:12 +1000, Benjamin Herrenschmidt wrote:
> On Thu, 2017-04-13 at 09:28 +0530, Aneesh Kumar K.V wrote:
> > > #endif
> > > mtctr r12
> > > bctrl
> > > +/*
> > > + * cur_cpu_spec->cpu_restore would restore LPCR to a
> > > + * sane value that is set at early bo
Wang,
Applying this, with the other one on top and it doesn't fix the problem (applied
on next-20170405). I tried each patch by itself, with the same bad result.
Thanks for the help but the backtrace is the same:
Unable to handle kernel paging request for data at address 0x2260
Faulting inst
Al,
On Fri, 2017-04-07 at 05:12 +0100, Al Viro wrote:
> On Fri, Apr 07, 2017 at 01:50:53PM +1000, Michael Neuling wrote:
>
> > diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
> > index bdf0e6e899..a2a9832a42 100644
> > --- a/drivers/tty/n_tty.c
>
Cc: [4.10+]
Signed-off-by: Michael Neuling
---
drivers/tty/n_tty.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
index bdf0e6e899..a2a9832a42 100644
--- a/drivers/tty/n_tty.c
+++ b/drivers/tty/n_tty.c
@@ -1668,11 +1668,17 @@ sta
> down_read(&tty->termios_rwsem);
>
> + ldata = tty->disc_data;
I did try just that alone and it didn't help.
Mikey
--------
>From 75c2a0369450692946ca8cc7ac148a98deaecd2a Mon Sep 17 00:00:00
> > If anyone has an idea, I'm happy to try a patch.
>
> Can you try this one [1].
Rob, I'm still hitting it when I apply that on next-20170405. Crash below..
Any other clues?
[ 229.422825] Unable to handle kernel paging request for data at address
0x2260
[ 229.423681] Faulting instruct
Hi all,
We are seeing the following crash (in linux-next but has been around since at
least v4.10).
[ 417.514499] Unable to handle kernel paging request for data at address
0x2260
[ 417.515361] Faulting instruction address: 0xc06fad80
cpu 0x15: Vector: 300 (Data Access) at [c0
On Mon, 2017-03-20 at 10:26 +0100, Dmitry Vyukov wrote:
> On Mon, Mar 20, 2017 at 10:21 AM, Dmitry Vyukov wrote:
> > On Mon, Mar 20, 2017 at 3:28 AM, Stephen Rothwell
> > wrote:
> > > Hi Greg,
> > >
> > > Today's linux-next merge of the tty tree got a conflict in:
> > >
> > > drivers/tty/tty_
stroy ldisc instance on hangup")
Reported-by: Mikulas Patocka
Signed-off-by: Peter Hurley
Signed-off-by: Michael Neuling
---
gregkh, can you take this? It never made it upstream and Peter Hurley
doesn't seem to be responding to email since mid 2016.
I'm reposting this from https://
> This patch works, I've had no tty crashes since applying it.
>
> I've seen that you haven't sent this patch yet to Linux-4.7-rc and
> Linux-4.6-stable. Will you? Or did you create a different patch?
We are hitting this now on powerpc. This patch never seemed to make
it upstream (drivers/tty/tty
t;
> Signed-off-by: Aneesh Kumar K.V
FWIW this is pretty simple and helps with us in powerpc...
Acked-By: Michael Neuling
> ---
> include/asm-generic/pgtable.h | 16
> mm/huge_memory.c | 4 ++--
> mm/memory.c | 2 +-
> mm/mpro
, we will
> clear
> the _PAGE_PRIVILEGED bit. The pte still remain non-accessible from both user
> and kernel.
>
> Signed-off-by: Aneesh Kumar K.V
FWIW I've tested this, so:
Acked-By: Michael Neuling
> ---
> arch/powerpc/include/asm/book3s/64/mmu-hash.h | 3 +++
&g
figuration... FWIW
Acked-By: Michael Neuling
> ---
> arch/powerpc/kernel/cpu_setup_power.S | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S
> b/arch/powerpc/kernel/cpu_setup_power.S
> index 52ff3f0..37ad045 100644
> ---
On Wed, 2016-11-23 at 10:30 +1100, Michael Ellerman wrote:
> "Gautham R. Shenoy" writes:
>
> > From: "Gautham R. Shenoy"
> >
> > Ensure that PSSCR is set to a safe value corresponding to no
> > state-loss each time a POWER9 CPU comes online.
>
> Is this a bug fix? I can't tell from the change
> > >
> > > @@ -439,7 +540,18 @@ timebase_resync:
> > > */
> > > bne cr4,clear_lock
> > >
> > > - /* Restore per core state */
> > > + /*
> > > + * First thread in the core to wake up and its waking up
> > > with
> > > + * complete hypervisor state loss. Restore per core
> > > hyperv
Except for the issue with patch 7 I've already commented on the rest of
this series is good with me. FWIW:
Acked-by: Michael Neuling
Thanks.
On Fri, 2016-07-08 at 02:17 +0530, Shreyas B. Prabhu wrote:
> POWER ISA v3 defines a new idle processor core mechanism. In summary,
&
> /*
> @@ -230,7 +238,7 @@ static int powernv_add_idle_states(void)
> strcpy(powernv_states[nr_idle_states].desc,
> "FastSleep");
> powernv_states[nr_idle_states].flags =
> CPUIDLE_FLAG_TIMER_STOP;
> powernv_states[nr
> diff --git a/arch/powerpc/include/asm/cpuidle.h
> b/arch/powerpc/include/asm/cpuidle.h
> index d2f99ca..3d7fc06 100644
> --- a/arch/powerpc/include/asm/cpuidle.h
> +++ b/arch/powerpc/include/asm/cpuidle.h
> @@ -13,6 +13,8 @@
> #ifndef __ASSEMBLY__
> extern u32 pnv_fastsleep_workaround_at_entr
es at boot. It doesn't need to wait for the
> rest of the series.
Acked-by: Michael Neuling
For the same reason. Without this we need powersave=off on the cmdline on
POWER9.
Mikey
>
> Cheers,
> Ben.
>
> >
> > ---
> > - No changes since v1
> >
> >
> > > +#define OPAL_PM_TIMEBASE_STOP0x0002
> > > +#define OPAL_PM_LOSE_HYP_CONTEXT 0x2000
> > > +#define OPAL_PM_LOSE_FULL_CONTEXT0x4000
> > > #define OPAL_PM_NAP_ENABLED 0x0001
> > > #define OPAL_PM_SLEEP_ENABLED0x0002
> > > #def
On Wed, 2016-06-08 at 22:31 +0530, Shreyas B Prabhu wrote:
> Hi Ben,
>
> Sorry for the delayed response.
>
> On 06/06/2016 03:58 AM, Benjamin Herrenschmidt wrote:
> >
> > On Thu, 2016-06-02 at 07:38 -0500, Shreyas B. Prabhu wrote:
> > >
> > > @@ -61,8 +72,13 @@ save_sprs_to_stack:
> > >
On Thu, 2016-05-12 at 13:33 +0200, Peter Zijlstra wrote:
> On Thu, May 12, 2016 at 09:07:52PM +1000, Michael Neuling wrote:
> >
> > On Thu, 2016-05-12 at 07:07 +0200, Peter Zijlstra wrote:
> >
> > >
> > > But as per the above, Power7 and Power8 have expl
On Thu, 2016-05-12 at 07:07 +0200, Peter Zijlstra wrote:
> On Thu, May 12, 2016 at 12:05:37PM +1000, Michael Neuling wrote:
> >
> > On Wed, 2016-05-11 at 20:24 +0200, Peter Zijlstra wrote:
> > >
> > > On Wed, May 11, 2016 at 02:33:45PM +0200, Peter Zijlstra wro
On Wed, 2016-05-11 at 20:24 +0200, Peter Zijlstra wrote:
> On Wed, May 11, 2016 at 02:33:45PM +0200, Peter Zijlstra wrote:
> >
> > Hmm, PPC folks; what does your topology look like?
> >
> > Currently your sched_domain_topology, as per arch/powerpc/kernel/smp.c
> > seems to suggest your cores do n
On Tue, 2016-05-03 at 08:32 +0200, Jiri Slaby wrote:
> On 01/27/2016, 07:12 PM, Greg Kroah-Hartman wrote:
> >
> > 4.4-stable review patch. If anyone has any objections, please let me
> > know.
> >
> > ----------
> >
>
> diff --git a/arch/powerpc/include/asm/cputable.h
> b/arch/powerpc/include/asm/cputable.h
> index df4fb5f..a4739a1 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -205,6 +205,7 @@ enum {
> #define CPU_FTR_DABRX
> LONG_A
On Wed, 2016-03-23 at 17:04 +0530, Srikar Dronamraju wrote:
> If asymmetric packing is used when target cpu is busy,
> update_sd_pick_busiest(), can select a lightly loaded cpu.
> find_busiest_group() has checks to ensure asym packing is only used
> when target cpu is not busy. However it may not
On Fri, 2016-03-18 at 15:04 +1100, Michael Neuling wrote:
> On Wed, 2016-02-03 at 01:11 +0530, Shilpasri G Bhat wrote:
>
> > cpu_to_chip_id() does a DT walk through to find out the chip id by
> > taking a contended device tree lock. This adds an unnecessary
> > overhe
On Wed, 2016-02-03 at 01:11 +0530, Shilpasri G Bhat wrote:
> cpu_to_chip_id() does a DT walk through to find out the chip id by
> taking a contended device tree lock. This adds an unnecessary overhead
> in a hot path. So instead of calling cpu_to_chip_id() everytime cache
> the chip ids for all co
On Sat, 2016-03-19 at 09:37 +1100, Benjamin Herrenschmidt wrote:
> On Fri, 2016-03-18 at 15:04 +1100, Michael Neuling wrote:
> >
> > static int nr_chips;
> > +static DEFINE_PER_CPU(unsigned int, chip_id);
> >
> > /*
> > * Note: The set of pstat
On Wed, 2016-03-09 at 20:07 +0530, Vaibhav Jain wrote:
> Hi Ian,
>
> Sorry for getting into this discussion late. I have few suggestions.
>
> Ian Munsie writes:
> >
> > diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig
> > index 8756d06..560412c 100644
> > --- a/drivers/misc/cxl/
ffset after any reads to a read/write offset.
>
> Due to these constraints, this functionality must be explicitly
> requested by userspace when starting the context by passing in the
> CXL_START_WORK_ERR_FF flag.
>
> Signed-off-by: Ian Munsie
Acked-by: Michael Neuling
On Mon, 2015-07-27 at 00:18 +0300, Vladimir Zapolskiy wrote:
> The sanity checks for overflow are not needed, because this is done on
> caller side in fs/sysfs/file.c
>
> Signed-off-by: Vladimir Zapolskiy
> Cc: linuxppc-...@lists.ozlabs.org
> Cc: Ian Munsie
> Cc: Micha
t performs this transformation
> is as follows:
>
> @@
> identifier a;
> declarer name DEFINE_PCI_DEVICE_TABLE;
> initializer i;
> @@
> - DEFINE_PCI_DEVICE_TABLE(a)
> + const struct pci_device_id a[]
> = i;
>
> Signed-off-by: Vaishali Thakkar
Looks good, thanks!
Ack
On Mon, 2015-06-29 at 16:05 +0530, Maninder Singh wrote:
> static Anlaysis detected below error:-
> (error) Possible null pointer dereference: phb
>
> So, Use phb after NULL check.
>
> Signed-off-by: Maninder Singh
Thanks, looks good.
Acked-By: Michael Neuling
> --
Looks good and it's boots for me.
Signed-off-by: Michael Neuling
> Signed-off-by: Shreyas B. Prabhu
> ---
> arch/powerpc/sysdev/xics/icp-native.c | 14 +-
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/arch/powerpc/sysdev/xics/icp-native
On Tue, 2015-05-05 at 21:12 +1000, Michael Ellerman wrote:
> As soon as we know the name of the cpu we're on, add it to the dump
> stack arch description, which is printed in case of an oops.
>
> Signed-off-by: Michael Ellerman
> ---
> arch/powerpc/kernel/cputable.c | 3 +++
> 1 file changed, 3
On Wed, 2015-04-08 at 19:50 +0200, Ulrich Weigand wrote:
> Anshuman Khandual wrote on 23.03.2015
> 11:34:30:
>
> > > With that in mind, do we have a way to set the top 32bits of the MSR
> > > (which contain the TM bits) when ptracing 32 bit processes? I can't
> > > find anything like that in thi
On Thu, 2015-03-19 at 09:45 +1100, Michael Neuling wrote:
> On Wed, 2015-03-18 at 13:53 +0100, Ulrich Weigand wrote:
> > Michael Neuling wrote on 23.02.2015 05:51:50:
> >
> > > Sorry for the slow response.
> >
> > Same here :-(
>
> I'm goin
On Wed, 2015-03-18 at 13:53 +0100, Ulrich Weigand wrote:
> Michael Neuling wrote on 23.02.2015 05:51:50:
>
> > Sorry for the slow response.
>
> Same here :-(
I'm going to break the cycle and respond in a few hours :-)
> > I think what you're proposing wit
Uli,
Sorry for the slow response.
> Michael Neuling wrote on 28.01.2015 05:28:09:
>
> > Sorry, I'm rethinking this as we didn't consider user suspended
> > transactions.
> >
> > It makes sense for normal transactions but for user suspended
> > tr
On Fri, 2015-01-23 at 08:44 +1100, Michael Neuling wrote:
> > > > Inside transaction both running and check pointed values can be
> > > > probed independently.
> > >
> > > Yep, that's the idea, although setting the running values won't change
> > > Inside transaction both running and check pointed values can be
> > > probed independently.
> >
> > Yep, that's the idea, although setting the running values won't change
> > anything since the the translation is already doomed and will abort once
> > the cpu starts executing it.
>
> So this
On Thu, 2015-01-01 at 13:38 +0530, Anshuman Khandual wrote:
> On 12/20/2014 12:58 AM, Edjunior Barbosa Machado wrote:
> > On 12/08/2014 08:08 AM, Anshuman Khandual wrote:
> >> On 12/03/2014 12:18 PM, Anshuman Khandual wrote:
> >>> On 12/03/2014 10:52 AM, Michael Ellerman wrote:
> On Tue, 2014-
ninitialized variable: hwirq
>
> Commit 80fa93fce37d ("cxl: Name interrupts in /proc/interrupt")
> introduced this error.
>
> This is a simple fix that removes the redundant increment.
>
> Signed-off-by: Colin Ian King
Thanks. Looks good.
Acked-By: Michael Neulin
> Remove the function mmio_size_show() that is not used anywhere.
Did you compile check this patch?
drivers/misc/cxl/sysfs.c:291:74: error: ‘mmio_size_show’ undeclared here (not
in a function)
It's used here:
static struct device_attribute afu_attrs[] = {
__ATTR_RO(mmi
igned-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/copro.h | 7 +
arch/powerpc/include/asm/mmu-hash64.h | 7 +
arch/powerpc/mm/copro_fault.c | 46
arch/powerpc/mm/slb.c | 3 --
arch/po
-by: Michael Neuling
---
arch/powerpc/Kconfig | 4
arch/powerpc/include/asm/copro.h | 16
arch/powerpc/include/asm/spu.h | 5 ++---
arch/powerpc/mm/Makefile
From: Ian Munsie
This moves spu_flush_all_slbs() into a generic call copro_flush_all_slbs().
This will be useful when we add cxl which also needs a similar SLB flush call.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/copro.h | 6 ++
arch/powerpc
when SLBs are invalidated. This ensures any
corresponding SLBs in cxl are also invalidated at the same time. This is
required for segment demotion.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/mm/copro_fault.c| 2 ++
arch/powerpc/mm/hash_native_64.c | 6 +-
2
in
Documentation/powerpc/cxl.txt.
It also adds this new userspace header file to Kbuild so it's exported when
doing "make headers_installs".
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
include/uapi/Kbuild | 1 +
include/uapi/misc/Kbuild | 2 ++
include/
CONFIG_SPU_BASE.
This adds a cxl_slbia() call (similar to spu_flush_all_slbs()) which checks if
the cxl module is loaded and in use, returning immediately if it is not. If it
is in use it calls into the cxl SLB invalidation code.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc
From: Ian Munsie
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/cxl/Kconfig | 17 +
drivers/misc/cxl/Makefile | 2 ++
2 files changed, 19 insertions(+)
diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig
index 5cdd319..a990b39 100644
.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/cxl/context.c | 193 +
drivers/misc/cxl/cxl.h | 629
drivers/misc/cxl/debugfs.c | 132 ++
drivers/misc/cxl/fault.c | 291 +
drivers/misc/cxl/file.c| 508
From: Ian Munsie
This documentation gives an overview of the hardware architecture, userspace
APIs via /dev/cxl/afuM.N and the syfs files. It also adds a MAINTAINERS file
entry for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
Documentation/ABI/testing/sysfs-class-cxl
SE is not enabled.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
include/misc/cxl.h | 48
1 file changed, 48 insertions(+)
create mode 100644 include/misc/cxl.h
diff --git a/include/misc/cxl.h b/include/misc/cxl.h
new file mode 1
be careful here as the current hash_page() assumes current in a few
places.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/mmu-hash64.h | 1 +
arch/powerpc/mm/hash_utils_64.c | 24 +---
2 files changed, 18 insertions(+), 7
From: Ian Munsie
This adds a number of functions for allocating IRQs under powernv PCIe for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/pnv-pci.h| 31 ++
arch/powerpc/platforms/powernv/pci-ioda.c | 154
From: Ian Munsie
Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful so
split it out.
This will be used by some of the cxl PCIe code later.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/platforms/powernv/pci-ioda.c | 42
From: Ian Munsie
Export mmu_kernel_ssize and mmu_linear_psize. These are needed by the cxl
driver which has it's own MMU. To setup the MMU cxl needs access to these.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/mm/hash_utils_64.c | 2 ++
1 file chang
ement though.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/sysdev/msi_bitmap.c | 36 +---
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/sysdev/msi_bitmap.c b/arch/powerpc/sysdev/msi_bitmap.c
index 2f
This is the latest version of the cxl driver. Change log below:
v4:
- Updates based on comments from mpe (offline and online).
- Refactor the sstp lock to be an entry lock.
- Fixed error paths on new status_mutex in start_work
- added some missing include files
- moved associating pid/mm fro
From: Ian Munsie
This adds the OPAL call to change a PHB into cxl mode.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/opal.h| 2 ++
arch/powerpc/platforms/powernv/opal-wrappers.S | 1 +
2 files changed, 3 insertions(+)
diff --git a
On Wed, 2014-10-08 at 09:59 +1100, Michael Ellerman wrote:
> On Tue, 2014-07-10 at 10:48:14 UTC, Michael Neuling wrote:
> > From: Ian Munsie
> >
> > This adds a number of functions for allocating IRQs under powernv PCIe for
> > cxl.
> >
> > diff --g
On Wed, 2014-10-08 at 10:04 +1100, Michael Ellerman wrote:
> On Tue, 2014-07-10 at 10:48:18 UTC, Michael Neuling wrote:
> > From: Ian Munsie
> >
> > This adds the base cxl support that needs to be build into the kernel to use
> > cxl as a module. This is needed so t
> > +int copro_data_segment(struct mm_struct *mm, u64 ea, u64 *esid, u64 *vsid);
>
> This function is otherwise not included in this patch, so it should
> probably be removed (as the next patch removes it anyway).
Yeah, looks like I screwed it up slightly in the packing of these
patches.
Thanks
segment handling which Cell didn't have.
This also moves the internal struct spu_slb to a generic struct copro_slb which
is now used in the spu and copro code. We use this new struct instead of the
us passing around esid and vsid parameters.
Signed-off-by: Ian Munsie
Signed-off-by: Mi
-by: Michael Neuling
---
arch/powerpc/Kconfig | 4
arch/powerpc/include/asm/copro.h | 18 ++
arch/powerpc/include/asm/spu.h | 5 ++---
arch/powerpc/mm/Makefile | 1
ement though.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/sysdev/msi_bitmap.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/sysdev/msi_bitmap.c b/arch/powerpc/sysdev/msi_bitmap.c
index 2ff6302..56
From: Ian Munsie
This moves spu_flush_all_slbs() into a generic call copro_flush_all_slbs().
This will be useful when we add cxl which also needs a similar SLB flush call.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/copro.h | 6 ++
arch/powerpc
From: Ian Munsie
Export mmu_kernel_ssize and mmu_linear_psize. These are needed by the cxl
driver which has it's own MMU. To setup the MMU cxl need access to these.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/mm/hash_utils_64.c | 2 ++
1 file chang
d-off-by: Michael Neuling
---
arch/powerpc/mm/copro_fault.c| 2 ++
arch/powerpc/mm/hash_native_64.c | 6 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/copro_fault.c b/arch/powerpc/mm/copro_fault.c
index 222ef9b..55791fc 100644
--- a/arch/powerpc/mm/copro_fa
From: Ian Munsie
Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful so
split it out.
This will be used by some of the cxl PCIe code later.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/platforms/powernv/pci-ioda.c | 42
From: Ian Munsie
This adds a number of functions for allocating IRQs under powernv PCIe for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/pnv-pci.h| 27 ++
arch/powerpc/platforms/powernv/pci-ioda.c | 153
From: Ian Munsie
This adds the OPAL call to change a PHB into cxl mode.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
arch/powerpc/include/asm/opal.h| 2 ++
arch/powerpc/platforms/powernv/opal-wrappers.S | 1 +
2 files changed, 3 insertions(+)
diff --git a
.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/cxl/context.c | 173
drivers/misc/cxl/cxl.h | 622
drivers/misc/cxl/debugfs.c | 112 +
drivers/misc/cxl/fault.c | 299 ++
drivers/misc/cxl/file.c| 493
From: Ian Munsie
This documentation gives an overview of the hardware architecture, userspace
APIs via /dev/cxl/afu0.0 and the syfs files. It also adds a MAINTAINERS file
entry for cxl.
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
Documentation/ABI/testing/sysfs-class-cxl
From: Ian Munsie
Signed-off-by: Ian Munsie
Signed-off-by: Michael Neuling
---
drivers/misc/cxl/Kconfig | 10 ++
drivers/misc/cxl/Makefile | 2 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/misc/cxl/Kconfig b/drivers/misc/cxl/Kconfig
index 5cdd319..585d6e3 100644
--- a
1 - 100 of 293 matches
Mail list logo
