[PATCH V4 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

From: Mirza Krak <mirza.k...@gmail.com> Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which is max rate. The maximum rate value of 127 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler &

[PATCH V4 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

From: Mirza Krak Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which is max rate. The maximum rate value of 127 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory

[PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

From: Mirza Krak <mirza.k...@gmail.com> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which is max rate. The maximum rate value of 92 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler &

[PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

From: Mirza Krak Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which is max rate. The maximum rate value of 92 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory

[PATCH V4 6/6] bus: Add support for Tegra Generic Memory Interface

From: Mirza Krak <mirza.k...@gmail.com> The Generic Memory Interface bus can be used to connect high-speed devices such as NOR flash, FPGAs, DSPs... Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswi...@toradex.com> Tested-on: Colibri T2

[PATCH V4 3/6] dt/bindings: Add bindings for Tegra GMI controller

From: Mirza Krak <mirza.k...@gmail.com> Document the devicetree bindings for the Generic Memory Interface (GMI) bus driver found on Tegra SOCs. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswi...@toradex.com> Tested-on: Colibri T20/T30

[PATCH V4 6/6] bus: Add support for Tegra Generic Memory Interface

From: Mirza Krak The Generic Memory Interface bus can be used to connect high-speed devices such as NOR flash, FPGAs, DSPs... Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board --- Changes in v2: - Fixed some checkpatch

[PATCH V4 3/6] dt/bindings: Add bindings for Tegra GMI controller

From: Mirza Krak Document the devicetree bindings for the Generic Memory Interface (GMI) bus driver found on Tegra SOCs. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Acked-by: Rob Herring --- Changes in v2: - Updated

[PATCH V4 5/6] ARM: tegra: Add Tegra20 GMI support

From: Mirza Krak <mirza.k...@gmail.com> Add a device node for the GMI controller found on Tegra20. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswi...@toradex.com> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Ac

[PATCH V4 5/6] ARM: tegra: Add Tegra20 GMI support

From: Mirza Krak Add a device node for the GMI controller found on Tegra20. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Acked-by: Jon Hunter --- Changes in v2: - added address-cells, size-cells and ranges properties

[PATCH V4 0/6] Add support for Tegra GMI bus controller

From: Mirza Krak <mirza.k...@hostmobility.com> Hi. This patch series adds support for the Tegra GMI bus controller. I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom carrier board which has multiple CAN controllers (SJA1000) connected to the GMI bus. I have re

[PATCH V4 4/6] ARM: tegra: Add Tegra30 GMI support

From: Mirza Krak <mirza.k...@gmail.com> Add a device node for the GMI controller found on Tegra30. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswi...@toradex.com> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Ac

[PATCH V4 0/6] Add support for Tegra GMI bus controller

From: Mirza Krak Hi. This patch series adds support for the Tegra GMI bus controller. I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom carrier board which has multiple CAN controllers (SJA1000) connected to the GMI bus. I have re-based on top of latest tegra/for-next

[PATCH V4 4/6] ARM: tegra: Add Tegra30 GMI support

From: Mirza Krak Add a device node for the GMI controller found on Tegra30. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board Acked-by: Jon Hunter --- Changes in v2: - added address-cells, size-cells and ranges properties

Re: [PATCH V3 6/6] bus: Add support for Tegra Generic Memory Interface

2016-11-03 11:51 GMT+01:00 Jon Hunter <jonath...@nvidia.com>: > > On 27/10/16 15:01, Mirza Krak wrote: >> >> From: Mirza Krak <mirza.k...@gmail.com> >> >> The Generic Memory Interface bus can be used to connect high-speed >> devices such as NOR flash

Re: [PATCH V3 6/6] bus: Add support for Tegra Generic Memory Interface

2016-11-03 11:51 GMT+01:00 Jon Hunter : > > On 27/10/16 15:01, Mirza Krak wrote: >> >> From: Mirza Krak >> >> The Generic Memory Interface bus can be used to connect high-speed >> devices such as NOR flash, FPGAs, DSPs... >> >> Signed-off-by: Mirz

Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

2016-11-03 13:26 GMT+01:00 Mirza Krak <mirza.k...@gmail.com>: > 2016-11-03 11:06 GMT+01:00 Jon Hunter <jonath...@nvidia.com>: >> Hi Mirza, >> >> On 27/10/16 15:01, Mirza Krak wrote: >>> >>> From: Mirza Krak <mirza.k...@gmail.com> >>>

Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

2016-11-03 13:26 GMT+01:00 Mirza Krak : > 2016-11-03 11:06 GMT+01:00 Jon Hunter : >> Hi Mirza, >> >> On 27/10/16 15:01, Mirza Krak wrote: >>> >>> From: Mirza Krak >>> >>> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz wh

Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

2016-11-03 11:06 GMT+01:00 Jon Hunter <jonath...@nvidia.com>: > Hi Mirza, > > On 27/10/16 15:01, Mirza Krak wrote: >> >> From: Mirza Krak <mirza.k...@gmail.com> >> >> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which >>

Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

2016-11-03 11:06 GMT+01:00 Jon Hunter : > Hi Mirza, > > On 27/10/16 15:01, Mirza Krak wrote: >> >> From: Mirza Krak >> >> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which >> is max rate. >> >> The maximum rate value of

Re: [PATCH V3 5/6] ARM: tegra: Add Tegra20 GMI support

m] > [Suggest to use git(>=2.9.0) format-patch --base= (or --base=auto for > convenience) to record what (public, well-known) commit your patch series was > built on] > [Check https://git-scm.com/docs/git-format-patch for more information] > > url: > https://github.co

Re: [PATCH V3 5/6] ARM: tegra: Add Tegra20 GMI support

e git(>=2.9.0) format-patch --base= (or --base=auto for > convenience) to record what (public, well-known) commit your patch series was > built on] > [Check https://git-scm.com/docs/git-format-patch for more information] > > url: > https://github.com/0day-ci/linux/commit

[PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

From: Mirza Krak <mirza.k...@gmail.com> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which is max rate. The maximum rate value of 92 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler &

[PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

From: Mirza Krak Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which is max rate. The maximum rate value of 92 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory

[PATCH V3 5/6] ARM: tegra: Add Tegra20 GMI support

From: Mirza Krak <mirza.k...@gmail.com> Add a device node for the GMI controller found on Tegra20. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswi...@toradex.com> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board

[PATCH V3 5/6] ARM: tegra: Add Tegra20 GMI support

From: Mirza Krak Add a device node for the GMI controller found on Tegra20. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board --- Changes in v2: - added address-cells, size-cells and ranges properties Changes in v3

[PATCH V3 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

From: Mirza Krak <mirza.k...@gmail.com> Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which is max rate. The maximum rate value of 127 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler &

[PATCH V3 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

From: Mirza Krak Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which is max rate. The maximum rate value of 127 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory

[PATCH V3 6/6] bus: Add support for Tegra Generic Memory Interface

From: Mirza Krak <mirza.k...@gmail.com> The Generic Memory Interface bus can be used to connect high-speed devices such as NOR flash, FPGAs, DSPs... Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswi...@toradex.com> Tested-on: Colibri T2

[PATCH V3 6/6] bus: Add support for Tegra Generic Memory Interface

From: Mirza Krak The Generic Memory Interface bus can be used to connect high-speed devices such as NOR flash, FPGAs, DSPs... Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board --- Changes in v2: - Fixed some checkpatch

[PATCH V3 0/6] Add support for Tegra GMI bus controller

From: Mirza Krak <mirza.k...@gmail.com.com> Hi. This patch series adds support for the Tegra GMI bus controller. I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom carrier board which has multiple CAN controllers (SJA1000) connected to the GMI bus. I have re

[PATCH V3 4/6] ARM: tegra: Add Tegra30 GMI support

From: Mirza Krak <mirza.k...@gmail.com> Add a device node for the GMI controller found on Tegra30. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswi...@toradex.com> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board

[PATCH V3 0/6] Add support for Tegra GMI bus controller

From: Mirza Krak Hi. This patch series adds support for the Tegra GMI bus controller. I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom carrier board which has multiple CAN controllers (SJA1000) connected to the GMI bus. I have re-based on top of latest tegra/for-next

[PATCH V3 4/6] ARM: tegra: Add Tegra30 GMI support

From: Mirza Krak Add a device node for the GMI controller found on Tegra30. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board --- Changes in v2: - added address-cells, size-cells and ranges properties Changes in v3

[PATCH V3 3/6] dt/bindings: Add bindings for Tegra GMI controller

From: Mirza Krak <mirza.k...@gmail.com> Document the devicetree bindings for the Generic Memory Interface (GMI) bus driver found on Tegra SOCs. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswi...@toradex.com> Tested-on: Colibri T20/T30

[PATCH V3 3/6] dt/bindings: Add bindings for Tegra GMI controller

From: Mirza Krak Document the devicetree bindings for the Generic Memory Interface (GMI) bus driver found on Tegra SOCs. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board --- Changes in v2: - Updated examples and some

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-09-06 12:32 GMT+02:00 Jon Hunter <jonath...@nvidia.com>: > > On 31/08/16 12:22, Mirza Krak wrote: >> 2016-08-30 19:06 GMT+02:00 Rob Herring <r...@kernel.org>: > > ... > >>>> nvidia,snor-cs = <4>; >>> >&g

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-09-06 12:32 GMT+02:00 Jon Hunter : > > On 31/08/16 12:22, Mirza Krak wrote: >> 2016-08-30 19:06 GMT+02:00 Rob Herring : > > ... > >>>> nvidia,snor-cs = <4>; >>> >>> NAK, no custom CS properties. > > Ok, so ...

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-08-30 19:06 GMT+02:00 Rob Herring <r...@kernel.org>: > On Wed, Aug 24, 2016 at 09:54:47PM +0200, Mirza Krak wrote: >> 2016-08-24 17:56 GMT+02:00 Jon Hunter <jonath...@nvidia.com>: >> + >> >> +Example with two SJA1000 CAN controllers c

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-08-30 19:06 GMT+02:00 Rob Herring : > On Wed, Aug 24, 2016 at 09:54:47PM +0200, Mirza Krak wrote: >> 2016-08-24 17:56 GMT+02:00 Jon Hunter : >> + >> >> +Example with two SJA1000 CAN controllers connected to the GMI bus. We >> >> wrap the >>

Re: [PATCH v2 5/6] ARM: tegra: Add Tegra20 GMI support

2016-08-31 9:18 GMT+02:00 Marcel Ziswiler <marcel.ziswi...@toradex.com>: > On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote: >> >> From: Mirza Krak <mirza.krak-re5jqeeqqe8avxtiumw...@public.gmane.org> >> >> Add a device node for the GMI controller found

Re: [PATCH v2 5/6] ARM: tegra: Add Tegra20 GMI support

2016-08-31 9:18 GMT+02:00 Marcel Ziswiler : > On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote: >> >> From: Mirza Krak >> >> Add a device node for the GMI controller found on Tegra20. >> >> Signed-off-by: Mirza Krak > mane.org> >> --- >

Re: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table]

2016-08-31 9:15 GMT+02:00 Marcel Ziswiler <marcel.ziswi...@toradex.com>: > On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote: >> >> From: Mirza Krak <mirza.krak-re5jqeeqqe8avxtiumw...@public.gmane.org> >> >> Add TEGRA20_CLK_NOR to init tabel and set default

Re: [Fwd: Re: [PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table]

2016-08-31 9:15 GMT+02:00 Marcel Ziswiler : > On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote: >> >> From: Mirza Krak >> >> Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz >> which >> is max rate. > > table ACK > >> >

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-08-30 17:02 GMT+02:00 Marcel Ziswiler <marcel.ziswi...@toradex.com>: > On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote: >> From: Mirza Krak <mirza.k...@gmail.com> >> >> Document the devicetree bindings for the Generic Memory Interface >>

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-08-30 17:02 GMT+02:00 Marcel Ziswiler : > On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote: >> From: Mirza Krak >> >> Document the devicetree bindings for the Generic Memory Interface >> (GMI) >> bus driver found on Tegra SOCs. >> >> Signe

Re: [PATCH v2 0/6] Add support for Tegra GMI bus controller

it. > > On Wed, 2016-08-24 at 15:37 +0200, Mirza Krak wrote: >> From: Mirza Krak <mirza.k...@gmail.com> >> >> Hi. >> >> This is a follow up to my previous RFC to add support for Tegra GMI >> bus >> controller. >> >> I have tested thi

Re: [PATCH v2 0/6] Add support for Tegra GMI bus controller

at 15:37 +0200, Mirza Krak wrote: >> From: Mirza Krak >> >> Hi. >> >> This is a follow up to my previous RFC to add support for Tegra GMI >> bus >> controller. >> >> I have tested this series on a Tegra30 using a Colibri T30 SOM on a >&g

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-08-26 9:25 GMT+02:00 Jon Hunter <jonath...@nvidia.com>: > > On 26/08/16 05:53, Mirza Krak wrote: > > ... > >>> I have an idea which is following: >>> >>> gmi@7009 { >>> status = "okay"; >>> #add

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-08-26 9:25 GMT+02:00 Jon Hunter : > > On 26/08/16 05:53, Mirza Krak wrote: > > ... > >>> I have an idea which is following: >>> >>> gmi@7009 { >>> status = "okay"; >>> #address-cells = <2>; >

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-08-24 21:54 GMT+02:00 Mirza Krak <mirza.k...@gmail.com>: > 2016-08-24 17:56 GMT+02:00 Jon Hunter <jonath...@nvidia.com>: > + >>> +Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap >>> the >>> +controllers with a

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-08-24 21:54 GMT+02:00 Mirza Krak : > 2016-08-24 17:56 GMT+02:00 Jon Hunter : > + >>> +Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap >>> the >>> +controllers with a simple-bus node since they are all connected to the same >&g

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-08-24 17:56 GMT+02:00 Jon Hunter : + >> +Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap >> the >> +controllers with a simple-bus node since they are all connected to the same >> +chip-select (CS4), in this example external address decoding is

Re: [PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

2016-08-24 17:56 GMT+02:00 Jon Hunter : + >> +Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap >> the >> +controllers with a simple-bus node since they are all connected to the same >> +chip-select (CS4), in this example external address decoding is provided: >> + >>

[PATCH v2 0/6] Add support for Tegra GMI bus controller

From: Mirza Krak <mirza.k...@gmail.com> Hi. This is a follow up to my previous RFC to add support for Tegra GMI bus controller. I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom carrier board which has multiple CAN controllers (SJA1000) connected to the GMI bus.

[PATCH v2 5/6] ARM: tegra: Add Tegra20 GMI support

From: Mirza Krak <mirza.k...@gmail.com> Add a device node for the GMI controller found on Tegra20. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> --- Changes in v2: - added address-cells, size-cells and ranges properties arch/arm/boot/dts/tegra20.dtsi | 14 ++ 1 file

[PATCH v2 4/6] ARM: tegra: Add Tegra30 GMI support

From: Mirza Krak <mirza.k...@gmail.com> Add a device node for the GMI controller found on Tegra30. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> --- Changes in v2: - added address-cells, size-cells and ranges properties arch/arm/boot/dts/tegra30.dtsi | 13 + 1 file

[PATCH v2 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

From: Mirza Krak <mirza.k...@gmail.com> Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which is max rate. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> --- Changes in v2: - no changes drivers/clk/tegra/clk-tegra30.c | 1 + 1 file changed, 1 insertion(+)

[PATCH v2 0/6] Add support for Tegra GMI bus controller

From: Mirza Krak Hi. This is a follow up to my previous RFC to add support for Tegra GMI bus controller. I have tested this series on a Tegra30 using a Colibri T30 SOM on a custom carrier board which has multiple CAN controllers (SJA1000) connected to the GMI bus. I have rebased on top

[PATCH v2 5/6] ARM: tegra: Add Tegra20 GMI support

From: Mirza Krak Add a device node for the GMI controller found on Tegra20. Signed-off-by: Mirza Krak --- Changes in v2: - added address-cells, size-cells and ranges properties arch/arm/boot/dts/tegra20.dtsi | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot

[PATCH v2 4/6] ARM: tegra: Add Tegra30 GMI support

From: Mirza Krak Add a device node for the GMI controller found on Tegra30. Signed-off-by: Mirza Krak --- Changes in v2: - added address-cells, size-cells and ranges properties arch/arm/boot/dts/tegra30.dtsi | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts

[PATCH v2 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

From: Mirza Krak Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which is max rate. Signed-off-by: Mirza Krak --- Changes in v2: - no changes drivers/clk/tegra/clk-tegra30.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk

[PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

From: Mirza Krak <mirza.k...@gmail.com> Document the devicetree bindings for the Generic Memory Interface (GMI) bus driver found on Tegra SOCs. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> --- Changes in v2: - Updated examples and some information based on comments fro

[PATCH v2 6/6] bus: Add support for Tegra Generic Memory Interface

From: Mirza Krak <mirza.k...@gmail.com> The Generic Memory Interface bus can be used to connect high-speed devices such as NOR flash, FPGAs, DSPs... Signed-off-by: Mirza Krak <mirza.k...@gmail.com> --- Changes in v2: - Fixed some checkpatch errors - Re-ordered probe to get rid of loc

[PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

From: Mirza Krak <mirza.k...@gmail.com> Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz which is max rate. Signed-off-by: Mirza Krak <mirza.k...@gmail.com> --- Changes in v2: - no changes drivers/clk/tegra/clk-tegra20.c | 1 + 1 file changed, 1 insertion(+)

[PATCH v2 3/6] dt/bindings: Add bindings for Tegra GMI controller

From: Mirza Krak Document the devicetree bindings for the Generic Memory Interface (GMI) bus driver found on Tegra SOCs. Signed-off-by: Mirza Krak --- Changes in v2: - Updated examples and some information based on comments from Jon Hunter. .../devicetree/bindings/bus/nvidia,tegra20-gmi.txt

[PATCH v2 6/6] bus: Add support for Tegra Generic Memory Interface

From: Mirza Krak The Generic Memory Interface bus can be used to connect high-speed devices such as NOR flash, FPGAs, DSPs... Signed-off-by: Mirza Krak --- Changes in v2: - Fixed some checkpatch errors - Re-ordered probe to get rid of local variables - Moved of_platform_default_populate call

[PATCH v2 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

From: Mirza Krak Add TEGRA20_CLK_NOR to init tabel and set default rate to 92 MHz which is max rate. Signed-off-by: Mirza Krak --- Changes in v2: - no changes drivers/clk/tegra/clk-tegra20.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk

Re: [PATCH 1/1] can: sja1000: clear interrupts on start

is OK from Christian before we do it. -- Med Vänliga Hälsningar / Best Regards ******* Mirza Krak Host Mobility AB mirza.k...@hostmobility.com Anders Personsgatan 12, 416 64 Göteborg Sweden http://www.hostmobility.com Direct: +46 31 31 32 704

Re: [PATCH 1/1] can: sja1000: clear interrupts on start

2015-11-11 11:06 GMT+01:00 Marc Kleine-Budde : > On 11/11/2015 10:54 AM, Mirza Krak wrote: >> 2015-11-11 9:04 GMT+01:00 Marc Kleine-Budde : >>> This problem occurs only an hardware, where the SJA1000 is powered >>> during system suspend? >> >> Cor

Re: [PATCH 1/1] can: sja1000: clear interrupts on start

be implemented to handle this and other problems (receive data). But still a DOWN/UP procedure should clear any previous state that could exist in the controller registers. -- Med Vänliga Hälsningar / Best Regards *** Mirza Krak

Re: [PATCH 1/1] can: sja1000: clear interrupts on start

blem. Yes, resume code should be implemented to handle this and other problems (receive data). But still a DOWN/UP procedure should clear any previous state that could exist in the controller registers. -- Med Vänliga Hälsningar / Best Regards ******

Re: [PATCH 1/1] can: sja1000: clear interrupts on start

> > to the patch. > Can we just get an ACK that it is OK from Christian before we do it. -- Med Vänliga Hälsningar / Best Regards ******* Mirza Krak Host Mobility AB mirza.k...@hostmobility.com Anders Personsgatan 12, 416 6

Re: [PATCH 1/1] can: sja1000: clear interrupts on start

2015-11-11 11:06 GMT+01:00 Marc Kleine-Budde <m...@pengutronix.de>: > On 11/11/2015 10:54 AM, Mirza Krak wrote: >> 2015-11-11 9:04 GMT+01:00 Marc Kleine-Budde <m...@pengutronix.de>: >>> This problem occurs only an hardware, where the SJA1000 is powered >>&g

[PATCH 1/1] can: sja1000: clear interrupts on start

From: Mirza Krak According to SJA1000 data sheet error-warning (EI) interrupt is not cleared by setting the controller in to reset-mode. Then if we have the following case: - system is suspended (echo mem > /sys/power/state) and SJA1000 is left in operating state - A bus error condition occ

[PATCH 1/1] can: sja1000: clear interrupts on start

From: Mirza Krak <mirza.k...@hostmobility.com> According to SJA1000 data sheet error-warning (EI) interrupt is not cleared by setting the controller in to reset-mode. Then if we have the following case: - system is suspended (echo mem > /sys/power/state) and SJA1000 is left in operat

Re: [PATCH 1/1] USB: option: add support for Cinterion PH8-P

Realized now that this was a total waste of time...Product id is the same as PH8... 2015-05-20 15:08 GMT+02:00 Mirza Krak : > From: Mirza Krak > > Also blacklist interface 4 as is done for PH8. > commit 12df84d4a802 ("USB: serial: option: blacklist interface 4 for > Cin

[PATCH 1/1] USB: option: add support for Cinterion PH8-P

From: Mirza Krak Also blacklist interface 4 as is done for PH8. commit 12df84d4a802 ("USB: serial: option: blacklist interface 4 for Cinterion PHS8 and PXS8") $ usb-devices T: Bus=02 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Pr

[PATCH 1/1] USB: option: add support for Cinterion PH8-P

From: Mirza Krak mirza.k...@hostmobility.com Also blacklist interface 4 as is done for PH8. commit 12df84d4a802 (USB: serial: option: blacklist interface 4 for Cinterion PHS8 and PXS8) $ usb-devices T: Bus=02 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=00(ifc ) Sub

Re: [PATCH 1/1] USB: option: add support for Cinterion PH8-P

Realized now that this was a total waste of time...Product id is the same as PH8... 2015-05-20 15:08 GMT+02:00 Mirza Krak mirza.k...@hostmobility.com: From: Mirza Krak mirza.k...@hostmobility.com Also blacklist interface 4 as is done for PH8. commit 12df84d4a802 (USB: serial: option