[patch 1/2] x86: apic: Export symbols for extended interrupt LVT functions

Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- arch/x86/kernel/apic_64.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c index d8d03e0..2a9f4bc 100644 --- a/arch/x86/kernel/apic_64.c +++ b/arch/x86/

Re: [PATCH] x86: apic: Export symbols for extended interrupt LVT functions

On 05.12.07 08:51:02, Arjan van de Ven wrote: > which kernel code is using or going to use these export? For IBS it is Perfmon. See here: http://git.kernel.org/?p=linux/kernel/git/eranian/linux-2.6.git;a=commit;h=7caef3e19d17349f869884f5adf7c9823e32ade7 MCE export has been added for consistency r

[PATCH] x86: apic: Export symbols for extended interrupt LVT functions

Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- arch/x86/kernel/apic_64.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c index 5a31a8c..a678e8f 100644 --- a/arch/x86/kernel/apic_64.c +++ b/arch/x86/

[PATCH] x86: apic: Extended interrupt LVT support for AMD Barcelona (32bit)

Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- arch/x86/kernel/apic_32.c | 31 +++ 1 files changed, 31 insertions(+), 0 deletions(-) diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c index 1872f88..ce6e341 100644 --- a/arch/x86/kernel/a

[PATCH] Extended interrupt LVT support for AMD Barcelona

. The vector mapping is hardcoded for now. Also macro definitions in apicdef.h has been updated. The patch is relative to x86/cleanup tree. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- arch/x86/kernel/apic_64.c | 26 ++ arch/x86/kernel/cpu/

[PATCH] Extended interrupt LVT support for AMD Barcelona

This patch adds extended interrupt support for AMD Barcelona CPUs. The patch provides functions to setup MCE and IBS interrupt vectors. Compared to the previous K8 implementation the vector offsets are centrally handled now in apic_64.c. Thus, the APIC setup code is responsible for vector mappings.

perfmon2 merge news

On 10.11.07 21:32:39, Andi Kleen wrote: > It would be really good to extract a core perfmon and start with > that and then add stuff as it makes sense. > > e.g. core perfmon could be something simple like just support > to context switch state and initialize counters in a basic way > and perhaps

Re: x86 merge: Keep kernel/cpu for CPU specific code?

On 13.11.07 13:02:08, Adrian Bunk wrote: > On Tue, Nov 13, 2007 at 12:44:43PM +0100, Robert Richter wrote: > > x86 CPU specific code is currently implemented in different ways for > > 64 and 32 bit. While there are almost no CPU specific files for 64 > > bit, there is th

x86 merge: Keep kernel/cpu for CPU specific code?

x86 CPU specific code is currently implemented in different ways for 64 and 32 bit. While there are almost no CPU specific files for 64 bit, there is the arch/x86/kernel/cpu/ directory for 32 bit. Is there already an idea about whether to use kernel/cpu also for 64 bit? Thanks, -Robert -- Advan

Re: [patch 1/6] x86: apicdef unification: some constants made unsigned

On 12.11.07 12:31:44, Maciej W. Rozycki wrote: > > -#defineGET_APIC_VERSION(x) ((x)&0xFF) > > -#defineGET_APIC_MAXLVT(x) (((x)>>16)&0xFF) > > -#defineAPIC_INTEGRATED(x) ((x)&0xF0) > > +#defineGET_APIC_VERS

Re: [patch 0/6] x86: apicdef.h unification

Thomas, On 06.11.07 21:32:12, Thomas Gleixner wrote: > Thanks for doing this, but please check the x86 git repository > (cleanup / mm branch) for stuff which has been worked on already. > > Maybe we need some coordination for this. Is it for sure that the x86/cleanup tree will go upstream soon a

Re: [patch 1/6] x86: apicdef unification: some constants made unsigned

On 07.11.07 12:41:09, Jeremy Fitzhardinge wrote: > > -#defineGET_APIC_VERSION(x) ((x)&0xFF) > > -#defineGET_APIC_MAXLVT(x) (((x)>>16)&0xFF) > > -#defineAPIC_INTEGRATED(x) ((x)&0xF0) > > +#defineGET_APIC_VE

[patch 3/6] x86: apicdef unification: whitespace changes only

Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- include/asm-x86/apicdef_32.h |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) Index: linux-perfmon/include/asm-x86/apicdef_32.h === --- linux-perfmon.orig/i

[patch 0/6] x86: apicdef.h unification

The following patch series unifies apicdef*h header files for the x86 architure. For a better review there are many small patches. -- Advanced Micro Devices, Inc. Operating System Research Center email: [EMAIL PROTECTED] - To unsubscribe from this list: send the line "unsubscribe linux-kernel

[patch 2/6] x86: apicdef unification: minor changes in macro order

Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- include/asm-x86/apicdef_64.h |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) Index: linux-perfmon/include/asm-x86/apicdef_64.h === --- linux-perfmon.orig/i

[patch 6/6] x86: apicdef unification: more whitespace changes

Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- include/asm-x86/apicdef.h | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) Index: linux-perfmon/include/asm-x86/apicdef.h === --- linux-perfmon.orig/i

[patch 5/6] x86: apicdef unification: 32 and 64 bit files coalesced

Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- include/asm-x86/apicdef.h| 401 +- include/asm-x86/apicdef_32.h | 402 -- include/asm-x86/apicdef_64.h | 402 ---

[patch 4/6] x86: apicdef unification: CONFIG_X86_32 checks added

Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- include/asm-x86/apicdef_32.h | 28 include/asm-x86/apicdef_64.h | 11 +++ 2 files changed, 39 insertions(+), 0 deletions(-) Index: linux-perfmon/include/asm-x86/apicde

[patch 1/6] x86: apicdef unification: some constants made unsigned

Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- include/asm-x86/apicdef_32.h | 16 1 files changed, 8 insertions(+), 8 deletions(-) Index: linux-perfmon/include/asm-x86/apicdef_32.h === ---

Re: [PATCH 2.6.23] oProfile: op_model_athalon.c support for AMD Family10h (Barcelona) Performance Counters

> This patch is necessary to make Event Based Profiling work reliably on a > Family10h processor > > --- > op_model_athlon.c | 22 -- > 1 file changed, 16 insertions(+), 6 deletions(-) > --- > > Signed-off-by: Barry Kasindorf <[EMAIL PROTEC

Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona

On 05.09.07 11:12:00, H. Peter Anvin wrote: > >PCI Devices will not be the same on the bus since PCI read/write > >functions will have different behavior. Without the patches you will > >get an error when accessing ECS with CF8. We need ECS access for > >patches that setups local interrupt vectors.

Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona

On 05.09.07 06:58:58, H. Peter Anvin wrote: > >But at the moment there is no need for further discussion on this subject > >because Andi refuses to add support for Barcelona CF8/CFC ECS access. > > > > Well, they don't add any functionality, do they? As such, I would agree > with Andi -- we onl

Re: [patch 5/5] x86: Set PCI config space size to extended for AMD Barcelona

On 03.09.07 09:48:15, dean gaudet wrote: > it's so very unfortunate the PCI standard has no feature bit to indicate > the presence of ECS. Right. Not nice. > FWIW in my testing on a range of machines spanning 7 or 8 years i could > read config space reg 256... and get 0x when the device

Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona

Andi, On 03.09.07 14:48:41, Andi Kleen wrote: > > As said above, I do not see CF8 access as a workaround. I expect my > > system to work in the same way also if MMCONFIG is not available. > > It should boot sure, but exotic stuff not working is not a major issue It is not only about booting the

Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona

Andi, On 03.09.07 12:15:03, Andi Kleen wrote: > > But it is needed for some devices for full functionality. > > Examples? I can only think of PCI express error reporting, which > few drivers implement anyways and isn't really a show stopper > if it doesn't work. Besides I would be surprised if i

[patch 5/5] x86: Set PCI config space size to extended for AMD Barcelona

This patch sets the config space size for AMD Barcelona PCI devices to 4096. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- arch/i386/pci/fixup.c | 14 ++ 1 file changed, 14 insertions(+) Index: linux-2.6/arch/i386/pci/f

[patch 2/5] x86: Add AMD64 Barcelona NB cfg MSR definitions

This patch adds MSR definitions for the northbridge configuration register for AMD's Barcelona CPUs. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- include/asm-i386/msr-index.h |1 + 1 file changed, 1 insertion(+) Index: linux-2.6/include/asm-i386/

[patch 0/5] (resent) x86: PCI extended config space access on AMD Barcelona CPUs

(resent due to mail server issues) Hello, the following series of patches adds support for PCI extended configuration space access of AMD's Barcelona CPUs (family 10h). It modifies the CF8/CFC IO register access method and sets the size of the CPU's PCI devices to 4096 bytes. Regards, Robert -

[patch 3/5] x86: Add PCI extended config space access for AMD Barcelona

This patch implements PCI extended configuration space access for AMD's Barcelona CPUs. It extends the method using CF8/CFC IO addresses. An x86 capability bit has been introduced that is set for CPUs supporting PCI extended config space accesses. Signed-off-by: Robert Richter <[EMAIL P

[patch 4/5] x86: Add PCI IDs for AMD Barcelona PCI devices

Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- include/linux/pci_ids.h |5 + 1 file changed, 5 insertions(+) Index: linux-2.6/include/linux/pci_ids.h === --- linux-2.6.orig/include/linux/pci_ids.h +++ lin

[patch 1/5] x86: Add AMD64 Barcelona PMU MSR definitions

Already added to the -mm tree. Its filename is i386-add-amd64-barcelona-pmu-msr-definitions.patch Signed-off-by: Robert Richter <[EMAIL PROTECTED]> --- include/asm-i386/msr-index.h | 36 +--- 1 file changed, 25 insertions(+), 11 deletions(-) Index:

Re: [patch 7/8] 2.6.22-rc3 perfmon2 : Renaming *_k8_* symbols to *_amd64_*

On 20.06.07 12:43:59, David Rientjes wrote: > On Wed, 20 Jun 2007, Robert Richter wrote: > > > This patch renames *_k8_* symbols to *_amd64_*. > > > > Signed-off-by: Robert Richter <[EMAIL PROTECTED]> > > > > Index: linux-2

Re: [patch 2/8] 2.6.22-rc3 perfmon2 : Debug messages added

On 20.06.07 12:49:05, David Rientjes wrote: > On Wed, 20 Jun 2007, Robert Richter wrote: > > > Debug messages added for better debugging. > > > > And you added BUG_ON()'s. > > > Signed-off-by: Robert Richter <[EMAIL PROTECTED]> > >

Re: [patch 2/8] 2.6.22-rc3 perfmon2 : Debug messages added

On 20.06.07 13:22:16, Stephane Eranian wrote: > David, > > On Wed, Jun 20, 2007 at 12:49:05PM -0700, David Rientjes wrote: > > On Wed, 20 Jun 2007, Robert Richter wrote: > > > > > Debug messages added for better debugging. > > > > > > >

Re: [patch 1/8] 2.6.22-rc3 perfmon2 : Barcelona CPU detection

On 20.06.07 12:45:35, David Rientjes wrote: > On Wed, 20 Jun 2007, Robert Richter wrote: > > > Index: linux-2.6.22-rc3/arch/x86_64/perfmon/perfmon_k8.c > > === > > --- linux-2.6.22-rc3.orig/arch/x86

[patch 0/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64, version 2

Hello, this is version 2 of the patch series. Thanks to David and James for reviewing this. Below you can find a diff that shows changes to the previous version. The patches are relative to Stephane's 2.6.22-rc3 Perfmon2 release. Regards, Robert Index: linux-2.6.22-rc3/arch/i386/perfmon/perfmon.

[patch 8/8] 2.6.22-rc3 perfmon2 : Renaming of module perfmon_k8 to perfmon_amd64

This patch renames module perfmon_k8 to perfmon_amd64. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/i386/perfmon/Kconfig === --- linux-2.6.22-rc3.orig/arch/i386/perfmon/Kconfig +++ linux-2.6.

[patch 5/8] 2.6.22-rc3 perfmon2 : Initial AMD64 PMU configuration

This patch implements an initial AMD64 PMU configuration. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/i386/perfmon/perfmon.c === --- linux-2.6.22-rc3.orig/arch/i386/perfmon/perfmon.c +++

[patch 7/8] 2.6.22-rc3 perfmon2 : Renaming *_k8_* symbols to *_amd64_*

This patch renames *_k8_* symbols to *_amd64_*. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/x86_64/perfmon/perfmon_k8.c === --- linux-2.6.22-rc3.orig/arch/x86_64/perfmon/perfmon_k8.c +++

[patch 6/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

only occur if the PMU description has been configured incorrectly. Also the function interface does not allow the return of error codes. So this can be handled using BUG_ON(). Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/i386/perfmon/per

Re: [patch 6/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

d; > > u64 *mask; > > unsigned int i, num, ena; > > + unsigned int ibs_check = 0; > > +#define IBS_CHECK_FETCHCTL 0x01 > > +#define IBS_CHECK_FETCHCTR 0x02 > > +#define IBS_CHECK_OPCTL0x04 > > +#define IBS_CHECK_OPCTR0x08 > > +#define

[patch 1/8] 2.6.22-rc3 perfmon2 : Barcelona CPU detection

This patch implements Barcelona CPU detection. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/i386/perfmon/perfmon.c === --- linux-2.6.22-rc3.orig/arch/i386/perfmon/perfmon.c +++ linux-2.6.22-rc

[patch 4/8] 2.6.22-rc3 perfmon2 : Rearrangement of AMD64 MSR definitions, 2nd try

David, hex values are now lowercase, thanks. This also affects patch #6. Andi, since this is not a Perfmon specific patch, could you apply it? Thanks, -Robert --- This patch rearranges AMD64 MSR definitions. 2nd try: - hex values made lowercase Signed-off-by: Robert Richter

[patch 2/8] 2.6.22-rc3 perfmon2 : Debug messages added

Debug messages added for better debugging. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/perfmon/perfmon_file.c === --- linux-2.6.22-rc3.orig/perfmon/perfmon_file.c +++ linux-2.6.22-rc3/p

Re: [patch 4/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

David, > Please don't include mixed cases of hex digits. This entire file has all > hex digits in lowercase type, so please conform to that. I fixed this in the 2nd version of the patch. > > +#define K8_MTRRFIXRANGE_DRAM_ENABLE0x0004 /* MtrrFixDramEn bit > >*/ > > +#define K8_

[patch 3/8] 2.6.22-rc3 perfmon2 : Minor changes

Minor changes (whitespace, comments, ...) Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/x86_64/perfmon/perfmon_k8.c === --- linux-2.6.22-rc3.orig/arch/x86_64/perfmon/perfmon_k8.c +++ linux-2.6.

Re: [patch 1/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

David, thanks for your comments. On 15.06.07 11:54:24, David Rientjes wrote: > On Fri, 15 Jun 2007, Robert Richter wrote: > > > Index: linux-2.6.22-rc3/arch/i386/perfmon/perfmon.c > > === > > --- linux-2

[patch 7/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

This patch renames *_k8_* symbols to *_amd64_*. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/x86_64/perfmon/perfmon_k8.c === --- linux-2.6.22-rc3.orig/arch/x86_64/perfmon/perfmon_k8.c +++

[patch 8/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

This patch renames module perfmon_k8 to perfmon_amd64. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/i386/perfmon/Kconfig === --- linux-2.6.22-rc3.orig/arch/i386/perfmon/Kconfig +++ linux-2.6.

[patch 5/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

This patch implements an initial AMD64 PMU configuration. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/i386/perfmon/perfmon.c === --- linux-2.6.22-rc3.orig/arch/i386/perfmon/perfmon.c +++

[patch 6/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

This patch implements Instruction Based Sampling (IBS). Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/i386/perfmon/perfmon.c === --- linux-2.6.22-rc3.orig/arch/i386/perfmon/perfmon.c +++ linux-

[patch 4/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

This patch rearranges AMD64 MSR definitions. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/include/asm-i386/msr-index.h === --- linux-2.6.22-rc3.orig/include/asm-i386/msr-index.h +++ linux-2.6.

[patch 2/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

Debug messages added for better debugging. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/perfmon/perfmon_file.c === --- linux-2.6.22-rc3.orig/perfmon/perfmon_file.c +++ linux-2.6.22-rc3/p

[patch 3/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

Minor changes (whitespace, comments, ...) Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/x86_64/perfmon/perfmon_k8.c === --- linux-2.6.22-rc3.orig/arch/x86_64/perfmon/perfmon_k8.c +++ linux-2.6.

[patch 1/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

This patch implements Barcelona CPU detection. Signed-off-by: Robert Richter <[EMAIL PROTECTED]> Index: linux-2.6.22-rc3/arch/i386/perfmon/perfmon.c === --- linux-2.6.22-rc3.orig/arch/i386/perfmon/perfmon.c +++ linux-2.6.22-rc

[patch 0/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

Hello, the following series of patches adds support for Instruction Based Sampling (IBS) of Barcelona CPUs. IBS is a code profiling mechanism that enables the processor to select a random instruction fetch or micro-op after a programmed time interval has expired and record specific performance inf

Re: [PATCH 20/22] 2.6.22-rc3 perfmon2 : new x86_64 files

Stephane, > > > + > > > + if (current_cpu_data.x86 != 15) { > > > + PFM_INFO("unsupported family=%d", current_cpu_data.x86); > > > + return -1; > > > + } > > > > Already obsolete with Barcelona and Griffin (16 and 17) but very similar > > counters. > > > Yes, but those will get

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