Hello Peter,
> -Original Message-
> From: Peter Korsgaard On Behalf Of Peter Korsgaard
> Sent: Wednesday, October 21, 2020 9:16 PM
> To: Sagar Kadam
> Cc: linux-kernel@vger.kernel.org; linux-ri...@lists.infradead.org; linux-
> i...@vger.kernel.org; and...@lunn.ch; Paul
Hello Peter,
> -Original Message-
> From: Peter Korsgaard On Behalf Of Peter Korsgaard
> Sent: Thursday, October 15, 2020 8:19 PM
> To: Sagar Kadam
> Cc: linux-kernel@vger.kernel.org; linux-ri...@lists.infradead.org; linux-
> i...@vger.kernel.org; and...@lunn.ch; Paul
> -Original Message-
> From: Andreas Schwab
> Sent: Friday, October 9, 2020 11:55 PM
> To: Sagar Kadam
> Cc: linux-kernel@vger.kernel.org; linux-ri...@lists.infradead.org; linux-
> i...@vger.kernel.org; pe...@korsgaard.com; and...@lunn.ch; Paul
> Walmsley ( Sifive)
Hello Peter,
> -Original Message-
> From: Peter Korsgaard On Behalf Of Peter Korsgaard
> Sent: Wednesday, October 7, 2020 5:10 PM
> To: Sagar Kadam
> Cc: linux-kernel@vger.kernel.org; linux-ri...@lists.infradead.org; linux-
> i...@vger.kernel.org; and...@lunn.ch; Paul
> -Original Message-
> From: Rob Herring
> Sent: Wednesday, October 7, 2020 12:13 AM
> To: Sagar Kadam
> Cc: a...@eecs.berkeley.edu; linux-ri...@lists.infradead.org;
> t...@linutronix.de; linux-...@vger.kernel.org; pal...@dabbelt.com;
> ja...@lakedaemon.net; Yash
Convert device tree bindings for SiFive's PLIC to YAML format
Signed-off-by: Sagar Kadam
---
.../interrupt-controller/sifive,plic-1.0.0.txt | 58 -
.../interrupt-controller/sifive,plic-1.0.0.yaml| 97 ++
2 files changed, 97 insertions(+), 58 dele
cussion from here [3]
[3] https://patchwork.kernel.org/cover/11769499/
-Rebased patches to 5.9-rc7
V1: Base version.
Sagar Kadam (3):
dt-bindings: fu540: prci: convert PRCI bindings to json-schema
dt-bindings: riscv: convert plic bindings to json-schema
dt-bindings: riscv: convert pwm bin
FU540-C000 SoC from SiFive has a PRCI block, here we convert
the device tree bindings from txt to YAML.
Signed-off-by: Sagar Kadam
---
.../bindings/clock/sifive/fu540-prci.txt | 46 -
.../bindings/clock/sifive/fu540-prci.yaml | 60 ++
2
Convert device tree bindings for SiFive's PWM controller to YAML
format.
Signed-off-by: Sagar Kadam
---
.../devicetree/bindings/pwm/pwm-sifive.txt | 33 ---
.../devicetree/bindings/pwm/pwm-sifive.yaml| 69 ++
2 files changed, 69 insertions(+
Rob Herring here[3]
[3] https://lkml.org/lkml/2020/9/15/670
-Rebased patch on 5.9-rc5
V2:
-Fixed bot failure mentioned by Rob Herring
-Updated dt-schema and kernel as suggested
V1:
Base version
Sagar Kadam (1):
dt-bindings: riscv: sifive-l2-cache: convert bindings to json-schema
.../devic
Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 Cache
controller to YAML format.
Signed-off-by: Sagar Kadam
---
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 51 ---
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 98 +
Hello Rob,
> -Original Message-
> From: Rob Herring
> Sent: Wednesday, September 23, 2020 2:07 AM
> To: Sagar Kadam
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> ri...@lists.infradead.org; devicet...@vger.kernel.org; linux-
> c...@vge
Hello Rob,
> -Original Message-
> From: Rob Herring
> Sent: Wednesday, September 23, 2020 2:04 AM
> To: Sagar Kadam
> Cc: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> ri...@lists.infradead.org; devicet...@vger.kernel.org; linux-
> c...@vge
Hello Rob,
> -Original Message-
> From: Rob Herring
> Sent: Wednesday, September 23, 2020 12:57 AM
> To: Sagar Kadam
> Cc: linux-kernel@vger.kernel.org; linux-ri...@lists.infradead.org;
> devicet...@vger.kernel.org; Paul Walmsley ( Sifive)
> ; pa
kernel as suggested
V1:
Base version
Sagar Kadam (1):
dt-bindings: riscv: sifive-l2-cache: convert bindings to json-schema
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 51
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 90 ++
2 files changed,
Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 Cache
controller to YAML format.
Signed-off-by: Sagar Kadam
---
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 51
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 90 +
Hello Stephen,
> -Original Message-
> From: Stephen Boyd
> Sent: Tuesday, September 15, 2020 5:37 AM
> To: Sagar Kadam ;
> devicet...@vger.kernel.org; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-...@vger.kernel.org; linux-
> ri...@lists.infrad
Hello Rob,
> -Original Message-
> From: Rob Herring
> Sent: Monday, September 14, 2020 11:30 PM
> To: Sagar Kadam
> Cc: linux-kernel@vger.kernel.org; linux-ri...@lists.infradead.org;
> devicet...@vger.kernel.org; Paul Walmsley ( Sifive)
> ; pal...@dabbelt.com;
>
refer it.
[1] https://paste.ubuntu.com/p/VHqqnXdrkJ
Additionally the default log of dt_binding_check on linux-5.9-rc4 without
these patches can be found here [2].
[2] https://paste.ubuntu.com/p/KNGJrJvvdt
Patch History:
V1: Base version.
Sagar Kadam (3):
dt-b
Convert device tree bindings for SiFive's PLIC to YAML format
Signed-off-by: Sagar Kadam
---
.../interrupt-controller/sifive,plic-1.0.0.txt | 58 ---
.../interrupt-controller/sifive,plic-1.0.0.yaml| 107 +
2 files changed, 107 insertions(+), 58 dele
Convert device tree bindings for SiFive's PWM controller to YAML
format.
Signed-off-by: Sagar Kadam
---
.../devicetree/bindings/pwm/pwm-sifive.txt | 33 --
.../devicetree/bindings/pwm/pwm-sifive.yaml| 72 ++
2 files changed, 72 insertions(+
FU540-C000 SoC from SiFive has a PRCI block, here we convert
the device tree bindings from txt to YAML.
Signed-off-by: Sagar Kadam
---
.../bindings/clock/sifive/fu540-prci.txt | 46 -
.../bindings/clock/sifive/fu540-prci.yaml | 75 ++
2 files
Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 Cache
controller to YAML format.
Signed-off-by: Sagar Kadam
---
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 51
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 92 +
pdated dt-schema and kernel as suggested
V1:
Base version
Sagar Kadam (1):
dt-bindings: riscv: sifive-l2-cache: convert bindings to json-schema
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 51
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 92 ++
Hi,
Please ignore this v2, since the subject line missed the patch sequences 0/1
and 1/1.
Will resubmit it.
Thanks & BR,
Sagar
> -Original Message-
> From: Sagar Kadam
> Sent: Friday, August 28, 2020 9:31 PM
> To: linux-kernel@vger.kernel.org
> Cc: linux-ri...@
Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 Cache
controller to YAML format.
Signed-off-by: Sagar Kadam
---
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 51
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 92 +
log is here[2].
[1] https://paste.ubuntu.com/p/R5b52vCkKJ/
[2] https://paste.ubuntu.com/p/gwYY3hd9Rx/
Change History:
V2:
-Fixed bot failure mentioned by Rob Herring
-Updated dt-schema and kernel as suggested
V1:
Base version
Sagar Kadam (1):
dt-bindings: riscv: sifive-l2-cac
Hi Rob,
> -Original Message-
> From: Rob Herring
> Sent: Tuesday, August 25, 2020 9:51 PM
> To: Sagar Kadam
> Cc: a...@eecs.berkeley.edu; devicet...@vger.kernel.org; Paul Walmsley (
> Sifive) ; Yash Shah ;
> pal...@dabbelt.com; linux-kernel@vger.ke
Hello Rob,
> -Original Message-
> From: Rob Herring
> Sent: Monday, August 24, 2020 11:06 PM
> To: Sagar Kadam
> Cc: a...@eecs.berkeley.edu; devicet...@vger.kernel.org; Paul Walmsley (
> Sifive) ; robh...@kernel.org; Yash Shah
> ; pal...@dabbelt.com; linux-
>
Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 Cache
controller to YAML format.
Signed-off-by: Sagar Kadam
---
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 51
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 93 +
ml
CHECK arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml
linux>
Sagar Kadam (1):
dt-bindings: riscv: sifive-l2-cache: convert bindings to json-schema
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 51
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 93 ++
Hi,
A gentle reminder.
Any suggestions here?
BR,
Sagar Kadam
> -Original Message-
> From: Sagar Kadam
> Sent: Tuesday, May 19, 2020 4:16 PM
> To: linux-ri...@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> m...@lists.infradead.org
> Cc: Paul Walmsley ;
Hello,
A gentle reminder. Any suggestions here?
BR,
Sagar
> -Original Message-
> From: Sagar Kadam
> Sent: Wednesday, May 13, 2020 7:27 PM
> To: linux-kernel@vger.kernel.org; linux-ri...@lists.infradead.org;
> devicet...@vger.kernel.org; robh...@kernel.org
> Cc:
Hi Pratyush,
> -Original Message-
> From: Pratyush Yadav
> Sent: Friday, May 15, 2020 12:35 PM
> To: Sagar Kadam
> Cc: linux-ri...@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> m...@lists.infradead.org; tudor.amba...@microchip.com;
> miquel.ray
Hello Greg and Palmer,
> -Original Message-
> From: Greg KH
> Sent: Wednesday, May 13, 2020 12:30 PM
> To: Palmer Dabbelt
> Cc: Sagar Kadam ; linux-ser...@vger.kernel.org;
> linux-ri...@lists.infradead.org; linux-kernel@vger.kernel.org; Paul Walmsley
> ; a...@eec
Hello Rob,
> -Original Message-
> From: Rob Herring
> Sent: Tuesday, May 12, 2020 7:42 AM
> To: Sagar Kadam
> Cc: linux-kernel@vger.kernel.org; linux-ri...@lists.infradead.org;
> pal...@dabbelt.com; Paul Walmsley ;
> atish.pa...@wdc.com; devicet...@vger.kernel.or
Hi,
> -Original Message-
> From: Andreas Schwab
> Sent: Wednesday, May 6, 2020 12:57 PM
> To: Anup Patel
> Cc: Sagar Kadam ; Palmer Dabbelt
> ; vigne...@ti.com; tudor.amba...@microchip.com;
> rich...@nod.at; Paul Walmsley ; linux-
> ker...@vger.kernel.org; linux
Hi Palmer,
> -Original Message-
> From: Palmer Dabbelt
> Sent: Wednesday, May 6, 2020 4:54 AM
> To: Sagar Kadam
> Cc: tudor.amba...@microchip.com; miquel.ray...@bootlin.com;
> rich...@nod.at; vigne...@ti.com; Paul Walmsley
> ; linux-ri...@lists.infrad
Hello Palmer,
> -Original Message-
> From: Palmer Dabbelt
> Sent: Tuesday, May 5, 2020 3:40 AM
> To: Sagar Kadam
> Cc: tudor.amba...@microchip.com; miquel.ray...@bootlin.com;
> rich...@nod.at; vigne...@ti.com; Paul Walmsley
> ; linux-ri...@lists.infrad
e a more
> generic approach.
> These protection scheme patches are not included in this series, will submit
> those separately.
>
A gentle reminder!!
Any comments on this series?
Thanks & BR,
Sagar Kadam
> V7<->V8:
> -Rebased this series on mainline v5.3-rc4.
>
Hi Bin,
On Mon, Aug 26, 2019 at 2:49 AM Bin Meng wrote:
>
> On Tue, Aug 13, 2019 at 8:40 PM Sagar Shrikant Kadam
> wrote:
> >
> > Update spi_nor_id table for is25wp256 (32MB) device from ISSI,
> > present on HiFive Unleashed dev board (Rev: A00).
> >
> > Set method to enable quad mode for ISSI d
Hi Vignesh,
On Fri, Aug 9, 2019 at 5:05 PM Vignesh Raghavendra wrote:
>
>
>
> On 03/07/19 12:09 AM, Sagar Shrikant Kadam wrote:
> > Use the post bfpt fixup hook for the is25wp256 device as done for
> > is25lp256 device to overwrite the address width advertised by BFPT.
> >
> > For instance the st
Hello Vignesh,
On Fri, Aug 9, 2019 at 4:57 PM Vignesh Raghavendra wrote:
>
> Hi Sagar,
>
> On 03/07/19 12:09 AM, Sagar Shrikant Kadam wrote:
> [...]> +static int issi_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
> > +{
> > + int status_old, status_new, blk_prot;
> > + u8 mask;
> >
Hello Andrew,
On Fri, Jul 19, 2019 at 6:57 PM Andrew Lunn wrote:
>
> On Fri, Jul 19, 2019 at 05:23:45PM +0530, Sagar Kadam wrote:
> > > +ð0 {
> > > + status = "okay";
> > > + phy-mode = "gmii";
> > > +
The series looks good to me.
Reviewed-by: Sagar Kadam
On Fri, Jul 19, 2019 at 4:41 PM Yash Shah wrote:
>
> DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
>
> Signed-off-by: Yash Shah
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.
Hi Tudor,
On Mon, Jul 15, 2019 at 4:35 PM wrote:
>
>
>
> On 07/15/2019 01:45 PM, Sagar Kadam wrote:
> > Hi All,
> >
> > Any comments on this series?
> >
>
> Hi, Sagar,
>
> I was OOO the last 2 weeks and previously I was busy with other spi-nor
>
; -Add support for locking is25xx device.
>
> v1:
> -Add support for is25wp256 device.
>
> Sagar Shrikant Kadam (4):
> mtd: spi-nor: add support for is25wp256
> mtd: spi-nor: fix nor->addr_width for is25wp256
> mtd: spi-nor: add support to unlock the flash device
> mtd: spi-nor: add locking support for is25wp256 device
>
> drivers/mtd/spi-nor/spi-nor.c | 343
> +++---
> include/linux/mtd/spi-nor.h | 8 +
> 2 files changed, 300 insertions(+), 51 deletions(-)
>
> --
> 1.9.1
>
Hi All,
Any comments on this series?
BR,
Sagar Kadam
Hi Vignesh,
On Mon, Jun 24, 2019 at 6:37 PM Vignesh Raghavendra wrote:
>
>
>
> On 24/06/19 6:10 PM, Sagar Kadam wrote:
> > Hello Vignesh,
> >
> > On Mon, Jun 24, 2019 at 3:04 PM Vignesh Raghavendra wrote:
> >>
> >> Hi,
> >>
> &g
Hello Vignesh,
On Mon, Jun 24, 2019 at 3:04 PM Vignesh Raghavendra wrote:
>
> Hi,
>
> On 21/06/19 3:58 PM, Sagar Kadam wrote:
> > Hello Vignesh,
> >
> > On Fri, Jun 21, 2019 at 11:33 AM Vignesh Raghavendra
> > wrote:
> >>
> >> Hi,
> &g
Hello Vignesh,
On Fri, Jun 21, 2019 at 11:33 AM Vignesh Raghavendra wrote:
>
> Hi,
>
> On 17/06/19 8:48 PM, Sagar Kadam wrote:
> > Hello Vignesh,
> >
> > Thanks for your review comments.
> >
> > On Sun, Jun 16, 2019 at 6:14 PM Vignesh Raghavendra wrote:
ocked_sr(nor, ofs, len, status);
> > }
> >
> > static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
> > @@ -1461,6 +1578,77 @@ static int macronix_quad_enable(struct spi_nor *nor)
> > }
> >
> > /**
> > + * issi_lock() - set BP[0123]
Hello Joe,
Thanks for reviewing the patch.
On Tue, Jun 18, 2019 at 5:55 AM Joe Perches wrote:
>
> On Mon, 2019-06-17 at 21:10 +0530, Sagar Kadam wrote:
> > On Sun, Jun 16, 2019 at 6:35 PM Vignesh Raghavendra wrote:
> []
> > > > +static int issi_unlock(struct spi_nor
r_lock;
> > mtd->_unlock = spi_nor_unlock;
> > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> > index ff13297..9a7d719 100644
> > --- a/include/linux/mtd/spi-nor.h
> > +++ b/include/linux/mtd/spi-nor.h
> > @@ -127,6 +127,7 @@
> > #define SR_BP0 BIT(2) /* Block protect 0 */
> > #define SR_BP1 BIT(3) /* Block protect 1 */
> > #define SR_BP2 BIT(4) /* Block protect 2 */
> > +#define SR_BP3 BIT(5) /* Block protect 3 for ISSI
> > device*/
>
> No need to mention ISSI here. I am sure there are devices from other
> vendors with BP3
>
Ok, I will drop this in V6 and submit.
> > #define SR_TBBIT(5) /* Top/Bottom protect */
> > #define SR_SRWD BIT(7) /* SR write protect */
> > /* Spansion/Cypress specific status bits */
> >
>
> Regards
> Vignesh
Thanks & BR,
Sagar Kadam
rom SFDP. I have verified that
with 3 byte address width, the
flascp util fails while verifying the written data. Please let me
know your views on this?
BR,
Sagar Kadam
> Regards
> Vignesh
>
>
> > } else if (info->addr_width) {
> > nor->addr_w
Hello Rob,
Please let me know if this patch is as per your requirements/comments
you mentioned earlier.
Thanks & Regards,
Sagar Kadam
On Wed, May 29, 2019 at 9:57 AM Sagar Shrikant Kadam
wrote:
>
> Reformatted compatibility strings to one valid combination on
> each line.
>
On Wed, May 29, 2019 at 9:23 PM Andrew Lunn wrote:
>
> On Wed, May 29, 2019 at 09:57:27AM +0530, Sagar Shrikant Kadam wrote:
> > The i2c-ocore driver already has a polling mode interface.But it needs
> > a workaround for FU540 Chipset on HiFive unleashed board (RevA00).
> > There is an erratum in
pace needed ^
>
> And drop the end of line commas and period.
>
>
> > +For Opencore based I2C IP block reimplemented in
> > +FU540-C000 SoC.Please refer
> > sifive-blocks-ip-versioning.tx
per subsystem.
>
Thanks Wolfram for confirming on this.
I will do check in the mail archives for additional info.
Regards,
Sagar Kadam
> Wolfram Sang should pick the patchset up.
>
Ok, Great. Do we need to write to him about this patchset?
> Andrew
Regards,
Sagar Kadam
Hi Andrew,
On Tue, May 21, 2019 at 7:24 PM Andrew Lunn wrote:
>
> > static void ocores_process_polling(struct ocores_i2c *i2c)
> > {
> > + const struct of_device_id *match;
> > +
> > + match = of_match_node(ocores_i2c_match, i2c->adap.dev.of_node);
> > +
> > while (1) {
> >
quot;aeroflexgaisler,i2cmst",
> > +"sifive,fu540-c000-i2c","sifive,i2c0".
> > + For Opencore based I2C IP block reimplemented in
>
> It looks like there are some tabs vs space issues here.
Ohh. It was not catched in checkpatch.pl. I will update it.
Thanks,
Sagar Kadam
>Andrew
Thanks Andreas,
Yes, I rebased to v5.2-rc1 and observed that there have been changes
in polling interface, and i2c->flags is not longer being used for
setting the polling mode. I am working on a way to hook in the fix for
broken IRQ and will submit it in v6.
Thanks & BR,
Sagar Kadam
On T
Hi Rob,
On Mon, May 20, 2019 at 8:07 PM Rob Herring wrote:
>
> On Mon, May 20, 2019 at 9:12 AM Sagar Shrikant Kadam
> wrote:
> >
> > Add FU540-C000 specific device tree bindings to already
> > available i2-ocores file. This device is available on
> > HiFive Unleashed Rev A00 board. Move interru
On Mon, May 20, 2019 at 8:22 PM Andrew Lunn wrote:
>
> On Mon, May 20, 2019 at 07:41:18PM +0530, Sagar Shrikant Kadam wrote:
> > The i2c-ocore driver already has a polling mode interface.But it needs
> > a workaround for FU540 Chipset on HiFive unleashed board (RevA00).
> > There is an erratum in
Hi Andrew,
On Mon, May 20, 2019 at 6:11 PM Andrew Lunn wrote:
>
> > @@ -406,7 +416,7 @@ static int ocores_xfer(struct i2c_adapter *adap,
> > {
> > struct ocores_i2c *i2c = i2c_get_adapdata(adap);
> >
> > - if (i2c->flags & OCORES_FLAG_POLL)
> > + if ((i2c->flags & (OCORES_FLAG_POLL
Hi Andrew,
On Thu, May 16, 2019 at 6:37 PM Andrew Lunn wrote:
>
> On Thu, May 16, 2019 at 10:38:40AM +0530, Sagar Shrikant Kadam wrote:
> > The i2c-ocore driver already has a polling mode interface.But it needs
> > a workaround for FU540 Chipset on HiFive unleashed board (RevA00).
> > There is an
i2c->flags |= OCORES_FLAG_POLL;
>
> These two don't need to be exclusive. It makes more sense to say
> SIFIVE needs to poll and it its IRQ is broken. A lot of your other
> changes then go away.
>
Other SiFive chip's with Ocore based I2C re-implementation might not
need the broken IRQ workaround.
and can use the the existing mainline polling mode interface, using
OCORES_FLAG_POLL.
Thanks & BR,
Sagar Kadam
>Andrew
Hello Rob,
Thank you for the review.
On Tue, May 14, 2019 at 2:26 AM Rob Herring wrote:
>
> On Tue, May 07, 2019 at 08:45:06PM +0530, Sagar Shrikant Kadam wrote:
> > Add FU540-C000 specific device tree bindings to already
> > available i2-ocores file. This device is available on
> > HiFive Unlea
On Mon, May 6, 2019 at 6:59 PM Andrew Lunn wrote:
>
> > /*
> > * 'process_lock' exists because ocores_process() and
> > ocores_process_timeout()
> > @@ -239,8 +240,13 @@ static irqreturn_t ocores_isr(int irq, void *dev_id)
> > struct ocores_i2c *i2c = dev_id;
> > u8 stat = oc_getre
On Mon, May 6, 2019 at 6:49 PM Andrew Lunn wrote:
>
> On Mon, May 06, 2019 at 06:23:58PM +0530, Sagar Shrikant Kadam wrote:
> > Add DT binding for OpenCore's based i2c device as found in
> > FU540 Chipset on HiFive Unleashed Platform (Rev A00).
> >
> > The doc explains, how to add DT support for I
On Tue, Apr 30, 2019 at 10:49 PM Paul Walmsley wrote:
>
> On Sun, 28 Apr 2019, Sagar Shrikant Kadam wrote:
>
> > Nor device (is25wp256 mounted on HiFive unleashed Rev A00 board) from ISSI
> > have memory blocks guarded by block protection bits BP[0,1,2,3].
> >
> > Clearing block protection bits,un
Thank you Paul, for your review comments.
On Tue, Apr 30, 2019 at 10:33 PM Paul Walmsley wrote:
>
> On Sun, 28 Apr 2019, Sagar Shrikant Kadam wrote:
>
> > Update spi_nor_id tablet for is25wp256 (32MB)device from ISSI,
> > present on HiFive Unleashed dev board (Rev: A00).
> >
> > Set method to ena
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