Hi Krishna,
On 2020-05-28 14:08, Krishna Manikandan wrote:
Define shutdown callback for display drm driver,
so as to disable all the CRTCS when shutdown
notification is received by the driver.
Would be nice to add some more context for adding this shutdown callback
something like below:
If
Hi Mathieu,
On 2020-05-25 21:45, Mathieu Poirier wrote:
Hi Sai,
On Sat, May 23, 2020 at 12:06:50AM +0530, Sai Prakash Ranjan wrote:
This series is mainly to add support for replicators
which lose context on removing AMBA clock like on SC7180
SoC where replicator in AOSS domain loses context
a group reference on
its own, so to fix this leak, do not take another reference in
iommu_alloc_default_domain() and pass the group as a function parameter
instead.
Reference:
https://lore.kernel.org/lkml/20200522130145.30067-1-saiprakash.ran...@codeaurora.org/
Reported-by: Sai Prakash Ranjan
Cc
Hi Joerg,
On 2020-05-25 18:32, Joerg Roedel wrote:
Hi,
On Fri, May 22, 2020 at 06:31:45PM +0530, Sai Prakash Ranjan wrote:
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index a4c2f122eb8b..05f7b77c432f 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -1491,6
On 2020-05-25 17:23, Jonathan Marek wrote:
On 5/25/20 7:40 AM, Sai Prakash Ranjan wrote:
On 2020-05-25 16:57, Jonathan Marek wrote:
On 5/25/20 7:17 AM, Sai Prakash Ranjan wrote:
Hi,
On 2020-05-25 16:38, Jonathan Marek wrote:
On 5/25/20 6:54 AM, Sai Prakash Ranjan wrote:
On 2020-05-25 15:39
On 2020-05-25 16:57, Jonathan Marek wrote:
On 5/25/20 7:17 AM, Sai Prakash Ranjan wrote:
Hi,
On 2020-05-25 16:38, Jonathan Marek wrote:
On 5/25/20 6:54 AM, Sai Prakash Ranjan wrote:
On 2020-05-25 15:39, Jonathan Marek wrote:
Hi,
On 5/25/20 5:42 AM, Sai Prakash Ranjan wrote:
Hi Jonathan
Hi,
On 2020-05-25 16:38, Jonathan Marek wrote:
On 5/25/20 6:54 AM, Sai Prakash Ranjan wrote:
On 2020-05-25 15:39, Jonathan Marek wrote:
Hi,
On 5/25/20 5:42 AM, Sai Prakash Ranjan wrote:
Hi Jonathan,
On 2020-05-24 08:08, Jonathan Marek wrote:
Add the apps_smmu node for sm8250. Note
On 2020-05-25 15:39, Jonathan Marek wrote:
Hi,
On 5/25/20 5:42 AM, Sai Prakash Ranjan wrote:
Hi Jonathan,
On 2020-05-24 08:08, Jonathan Marek wrote:
Add the apps_smmu node for sm8250. Note that adding the iommus field
for
UFS is required because initializing the iommu removes the bypass
Hi Jonathan,
On 2020-05-25 02:36, Jonathan Marek wrote:
Add support for the graphics clock controller found on SM8250
based devices. This would allow graphics drivers to probe and
control their clocks.
This is copied from the downstream kernel, adapted for upstream.
For example, GDSCs have
Hi Jonathan,
On 2020-05-24 08:08, Jonathan Marek wrote:
Add the apps_smmu node for sm8250. Note that adding the iommus field
for
UFS is required because initializing the iommu removes the bypass
mapping
that created by the bootloader.
This statement doesn't seem right, you can just say
Hi Jonathan,
On 2020-05-24 08:08, Jonathan Marek wrote:
Add the apps_smmu node for sm8150. Note that adding the iommus field
for
UFS is required because initializing the iommu removes the bypass
mapping
that created by the bootloader.
Signed-off-by: Jonathan Marek
---
Add an optional boolean property "qcom,replicator-loses-context" to
identify replicators which loses context when AMBA clocks are removed
in certain configurable replicator designs.
Reviewed-by: Mike Leach
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bi
with such
limitations. So add a new property "qcom,replicator-loses-context"
to identify such replicators and reset them.
Suggested-by: Mike Leach
Reviewed-by: Mike Leach
Signed-off-by: Sai Prakash Ranjan
---
.../coresight/coresight-replicator.c | 55 +--
1 fi
/
Changes since v2:
* Added DT maintainers which I missed in v2
* Added proper kernel-doc and header as per Mathieu
Sai Prakash Ranjan (2):
coresight: replicator: Reset replicator if context is lost
dt-bindings: arm: coresight: Add optional property to replicators
.../devicetree/bindings/arm
Hi Mathieu,
On 2020-05-22 23:10, Mathieu Poirier wrote:
Hi Sai,
On Tue, May 19, 2020 at 07:06:02PM +0530, Sai Prakash Ranjan wrote:
On some QCOM SoCs, replicators in Always-On domain loses its
context as soon as the clock is disabled. Currently as a part
of pm_runtime workqueue, clock
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/iommu.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index a4c2f122eb8b..05f7b77c432f 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -1491,6 +1491,7
Hi Mike,
On 2020-05-21 21:38, Mike Leach wrote:
Hi Sai,
On Tue, 19 May 2020 at 14:36, Sai Prakash Ranjan
wrote:
On some QCOM SoCs, replicators in Always-On domain loses its
context as soon as the clock is disabled. Currently as a part
of pm_runtime workqueue, clock is disabled after
On 2020-05-19 20:41, Rob Clark wrote:
On Tue, May 19, 2020 at 2:26 AM Sai Prakash Ranjan
wrote:
Hi Will,
On 2020-05-18 21:15, Will Deacon wrote:
> On Mon, May 11, 2020 at 11:30:08AM -0600, Jordan Crouse wrote:
>> On Fri, May 08, 2020 at 08:40:40AM -0700, Rob Clark wrote:
>>
Use CS_AMBA_ID macro for coresight catu AMBA id table
instead of open coding.
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-catu.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c
b/drivers
Add an optional boolean property "qcom,replicator-loses-context" to
identify replicators which loses context when AMBA clocks are removed
in certain configurable replicator designs.
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/arm/coresight.txt | 6
Use CS_AMBA_ID macro for dynamic replicator AMBA id table
instead of open coding.
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-replicator.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight
.
Previous version is here - https://lore.kernel.org/patchwork/patch/1239923/
More discussion is found here - https://lore.kernel.org/patchwork/patch/1231182/
There were no patch 1 and patch 2 in v1.
Sai Prakash Ranjan (4):
coresight: replicator: Use CS_AMBA_ID macro for id table
coresight: catu
with such
limitations. So add a new property "qcom,replicator-loses-context"
to identify such replicators and reset them.
Suggested-by: Mike Leach
Signed-off-by: Sai Prakash Ranjan
---
Added Mike's suggested by for parts other than the DT property.
Perhaps I should add Co-developed-by
l Deacon wrote:
> > >
> > > On Thu, May 07, 2020 at 11:55:54AM +0100, Robin Murphy wrote:
> > > > On 2020-05-07 11:14 am, Sai Prakash Ranjan wrote:
> > > > > On 2020-04-22 01:50, Sai Prakash Ranjan wrote:
> > > > > > Add stall implementation hook to
Hi Mike, Suzuki,
On 2020-05-16 15:34, Sai Prakash Ranjan wrote:
Hi Mike, Suzuki
[...]
Please look at the CoreSight components specification 3.0 (ARM IHI
0029E) Section B2.1.2 which describes the Unique Component Identifier
(UCI).
As mentioned above this consists of a combination of bits
Hi Bjorn,
On 2020-05-19 00:21, Bjorn Andersson wrote:
On Fri 15 May 03:55 PDT 2020, Sai Prakash Ranjan wrote:
[...]
The previous version of this patch in QCOM tree seems to have added
the
property to replicator node instead of etm7 node, can you please drop
that from the tree and apply
Hi Mike, Suzuki
[...]
Please look at the CoreSight components specification 3.0 (ARM IHI
0029E) Section B2.1.2 which describes the Unique Component Identifier
(UCI).
As mentioned above this consists of a combination of bits from
multiple registers, including PIDR4.
Ok got it now, thanks
On 2020-05-15 21:28, Sai Prakash Ranjan wrote:
Hi Mathieu,
On 2020-05-15 21:21, Mathieu Poirier wrote:
On Fri, May 15, 2020 at 08:37:13PM +0530, Sai Prakash Ranjan wrote:
Hi Mathieu,
On 2020-05-15 20:22, Mathieu Poirier wrote:
> On Thu, 14 May 2020 at 12:39, Sai Prakash Ranjan
>
wer up bit is set (TRCPDCR.PU).
Signed-off-by: Tingwei Zhang
Co-developed-by: Sai Prakash Ranjan
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/arm/coresight.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/coresi
as that of respective CPU cores,
they are powered on when the CPU core is powered on. So we can
skip powering up of trace unit after checking for this errata
via new property called "qcom,skip-power-up".
Signed-off-by: Tingwei Zhang
Co-developed-by: Sai Prakash Ranjan
Signed-off-by: S
This series adds support to skip powering up of trace unit on systems
with an errata which stops CPU watchdog counter when power up bit is
set (TRCPDCR.PU = 1). Setting this bit is not required on Qualcomm
Technologies Inc. chipsets where this errata exists since the ETMs
are in the same power
Hi Mathieu,
On 2020-05-15 21:21, Mathieu Poirier wrote:
On Fri, May 15, 2020 at 08:37:13PM +0530, Sai Prakash Ranjan wrote:
Hi Mathieu,
On 2020-05-15 20:22, Mathieu Poirier wrote:
> On Thu, 14 May 2020 at 12:39, Sai Prakash Ranjan
> wrote:
> >
> > Hi Mathieu,
> >
Hi Mathieu,
On 2020-05-15 20:22, Mathieu Poirier wrote:
On Thu, 14 May 2020 at 12:39, Sai Prakash Ranjan
wrote:
Hi Mathieu,
On 2020-05-14 23:30, Mathieu Poirier wrote:
> Good morning Sai,
>
> On Thu, May 14, 2020 at 04:29:15PM +0530, Sai Prakash Ranjan wrote:
>> From
Hi Bjorn,
On 2020-05-15 16:21, Sai Prakash Ranjan wrote:
Now that deep idle states are properly supported on SC7180,
we need to add "coresight-loses-context-with-cpu" property
to avoid failure of trace session because of losing context
on entering deep idle states.
Reviewed-by: St
CPU watchdog counter is stopped when power up bit is set.
Depends on https://lore.kernel.org/patchwork/cover/1242100/ changes.
Sai Prakash Ranjan (2):
arm64: dts: qcom: sc7180: Support ETMv4 power management
arm64: dts: qcom: sc7180: Add support to skip powering up of ETM
arch/arm64/boot/dts
Now that deep idle states are properly supported on SC7180,
we need to add "coresight-loses-context-with-cpu" property
to avoid failure of trace session because of losing context
on entering deep idle states.
Reviewed-by: Stephen Boyd
Signed-off-by: Sai Prakash Ranjan
---
Add "qcom,skip-power-up" property to skip powering up ETM
on SC7180 SoC to workaround a hardware errata where CPU
watchdog counter is stopped when ETM power up bit is set
(i.e., when TRCPDCR.PU = 1).
Signed-off-by: Sai Prakash Ranjan
---
Depends on ETM driver change her
as that of respective CPU cores,
they are powered on when the CPU core is powered on. So we can
skip powering up of trace unit after checking for this errata
via new property called "qcom,skip-power-up".
Signed-off-by: Tingwei Zhang
Co-developed-by: Sai Prakash Ranjan
Signed-off-by: S
wer up bit is set (TRCPDCR.PU).
Signed-off-by: Tingwei Zhang
Co-developed-by: Sai Prakash Ranjan
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/arm/coresight.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/coresi
This series adds support to skip powering up of trace unit on systems
with an errata which stops CPU watchdog counter when power up bit is
set (TRCPDCR.PU = 1). Setting this bit is not required on Qualcomm
Technologies Inc. chipsets where this errata exists since the ETMs
are in the same power
Hi Mathieu,
On 2020-05-14 23:30, Mathieu Poirier wrote:
Good morning Sai,
On Thu, May 14, 2020 at 04:29:15PM +0530, Sai Prakash Ranjan wrote:
From: Tingwei Zhang
On some Qualcomm Technologies Inc. SoCs like SC7180, there
exists a hardware errata where the APSS (Application Processor
, they are powered on when the
CPU core is powered on. So we can disable powering up of the
trace unit after checking for this errata via new property
called "qcom,tupwr-disable".
Signed-off-by: Tingwei Zhang
Co-developed-by: Sai Prakash Ranjan
Signed-off-by: Sai Prakash Ranjan
---
.../
On 2020-05-13 07:19, Stephen Boyd wrote:
Quoting Mike Leach (2020-05-12 14:52:33)
HI Sai,
On Tue, 12 May 2020 at 18:46, Sai Prakash Ranjan
wrote:
>
> Hi Mike,
>
> On 2020-05-12 17:19, Mike Leach wrote:
> [...]
>
> >> >>
> >> >> Sorry for h
Hi Mike,
On 2020-05-13 03:22, Mike Leach wrote:
[...]
Looking at the AMBA driver there is a comment there that AMBA does not
lose state when clocks are removed. This is consistent with the AMBA
protocol spec which states that AMBA slaves can only be accessed /
read / write on various strobe
Hi Mike,
On 2020-05-12 17:19, Mike Leach wrote:
[...]
>>
>> Sorry for hurrying up and sending the patch -
>> https://lore.kernel.org/patchwork/patch/1239923/.
>> I will send v2 based on further feedbacks here or there.
>>
>>>
>>> 1) does this replicator part have a unique ID that differs from
Hi Mathieu,
On 2020-05-11 21:49, Mathieu Poirier wrote:
Hi Sai,
On Mon, 11 May 2020 at 02:34, Sai Prakash Ranjan
wrote:
On some QCOM SoCs, replicators in Always-On domain loses its
context as soon as the clock is disabled. Currently as a part
of pm_runtime workqueue, clock is disabled after
Hi Suzuki,
On 2020-05-11 20:00, Suzuki K Poulose wrote:
On 05/11/2020 03:16 PM, Sai Prakash Ranjan wrote:
Hi Mike,
On 2020-05-11 16:44, Mike Leach wrote:
[...]
I checked with the debug team and there is a limitation with
the replicator(swao_replicator) in the AOSS group where it
loses
On 2020-05-11 19:46, Sai Prakash Ranjan wrote:
Hi Mike,
On 2020-05-11 16:44, Mike Leach wrote:
[...]
I checked with the debug team and there is a limitation with
the replicator(swao_replicator) in the AOSS group where it
loses the idfilter register context when the clock is disabled
Hi Mike,
On 2020-05-11 16:44, Mike Leach wrote:
[...]
I checked with the debug team and there is a limitation with
the replicator(swao_replicator) in the AOSS group where it
loses the idfilter register context when the clock is disabled.
This is not just in SC7180 SoC but also reported on
with such
limitations. Hence check the replicator idfilter registers
in dynamic_replicator_enable() and reset again.
Signed-off-by: Sai Prakash Ranjan
---
More info here - https://lore.kernel.org/patchwork/patch/1231182/
---
drivers/hwtracing/coresight/coresight-replicator.c | 11 +++
1
Hi Suzuki, Mike,
On 2020-05-06 13:05, Sai Prakash Ranjan wrote:
[...]
OK - sorry I read your statement saying that replicator1 was 0 after
the reset in probe(), rather than look at the logs.
From the logs it is working at the time probe() occurs, but by the
time we come to enable
Hi Robin,
On 2020-05-07 16:25, Robin Murphy wrote:
On 2020-05-07 11:14 am, Sai Prakash Ranjan wrote:
Hi Will, Robin
On 2020-04-22 01:50, Sai Prakash Ranjan wrote:
Add stall implementation hook to enable stalling
faults on QCOM platforms which supports it without
causing any kind of hardware
Hi Will,
On 2020-05-07 16:01, Will Deacon wrote:
On Thu, May 07, 2020 at 03:58:06PM +0530, Sai Prakash Ranjan wrote:
Hi Will, Joerg
On 2020-04-21 00:03, Sai Prakash Ranjan wrote:
> This series allows DRM, Modem devices to set a default
> identity mapping in qcom smmu implementation.
>
On 2020-05-07 16:03, Robin Murphy wrote:
On 2020-05-07 11:04 am, Sai Prakash Ranjan wrote:
Hi,
On 2020-05-07 05:40, Doug Anderson wrote:
Hi,
On Thu, Apr 23, 2020 at 7:35 AM Doug Anderson
wrote:
Hi,
On Thu, Apr 23, 2020 at 2:55 AM Sai Prakash Ranjan
wrote:
>
> Currently on
Hi Will, Joerg
On 2020-04-21 00:03, Sai Prakash Ranjan wrote:
This series allows DRM, Modem devices to set a default
identity mapping in qcom smmu implementation.
Patch 1 is cleanup to support other SoCs to call into
QCOM specific implementation.
Patch 2 sets the default identity domain
Hi Will, Robin
On 2020-04-22 01:50, Sai Prakash Ranjan wrote:
Add stall implementation hook to enable stalling
faults on QCOM platforms which supports it without
causing any kind of hardware mishaps. Without this
on QCOM platforms, GPU faults can cause unrelated
GPU memory accesses to return
Hi,
On 2020-05-07 05:40, Doug Anderson wrote:
Hi,
On Thu, Apr 23, 2020 at 7:35 AM Doug Anderson
wrote:
Hi,
On Thu, Apr 23, 2020 at 2:55 AM Sai Prakash Ranjan
wrote:
>
> Currently on reboot/shutdown, the following messages are
> displayed on the console as error messag
Hi Suzuki, Mike,
On 2020-04-29 22:41, Sai Prakash Ranjan wrote:
Hi Mike,
On 2020-04-29 22:28, Mike Leach wrote:
Hi,
[...]
>> > You need to find what is resetting the IDFILTERs to 0 for replicator1.
>> >
>>
>> That is right.
>>
>
> By default a
Hi Mike,
On 2020-04-29 22:28, Mike Leach wrote:
Hi,
[...]
>> > You need to find what is resetting the IDFILTERs to 0 for replicator1.
>> >
>>
>> That is right.
>>
>
> By default all replicators have the IDFILTER registers set to 0 out of
> hardware reset. This ensures that programmable
Hi Mike,
On 2020-04-29 19:57, Mike Leach wrote:
Hi,
[...]
>> Looking more into replicator1(swao_replicator) values as 0x0 even
>> after replicator_reset()
>> in replicator probe, I added dynamic_replicator_reset in
>> dynamic_replicator_enable()
>> and am not seeing any hardlockup. Also I
On 2020-04-29 19:19, Suzuki K Poulose wrote:
On 04/29/2020 12:47 PM, Sai Prakash Ranjan wrote:
On 2020-04-28 17:53, Sai Prakash Ranjan wrote:
On 2020-04-27 19:23, Suzuki K Poulose wrote:
On 04/27/2020 10:45 AM, Mike Leach wrote:
[...]
This is not sufficient. You must prevent another
On 2020-04-28 17:53, Sai Prakash Ranjan wrote:
On 2020-04-27 19:23, Suzuki K Poulose wrote:
On 04/27/2020 10:45 AM, Mike Leach wrote:
[...]
This is not sufficient. You must prevent another session trying to
enable the other port of the replicator as this could silently fail
the "on-
On 2020-04-27 19:23, Suzuki K Poulose wrote:
On 04/27/2020 10:45 AM, Mike Leach wrote:
[...]
This is not sufficient. You must prevent another session trying to
enable the other port of the replicator as this could silently fail
the "on-going" session. Not ideal. Fail the attempt to enable a
Add LLCC compatible for SC7180 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
b/Documentation/devicetree/bindings/arm/msm/qcom
on const
Sai Prakash Ranjan (2):
dt-bindings: msm: Convert LLCC bindings to YAML
dt-bindings: msm: Add LLCC for SC7180
Vivek Gautam (1):
soc: qcom: llcc: Add configuration data for SC7180
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 41 --
.../bindings/arm/msm/qcom,llcc.yaml
Convert LLCC bindings to DT schema format using json-schema.
Signed-off-by: Sai Prakash Ranjan
---
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 41 --
.../bindings/arm/msm/qcom,llcc.yaml | 54 +++
2 files changed, 54 insertions(+), 41 deletions
From: Vivek Gautam
Add LLCC configuration data for SC7180 SoC which controls
LLCC behaviour.
Signed-off-by: Vivek Gautam
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/llcc-qcom.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/qcom
On 2019-10-18 20:02, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2019-10-18 06:57:09)
Add LLCC compatible for SC7180 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Can you
On 2019-10-18 20:01, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2019-10-18 06:57:08)
diff --git a/drivers/soc/qcom/llcc-qcom.c
b/drivers/soc/qcom/llcc-qcom.c
index 4bd982a294ce..4acb52f8536b 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -91,6 +91,13
Add LLCC compatible for SC7180 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
b/Documentation/devicetree/bindings
LLCC behaviour is controlled by the configuration data set
in the llcc-qcom driver, add the same for SC7180 SoC.
Also add the compatible for SC7180.
The patch is based on linux-next where llcc driver has been
made generic and not sdm845 specific.
Sai Prakash Ranjan (1):
dt-bindings: msm: Add
From: Vivek Gautam
Add llcc configuration data for SC7180 SoC which controls
llcc behaviour.
Signed-off-by: Vivek Gautam
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/llcc-qcom.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b
On 2019-10-18 01:30, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2019-10-11 06:40:13)
On 2019-10-11 19:04, Marc Zyngier wrote:
> On Fri, 11 Oct 2019 18:47:39 +0530
> Sai Prakash Ranjan wrote:
>
>> Hi Mark,
>>
>> Thanks a lot for the detailed explanation
On 2019-10-11 19:04, Marc Zyngier wrote:
On Fri, 11 Oct 2019 18:47:39 +0530
Sai Prakash Ranjan wrote:
Hi Mark,
Thanks a lot for the detailed explanations, I did have a look at all
the variations before posting this.
On 2019-10-11 16:20, Mark Rutland wrote:
> Hi,
>
> On Fri, Oct
Hi Mark,
Thanks a lot for the detailed explanations, I did have a look at all the
variations before posting this.
On 2019-10-11 16:20, Mark Rutland wrote:
Hi,
On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai Prakash Ranjan wrote:
On latest QCOM SoCs like SM8150 and SC7180 with big.LITTLE arch
On latest QCOM SoCs like SM8150 and SC7180 with big.LITTLE arch, below
warnings are observed during bootup of big cpu cores.
SM8150:
[0.271177] CPU features: SANITY CHECK: Unexpected variation in
SYS_ID_AA64PFR0_EL1. Boot CPU: 0x00, CPU4: 0x001112
[0.271184] CPU
it only for MSM8998 MTP.
Reported-and-tested-by: Jeffrey Hugo
Fixes: 783abfa2249a ("arm64: dts: qcom: msm8998: Add Coresight support")
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi | 68 +++
arch/arm64/boot/dts/qcom/msm8998.dts
On 2019-10-01 11:01, Jeffrey Hugo wrote:
On Tue, Oct 1, 2019 at 11:52 AM Sai Prakash Ranjan
wrote:
Haan then likely it's the firmware issue.
We should probably disable coresight in soc dtsi and enable only for
MTP. For now you can add a status=disabled for all coresight nodes in
msm8998.dtsi
On 2019-10-01 10:14, Jeffrey Hugo wrote:
On Tue, Oct 1, 2019 at 11:04 AM Sai Prakash Ranjan
wrote:
On 2019-10-01 09:13, Jeffrey Hugo wrote:
> Sai,
>
> This patch breaks boot on the 835 laptops. However, I haven't seen
> the same issue on the MTP. I wonder, is coresight expe
On 2019-10-01 09:13, Jeffrey Hugo wrote:
Sai,
This patch breaks boot on the 835 laptops. However, I haven't seen
the same issue on the MTP. I wonder, is coresight expected to work
with production fused devices? I wonder if thats the difference
between the laptop and MTP that is causing the
On 2019-09-17 21:04, Raul Rangel wrote:
On Mon, Aug 26, 2019 at 02:24:14PM -0700, Stephen Boyd wrote:
>
> ---8<---
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index c0990703ce54..f42a803fb11a 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -3737,6 +3737,37 @@ static
on a patch by Bjorn Andersson.
Fixes: da0f0b2c3ad2 ("clk: Correct lookup logic in
clk_fetch_parent_index()")
Cc: Bjorn Andersson
Cc: Sai Prakash Ranjan
Signed-off-by: Stephen Boyd
---
drivers/clk/clk.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/dri
On 8/7/2019 3:42 PM, Suzuki K Poulose wrote:
Sai,
Any more tests you would want me to run?
Apologies for the late response. I had seen the results and they look fine.
I was hitting some issues, which I have now root caused to firmware issues.
So we are good to go.
Thanks Suzuki.
Hi
Hi Suzuki,
On 7/31/2019 11:35 AM, Sai Prakash Ranjan wrote:
Hi Suzuki,
On 7/31/2019 11:28 AM, Sai Prakash Ranjan wrote:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Acked-by: Suzuki K Poulose
---
arch/arm64/boot
Hi Suzuki,
On 7/31/2019 11:28 AM, Sai Prakash Ranjan wrote:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Acked-by: Suzuki K Poulose
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++
1 file
From: Vivek Gautam
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
Signed-off-by: Vivek Gautam
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Acked-by: Suzuki K Poulose
.
Sai Prakash Ranjan (2):
arm64: dts: qcom: sdm845: Add Coresight support
arm64: dts: qcom: msm8998: Add Coresight support
Vivek Gautam (1):
arm64: dts: qcom: msm8996: Add Coresight support
arch/arm64/boot/dts/qcom/msm8996.dtsi | 468 ++
arch/arm64/boot/dts/qcom
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Acked-by: Suzuki K Poulose
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++
1 file changed, 451 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on MSM8998.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Acked-by: Suzuki K Poulose
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 ++
1 file changed
On 7/26/2019 3:49 PM, Greg Kroah-Hartman wrote:
On Fri, Jul 26, 2019 at 03:44:40PM +0530, Sai Prakash Ranjan wrote:
On 7/26/2019 3:14 PM, Sai Prakash Ranjan wrote:
On 7/26/2019 2:11 PM, Greg Kroah-Hartman wrote:
On Fri, Jul 26, 2019 at 01:50:27PM +0530, Sai Prakash Ranjan wrote:
On 7/26/2019
On 7/26/2019 3:14 PM, Sai Prakash Ranjan wrote:
On 7/26/2019 2:11 PM, Greg Kroah-Hartman wrote:
On Fri, Jul 26, 2019 at 01:50:27PM +0530, Sai Prakash Ranjan wrote:
On 7/26/2019 12:34 PM, Greg Kroah-Hartman wrote:
On Fri, Jul 26, 2019 at 11:49:19AM +0530, Sai Prakash Ranjan wrote:
Hi,
When
On 7/26/2019 3:28 PM, Sai Prakash Ranjan wrote:
Hi Suzuki,
On 7/26/2019 2:58 PM, Suzuki K Poulose wrote:
On 07/26/2019 09:41 AM, Greg Kroah-Hartman wrote:
On Fri, Jul 26, 2019 at 01:50:27PM +0530, Sai Prakash Ranjan wrote:
On 7/26/2019 12:34 PM, Greg Kroah-Hartman wrote:
On Fri, Jul 26
Hi Suzuki,
On 7/26/2019 2:58 PM, Suzuki K Poulose wrote:
On 07/26/2019 09:41 AM, Greg Kroah-Hartman wrote:
On Fri, Jul 26, 2019 at 01:50:27PM +0530, Sai Prakash Ranjan wrote:
On 7/26/2019 12:34 PM, Greg Kroah-Hartman wrote:
On Fri, Jul 26, 2019 at 11:49:19AM +0530, Sai Prakash Ranjan wrote
On 7/26/2019 2:11 PM, Greg Kroah-Hartman wrote:
On Fri, Jul 26, 2019 at 01:50:27PM +0530, Sai Prakash Ranjan wrote:
On 7/26/2019 12:34 PM, Greg Kroah-Hartman wrote:
On Fri, Jul 26, 2019 at 11:49:19AM +0530, Sai Prakash Ranjan wrote:
Hi,
When trying to test my coresight patches, I found
On 7/26/2019 12:34 PM, Greg Kroah-Hartman wrote:
On Fri, Jul 26, 2019 at 11:49:19AM +0530, Sai Prakash Ranjan wrote:
Hi,
When trying to test my coresight patches, I found that etr,etf and stm
device nodes are missing from /dev.
I have no idea what those device nodes are.
Bisection gives
On 7/26/2019 11:49 AM, Sai Prakash Ranjan wrote:
Hi,
When trying to test my coresight patches, I found that etr,etf and stm
device nodes are missing from /dev.
Bisection gives this as the bad commit.
1be01d4a57142ded23bdb9e0c8d9369e693b26cc is the first bad commit
commit
Hi,
When trying to test my coresight patches, I found that etr,etf and stm
device nodes are missing from /dev.
Bisection gives this as the bad commit.
1be01d4a57142ded23bdb9e0c8d9369e693b26cc is the first bad commit
commit 1be01d4a57142ded23bdb9e0c8d9369e693b26cc
Author: Geert Uytterhoeven
On 7/21/2019 8:05 PM, Leo Yan wrote:
On Wed, Jul 17, 2019 at 10:56:02AM -0600, Mathieu Poirier wrote:
On Fri, Jul 12, 2019 at 07:46:27PM +0530, Sai Prakash Ranjan wrote:
Add support for coresight CPU debug module on Qualcomm
Kryo CPUs. This patch adds the UCI entries for Kryo CPUs
found
Hi Suzuki,
On 7/19/2019 3:16 PM, Suzuki K Poulose wrote:
Hi Sai,
On 12/07/2019 15:16, Sai Prakash Ranjan wrote:
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Mathieu Poirier
Acked-by: Suzuki K Poulose
---
arch/arm64/boot/dts/qcom
Hi,
On 7/18/2019 3:07 PM, Suzuki K Poulose wrote:
Using the sysfs doesn't guarantee that the ETR actually uses SG mode,
unless
the buffer size selected is > 1M, which is why I am more interested in the
perf usage. Alternatively you may configure a larger buffer size (say,
8MB) via:
echo
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