On Tue, Mar 16, 2021 at 12:29:16PM +0100, Jan Kara wrote:
> On Thu 04-03-21 13:35:38, Sascha Hauer wrote:
> > Current quotactl syscall uses a path to a block device to specify the
> > filesystem to work on which makes it unsuitable for filesystems that
> > do not have a bloc
On Wed, Mar 10, 2021 at 10:54:05AM +0800, dillon min wrote:
> Hi Sascha,
>
> Thanks for reviewing.
>
> On Tue, Mar 9, 2021 at 8:18 PM Sascha Hauer wrote:
> >
> > On Tue, Mar 09, 2021 at 02:15:19PM +0800, dillon.min...@gmail.com wrote:
> > > From: dillon min
On Tue, Mar 09, 2021 at 02:15:19PM +0800, dillon.min...@gmail.com wrote:
> From: dillon min
>
> This patch intend to fix ubi filesystem mount failed on MYS-6ULX-IOT board,
> from Micron MT29F2G08ABAEAWP's datasheets, we need to choose 4-bit ECC.
>
> Table 18: Error Management Details
>
>
. quotactl_path replaces the path
to the block device with a path where the filesystem is mounted at.
The global Q_SYNC command to sync all filesystems is not supported for
this new syscall, otherwise quotactl_path behaves like quotactl.
Signed-off-by: Sascha Hauer
Reviewed-by: Christoph Hellwig
en inodes
for quota metadata storage
- Drop unnecessary quotactl_cmd_onoff() check
Sascha Hauer (2):
quota: Add mountpath based quota support
quota: wire up quotactl_path
arch/alpha/kernel/syscalls/syscall.tbl | 1 +
arch/arm/tools/syscall.tbl | 1 +
arch/arm64/include/asm
Expand the quotactl.2 manpage with a description for quotactl_path()
that takes a mountpoint path instead of a path to a block device.
Signed-off-by: Sascha Hauer
---
man2/quotactl.2 | 31 ---
man2/quotactl_path.2 | 1 +
2 files changed, 29 insertions(+), 3
Wire up the quotactl_path syscall added in the previous patch.
Signed-off-by: Sascha Hauer
Reviewed-by: Christoph Hellwig
---
arch/alpha/kernel/syscalls/syscall.tbl | 1 +
arch/arm/tools/syscall.tbl | 1 +
arch/arm64/include/asm/unistd.h | 2 +-
arch/arm64
ecryptfs_decrypt_page() issues a warning "Error encrypting extent". This
should be "Error decrypting extent" instead.
Signed-off-by: Sascha Hauer
---
fs/ecryptfs/crypto.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/ecryptfs/crypto.c b/fs/ecr
On Fri, Feb 12, 2021 at 11:05:05AM +0100, Jan Kara wrote:
> On Fri 12-02-21 09:38:35, Sascha Hauer wrote:
> > On Thu, Feb 11, 2021 at 03:38:13PM +, Christoph Hellwig wrote:
> > > > + if (!mountpoint)
> > > > + return -ENODEV;
> > &
On Thu, Feb 11, 2021 at 03:38:13PM +, Christoph Hellwig wrote:
> > + if (!mountpoint)
> > + return -ENODEV;
> > +
> > + ret = user_path_at(AT_FDCWD, mountpoint,
> > +LOOKUP_FOLLOW | LOOKUP_AUTOMOUNT, );
>
> user_path_at handles an empty path, although
. quotactl_path replaces the path
to the block device with a path where the filesystem is mounted at.
The global Q_SYNC command to sync all filesystems is not supported for
this new syscall, otherwise quotactl_path behaves like quotactl.
Signed-off-by: Sascha Hauer
---
fs/quota/quota.c | 49
Wire up the quotactl_path syscall added in the previous patch.
Signed-off-by: Sascha Hauer
---
arch/alpha/kernel/syscalls/syscall.tbl | 1 +
arch/arm/tools/syscall.tbl | 1 +
arch/arm64/include/asm/unistd.h | 2 +-
arch/arm64/include/asm/unistd32.h
. With this quotactl_path() can
only do the Q_QUOTAON operation on filesystems which use hidden inodes
for quota metadata storage
- Drop unnecessary quotactl_cmd_onoff() check
Sascha Hauer (2):
quota: Add mountpath based quota support
quota: wire up quotactl_path
arch/alpha/kernel/syscalls/syscall.tbl | 1
Expand the quotactl.2 manpage with a description for quotactl_path()
that takes a mountpoint path instead of a path to a block device.
Signed-off-by: Sascha Hauer
---
man2/quotactl.2 | 31 ---
man2/quotactl_path.2 | 1 +
2 files changed, 29 insertions(+), 3
Hi Dan,
On Mon, Feb 08, 2021 at 04:45:17PM +0300, Dan Carpenter wrote:
> On Sun, Feb 07, 2021 at 05:23:28PM +0800, Youling Tang wrote:
> > Fix the below ignoring return value warning for device_reset.
> >
> > drivers/staging/mt7621-dma/mtk-hsdma.c:685:2: warning: ignoring return value
> > of
On Sun, Feb 07, 2021 at 05:23:28PM +0800, Youling Tang wrote:
> Fix the below ignoring return value warning for device_reset.
>
> drivers/staging/mt7621-dma/mtk-hsdma.c:685:2: warning: ignoring return value
> of function declared with 'warn_unused_result' attribute [-Wunused-result]
>
the full UBIFS quota series here as it remains unchanged
and I'd like to get feedback to the new syscall first. For those interested
the most recent series can be found here: https://lwn.net/Articles/810463/
Sascha
Sascha Hauer (2):
quota: Add mountpath based quota support
quota: wire up
. quotactl_path replaces the path
to the block device with a path where the filesystem is mounted at.
The global Q_SYNC command to sync all filesystems is not supported for
this new syscall, otherwise quotactl_path behaves like quotactl.
Signed-off-by: Sascha Hauer
---
fs/quota/quota.c | 77
Expand the quotactl.2 manpage with a description for quotactl_path()
that takes a mountpoint path instead of a path to a block device.
Signed-off-by: Sascha Hauer
---
man2/quotactl.2 | 19 +--
man2/quotactl_path.2 | 1 +
2 files changed, 18 insertions(+), 2 deletions
Wire up the quotactl_path syscall added in the previous patch.
Signed-off-by: Sascha Hauer
---
arch/alpha/kernel/syscalls/syscall.tbl | 1 +
arch/arm/tools/syscall.tbl | 1 +
arch/arm64/include/asm/unistd.h | 2 +-
arch/arm64/include/asm/unistd32.h
On Wed, Jan 27, 2021 at 12:12:20PM +0200, Abel Vesa wrote:
> On 21-01-26 15:30:17, Sascha Hauer wrote:
> > On Tue, Jan 26, 2021 at 03:12:39PM +0200, Abel Vesa wrote:
> > > On 21-01-26 12:51:05, Sascha Hauer wrote:
> > > > On Tue, Jan 26, 2021 at 01:21:36PM +0200, A
On Tue, Jan 26, 2021 at 03:12:39PM +0200, Abel Vesa wrote:
> On 21-01-26 12:51:05, Sascha Hauer wrote:
> > On Tue, Jan 26, 2021 at 01:21:36PM +0200, Abel Vesa wrote:
> > > Some clocks are already enabled in HW even before the kernel
> > > starts to boot. So, in order to
On Tue, Jan 26, 2021 at 01:21:36PM +0200, Abel Vesa wrote:
> Some clocks are already enabled in HW even before the kernel
> starts to boot. So, in order to make sure that these clocks do not
> get disabled when clk_disable_unused call is done or when
> reparenting clocks, we enable them in core on
On Wed, Jan 20, 2021 at 06:14:21PM +0200, Abel Vesa wrote:
> On 21-01-20 16:50:01, Sascha Hauer wrote:
> > On Wed, Jan 20, 2021 at 05:28:13PM +0200, Abel Vesa wrote:
> > > On 21-01-20 16:13:05, Sascha Hauer wrote:
> > > > Hi Abel,
> > > >
> > &g
On Wed, Jan 20, 2021 at 05:28:13PM +0200, Abel Vesa wrote:
> On 21-01-20 16:13:05, Sascha Hauer wrote:
> > Hi Abel,
> >
> > On Wed, Jan 20, 2021 at 04:44:54PM +0200, Abel Vesa wrote:
> > > On 21-01-18 08:00:43, Adam Ford wrote:
> > > > On Mon
Hi Abel,
On Wed, Jan 20, 2021 at 04:44:54PM +0200, Abel Vesa wrote:
> On 21-01-18 08:00:43, Adam Ford wrote:
> > On Mon, Jan 18, 2021 at 6:52 AM Abel Vesa wrote:
> > >
> > > On 21-01-15 12:29:08, Adam Ford wrote:
> > >
> > > ...
> > >
> > > > diff --git a/drivers/clk/imx/clk-imx25.c
Hi Adam,
On Tue, Dec 29, 2020 at 08:51:28AM -0600, Adam Ford wrote:
> Remove the earlycon uart clocks that are hard cord in platforms
> clock driver, instead of parsing the earlycon uart port from dt
"instead parse the earlycon uart..."
Otherwise it's confusing what you mean here.
> and enable
Hi Adam,
On Mon, Dec 07, 2020 at 09:51:33AM -0600, Adam Ford wrote:
> On Sun, Dec 6, 2020 at 11:24 PM Sascha Hauer wrote:
> >
> > Hi Adam,
> >
> > On Fri, Dec 04, 2020 at 12:31:54PM -0600, Adam Ford wrote:
> > > The default clock source on i.MX8M Mi
Hi Adam,
On Fri, Dec 04, 2020 at 12:31:54PM -0600, Adam Ford wrote:
> The default clock source on i.MX8M Mini and Nano boards use a 24MHz clock,
> but users who need to re-parent the clock source run into issues because
> all the UART clocks are enabled whether or not they're needed by sdout.
>
it only works when we are waiting for the bit to clear.
Signed-off-by: Sascha Hauer
---
I've already sent this in October without any reaction, this is just a
resend with +Cc Stephen Boyd and +Cc linux-kernel@vger.kernel.org
drivers/clk/clk-si5351.c | 13 ++---
1 file changed, 10
ot;ubifs: Add helper functions for authentication
> support")
> Signed-off-by: Wang ShaoBo
> ---
> fs/ubifs/auth.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Sascha Hauer
Sascha
>
> diff --git a/fs/ubifs/auth.c b/fs/ubifs/auth.c
> index b
> Signed-off-by: Wang ShaoBo
> ---
> fs/ubifs/super.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Prefix for this patch should be "ubifs:" rather than "bdi:". With this:
Reviewed-by: Sascha Hauer
Sascha
>
> diff --git a/fs/ubifs/super.c
On Tue, Nov 17, 2020 at 11:16:26AM +0100, Juergen Borleis wrote:
> Hi,
>
> reading a NAND page in raw mode is required to check the consistence of the
> so-
> called FCBs (used to boot the SoC from NAND content).
>
> Before e5e5631cc88987a6f3cd8304660bd9190da95916 ("mtd: rawnand: gpmi: Use
>
ial case
> clk: imx: gate2: Keep the register writing in on place
> clk: imx: gate2: Check if clock is enabled against cgr_val
> clk: imx: gate2: Add cgr_mask for more flexible number of control bits
> clk: imx: gate2: Add locking in is_enabled op
For the series:
Reviewed-by: Sasch
On Wed, Oct 28, 2020 at 11:50:57AM +0200, Abel Vesa wrote:
> On 20-10-28 09:24:12, Sascha Hauer wrote:
> > Hi Abel,
> >
> > On Mon, Oct 26, 2020 at 08:50:48PM +0200, Abel Vesa wrote:
> > > The clock is considered to be enabled only if the controlling bits
> >
Hi Abel,
On Mon, Oct 26, 2020 at 08:50:48PM +0200, Abel Vesa wrote:
> The clock is considered to be enabled only if the controlling bits
> match the cgr_val mask. Also make sure the is_enabled returns the
> correct vaule by locking the access to the register.
>
> Signed-off-by: Abel Vesa
>
On Fri, Oct 09, 2020 at 09:48:29AM +0200, Christian Eggers wrote:
> Hi Sascha,
>
> On Friday, 9 October 2020, 09:39:44 CEST, Sascha Hauer wrote:
> > On Fri, Oct 09, 2020 at 06:27:38AM +0200, Christian Eggers wrote:
> > > This reverts commit 525c9e5a32bd7951
On Mon, Oct 12, 2020 at 12:59:34PM +0200, Christian Eggers wrote:
> Hi Sascha,
>
> On Friday, 9 October 2020, 09:39:44 CEST, Sascha Hauer wrote:
> > On Fri, Oct 09, 2020 at 06:27:38AM +0200, Christian Eggers wrote:
> > > This reverts commit 525c9e5a32bd7951
On Fri, Oct 09, 2020 at 06:27:38AM +0200, Christian Eggers wrote:
> This reverts commit 525c9e5a32bd7951eae3f06d9d077fea51718a6c.
>
> If CONFIG_PM is disabled, the system completely freezes on probe as
> nothing enables the clock of the SPI peripheral.
Instead of reverting it, why not just fix
On Tue, Sep 29, 2020 at 08:45:29PM +0800, Zhihao Cheng wrote:
> Fix a memory leak after dumping authentication mount options in error
> handling branch.
>
> Signed-off-by: Zhihao Cheng
> Cc: # 4.20+
> Fixes: d8a22773a12c6d7 ("ubifs: Enable authentication support"
cause memory leak if UBIFS has already been
> mounted with old authentication mount options.
>
> Signed-off-by: Zhihao Cheng
> Cc: # 4.20+
> Fixes: d8a22773a12c6d7 ("ubifs: Enable authentication support")
Reviewed-by: Sascha Hauer
Sascha
> ---
> fs/ubifs/super.
On Tue, Sep 29, 2020 at 08:45:31PM +0800, Zhihao Cheng wrote:
> Release the authentication related resource in some error handling
> branches in mount_ubifs().
>
> Signed-off-by: Zhihao Cheng
> Cc: # 4.20+
> Fixes: d8a22773a12c6d7 ("ubifs: Enable authentication support
On Mon, Sep 28, 2020 at 09:06:12PM +0200, Richard Weinberger wrote:
> When removing the last reference of an inode the size of an auth node
> is already part of write_len. So we must not call ubifs_add_auth_dirt().
> Call it only when needed.
>
> Cc:
> Cc: Sascha Hauer
&g
Hi Sasha,
On Mon, Sep 28, 2020 at 09:30:25PM -0400, Sasha Levin wrote:
> From: Sascha Hauer
>
> [ Upstream commit 530b5affc675ade5db4a03f04ed7cd66806c8a1a ]
>
> spi_unregister_controller() not only unregisters the controller, but
> also frees the controller. This will fr
tempted to kill init!
> > exitcode=0x000b ]---
> >
> > This is because since this commit, the allocation of the drivers private
> > data is done explicitly and in this case spi_alloc_master() won't set the
> > c
On Mon, Aug 24, 2020 at 09:06:47PM +0200, Krzysztof Kozlowski wrote:
> Driver requires different amount of clocks for different SoCs. Describe
> these requirements properly to fix dtbs_check warnings like:
>
> arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dt.yaml:
>
On Fri, Aug 21, 2020 at 09:52:00AM +, Robin Gong wrote:
> On 2020/08/20 14:52 Sascha Hauer wrote:
> > On Wed, Aug 19, 2020 at 01:08:29PM +0200, Lars-Peter Clausen wrote:
> > > > For the first option, which is potentially more performant, we have
> > > > to le
On Mon, Aug 24, 2020 at 06:26:46PM +0200, Krzysztof Kozlowski wrote:
> +oneOf:
> + - items:
> + - enum:
> + - fsl,imx6q-ocotp
> + - fsl,imx6sl-ocotp
> + - fsl,imx6sx-ocotp
> + - fsl,imx6ul-ocotp
> + -
On Mon, Aug 24, 2020 at 08:38:06AM +0200, Krzysztof Kozlowski wrote:
> On Mon, Aug 24, 2020 at 07:24:46AM +0200, Sascha Hauer wrote:
> > On Sun, Aug 23, 2020 at 06:15:30PM +0200, Krzysztof Kozlowski wrote:
> > > The GPIO controller node can have gpio-ranges property. This fixe
The subject contains a "imx-pwm", presumably from the last patch.
Sascha
On Sun, Aug 23, 2020 at 06:15:35PM +0200, Krzysztof Kozlowski wrote:
> DTSes with new i.MX 8M SoCs introduce their own compatibles so add them
> to fix dtbs_check warnings like:
>
>
On Sun, Aug 23, 2020 at 06:15:30PM +0200, Krzysztof Kozlowski wrote:
> The GPIO controller node can have gpio-ranges property. This fixes
> dtbs_check warnings like:
>
> arch/arm64/boot/dts/freescale/imx8mm-evk.dt.yaml: gpio@3020:
> 'gpio-ranges' does not match any of the regexes:
From: Sven Schneider
This font is derived from lib/fonts/font_6x10.c and is useful for small
OLED displays
Signed-off-by: Sven Schneider
Signed-off-by: Sascha Hauer
---
Changes since v1:
- re-added lost Signed-off-by lines
- do not mode change include/linux/font.h to 0755
- Add SPDX tag
From: Sven Schneider
This font is derived from lib/fonts/font_6x10.c and is useful for small OLED
displays.
---
Hi All,
I am not sure any new fonts are desired in the kernel. If yes, please consider
for inclusion, otherwise some "go away, there are enough fonts in the kernel
already" would be
On Wed, Aug 19, 2020 at 01:08:29PM +0200, Lars-Peter Clausen wrote:
> > For the first option, which is potentially more performant, we have to
> > leave the atomic PCM context
> > and we are not sure if we are allowed to.
> > For the second option, we would have to divide the dma_device
for valid interface modes early so that
later in the driver we do not have to care for unexpected interface
modes.
Add back the test to let the driver bail out early on unhandled
interface modes.
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 22 +++---
1 file
SolidRun Clearfog:
WARNING: CPU: 0 PID: 268 at drivers/net/ethernet/marvell/mvneta.c:3512
mvneta_start_dev+0x220/0x23c
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
On Tue, Jun 23, 2020 at 12:53:40AM +0100, Russell King - ARM Linux admin wrote:
> On Tue, Jun 16, 2020 at 10:31:39AM +0200, Sascha Hauer wrote:
> > The MVNETA_SERDES_CFG register is only available on older SoCs like the
> > Armada XP. On newer SoCs like the Armada 38x the f
writing the correct magic value into
the MVNETA_SERDES_CFG register.
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 9933eb4577d43
is configured.
With this we no longer write to the MVNETA_SERDES_CFG on SoCs where it
doesn't exist.
Suggested-by: Russell King
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 80 +++
1 file changed, 44 insertions(+), 36 deletions(-)
diff --git
Jun 12, 2020 at 10:38:47AM +0200, Sascha Hauer wrote:
> > > > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > > > called DRSGMII. Depending on the Port MAC Control Register0 PortType
> > > > setting this seems to be either an overcl
On Fri, Jun 12, 2020 at 12:30:31PM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 12, 2020 at 12:22:13PM +0100, Russell King - ARM Linux admin
> wrote:
> > On Fri, Jun 12, 2020 at 11:42:08AM +0100, Russell King - ARM Linux admin
> > wrote:
> > > With the obvious mistakes fixed
On Fri, Jun 12, 2020 at 09:47:10AM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 12, 2020 at 10:38:47AM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > called DRSGMII. Depending on the Port MAC Control Reg
() to differentiate the different
possibilities.
Fixes: da58a931f248f ("net: mvneta: Add support for 2500Mbps SGMII")
Signed-off-by: Sascha Hauer
---
Changes since v1:
- Add Fixes: tag
drivers/net/ethernet/marvell/mvneta.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Hi Andrew,
+Cc Maxime Chevallier
On Tue, Jun 09, 2020 at 03:28:48PM +0200, Andrew Lunn wrote:
> On Tue, Jun 09, 2020 at 03:11:52PM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > called DRSGMII. Depending on the Port MAC Co
Hi Andrew,
On Tue, Jun 09, 2020 at 03:12:16PM +0200, Andrew Lunn wrote:
> On Tue, Jun 09, 2020 at 02:55:35PM +0200, Sascha Hauer wrote:
> > On Mon, Jun 08, 2020 at 04:57:37PM +0200, Andrew Lunn wrote:
> > > On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> >
() to differentiate the different
possibilities.
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 51889770958d8..3b13048931412
On Mon, Jun 08, 2020 at 04:57:37PM +0200, Andrew Lunn wrote:
> On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode
> > called DRSGMII.
> >
> > This patch adds a corresponding phy-mode
On Mon, Jun 08, 2020 at 05:08:01PM +0100, Russell King - ARM Linux admin wrote:
> On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode
> > called DRSGMII.
> >
> > This patch adds a co
.
Signed-off-by: Sascha Hauer
---
.../devicetree/bindings/net/ethernet-controller.yaml | 1 +
drivers/net/ethernet/marvell/mvneta.c | 7 ++-
include/linux/phy.h| 3 +++
3 files changed, 10 insertions(+), 1 deletion(-)
This patch
Hi,
On Mon, Jun 01, 2020 at 05:11:34PM +0800, Zhihao Cheng wrote:
> Following process triggers a memleak caused by forgetting to release the
> initial anchor PEB (CONFIG_MTD_UBI_FASTMAP is disabled):
> 1. attach -> __erase_worker -> produce the initial anchor PEB
> 2. detach -> ubi_fastmap_close
> seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
> have the chance to test this patch set if could fix their issues.
> Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> on i.mx8mm because the event id is zero.
For the series:
Acke
On Wed, May 13, 2020 at 08:52:39AM +, Robin Gong wrote:
> On 2020/05/13 16:48 Sascha Hauer wrote:
> > On Wed, May 13, 2020 at 08:38:26AM +, Robin Gong wrote:
> > > On 2020/05/13 Sascha Hauer wrote:
> > > > This patch is the one bisecting will
On Wed, May 13, 2020 at 09:05:33AM +, Robin Gong wrote:
> On 2020/05/13 Sascha Hauer wrote:d
> > > drivers/spi/spi-imx.c | 16
> > > 1 file changed, 8 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/spi/spi-imx.c b/dr
On Wed, May 13, 2020 at 08:38:26AM +, Robin Gong wrote:
> On 2020/05/13 Sascha Hauer wrote:
> > This patch is the one bisecting will end up with when somebody uses an older
> > SDMA firmware or the ROM scripts. It should have a better description what
> > happens and what
On Tue, May 12, 2020 at 01:32:30AM +0800, Robin Gong wrote:
> Change to XCH mode even in dma mode, please refer to the below
> errata:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
>
> Signed-off-by: Robin Gong
> Acked-by: Mark Brown
> ---
> drivers/spi/spi-imx.c | 16
>
On Tue, May 12, 2020 at 01:32:30AM +0800, Robin Gong wrote:
> Change to XCH mode even in dma mode, please refer to the below
> errata:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
This patch is the one bisecting will end up with when somebody uses an
older SDMA firmware or the ROM scripts.
On Tue, May 12, 2020 at 01:32:23AM +0800, Robin Gong wrote:
> There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> transfer to be send twice in DMA mode. Please get more information from:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
> new sdma ram
On Tue, May 12, 2020 at 01:32:26AM +0800, Robin Gong wrote:
> This reverts commit d288bddd8374e0a043ac9dde64a1ae6a09411d74, since
> 'context_loaded' finally removed.
>
> Signed-off-by: Robin Gong
> ---
> drivers/dma/imx-sdma.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git
In the subject: s/dupilicated/duplicated/
Sascha
On Tue, May 12, 2020 at 01:32:28AM +0800, Robin Gong wrote:
> Since sdma_transfer_init() will do sdma_load_context before any
> sdma transfer, no need once more in sdma_config_channel().
>
> Signed-off-by: Robin Gong
> Acked-by: Vinod Koul
>
On Sun, May 10, 2020 at 07:02:13PM +0800, zhoubo...@foxmail.com wrote:
> From: To-run-away
>
> Increase the use of dm9000 to initialize the SROM_BANK clock in the SOC,
> otherwise the chip will not work.
The dm9000 doesn't have anything called SROM in it. You have to
describe the clock input
Positions of the entries in nv_port_info[] must be consistent to enum
nv_host_type. Ensure this by using the enum as array index directly.
Signed-off-by: Sascha Hauer
---
drivers/ata/sata_nv.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/ata
On Sun, May 03, 2020 at 11:46:27PM +0200, Pali Rohár wrote:
> On Monday 27 January 2020 12:24:28 Sascha Hauer wrote:
> > On Mon, Jan 27, 2020 at 12:16:30PM +0100, Pali Rohár wrote:
> > > On Monday 06 January 2020 09:16:05 Sascha Hauer wrote:
> > > > On Wed, Dec 25,
On Fri, Aug 09, 2019 at 04:04:45AM +, Biwen Li wrote:
> >
> > Hi,
> >
> > On Thu, Aug 08, 2019 at 11:53:43AM +0800, Biwen Li wrote:
> > > The patch supports slave mode for imx I2C driver
> > >
> > > Signed-off-by: Biwen Li
> > > ---
> > > drivers/i2c/busses/i2c-imx.c | 199
> > >
Hi,
On Thu, Aug 08, 2019 at 11:53:43AM +0800, Biwen Li wrote:
> The patch supports slave mode for imx I2C driver
>
> Signed-off-by: Biwen Li
> ---
> drivers/i2c/busses/i2c-imx.c | 199 ---
> 1 file changed, 185 insertions(+), 14 deletions(-)
>
> diff --git
On Tue, Jul 02, 2019 at 05:54:54PM +0100, Srinivas Kandagatla wrote:
> Hi Sascha,
>
> On 01/07/2019 09:06, Sascha Hauer wrote:
> > Hi Srinivas,
> >
> > On Tue, May 21, 2019 at 11:21:07AM +0200, Sascha Hauer wrote:
> > > On Tue, May 21, 2019 at 10:02:3
Hi Srinivas,
On Tue, May 21, 2019 at 11:21:07AM +0200, Sascha Hauer wrote:
> On Tue, May 21, 2019 at 10:02:32AM +0100, Srinivas Kandagatla wrote:
> >
> >
> > On 21/05/2019 09:56, Sascha Hauer wrote:
> > > . Are there any suggestions how to register the nvmem devic
Hi,
On Fri, Jun 14, 2019 at 09:23:48AM +0200, Sascha Hauer wrote:
> First two patches are a fix for the Marvell HCI driver which fails to
> properly upload the firmware. Third patch adds simple serdev support
> to the driver.
>
> Sascha
>
> Sascha Hauer (3):
> B
First two patches are a fix for the Marvell HCI driver which fails to
properly upload the firmware. Third patch adds simple serdev support
to the driver.
Sascha
Sascha Hauer (3):
Bluetooth: hci_ldisc: Add function to wait for characters to be sent
Bluetooth: hci_mrvl: Wait for final ack
this final ack with the old baudrate give the hci
ldisc workqueue a chance to run before switching the baudrate. Without
this the final ack will never be received by the device and firmware
upload fails.
Signed-off-by: Sascha Hauer
---
drivers/bluetooth/hci_mrvl.c | 3 +++
1 file changed, 3 insertions
The hci UART line discipline sends its characters in a workqueue. Some
devices like the Marvell Bluetooth chips need to make sure that all
queued characters are sent before switching the baudrate. This adds
a function to synchronize with the workqueue.
Signed-off-by: Sascha Hauer
---
drivers
This adds serdev support to the Marvell hci uart driver. Only basic
serdev support, none of the fancier features like regulator or enable
GPIO support is added for now.
Signed-off-by: Sascha Hauer
---
.../bindings/net/marvell-bluetooth.txt| 25 +++
drivers/bluetooth/Kconfig
On Mon, May 27, 2019 at 04:51:15PM +0800, yibin.g...@nxp.com wrote:
> From: Robin Gong
>
> The next v3 i.mx7ulp edma is based on v1, so change version
> check logic for v2 instead.
>
> Signed-off-by: Robin Gong
> ---
> drivers/dma/fsl-edma-common.c | 40
On Mon, May 27, 2019 at 04:51:17PM +0800, yibin.g...@nxp.com wrote:
> From: Robin Gong
>
> +static const struct of_device_id fsl_edma_dt_ids[] = {
> + { .compatible = "fsl,vf610-edma", .data = (void *)v1 },
> + { .compatible = "fsl,imx7ulp-edma", .data = (void *)v3 },
> + { /*
On Tue, May 21, 2019 at 10:02:32AM +0100, Srinivas Kandagatla wrote:
>
>
> On 21/05/2019 09:56, Sascha Hauer wrote:
> > . Are there any suggestions how to register the nvmem devices
> > with a different name?
>
> struct nvmem_config provides id field for this
Hi all,
nvmem derives the device name directly from the partition name of the
underlying device. IMO this is wrong since it's not possible to create
two partitions with the same name on different devices. In my case I
have a NAND device and a SPI NOR device which both happen to have a
partition
The Kernel has nice hexdump facilities, use them rather a homebrew
hexdump function.
Signed-off-by: Sascha Hauer
---
fs/ecryptfs/debug.c | 22 +++---
1 file changed, 3 insertions(+), 19 deletions(-)
diff --git a/fs/ecryptfs/debug.c b/fs/ecryptfs/debug.c
index 3d2bdf546ec6
On Thu, May 09, 2019 at 04:35:33AM +, Sumit Batra wrote:
> > > > So the clock driver reports the wrong clock. Please fix the clock
> > > > driver then.
> > > No, this is a problem with the i2c driver. It is not a problem with
> > > the clock driver, so the i2c driver needs to be modified.
>
Hi,
In case we end up with the handling of this issue in the i2c driver,
here are the things to consider for v2.
On Tue, Apr 30, 2019 at 12:47:18PM +0800, Chuanhua Han wrote:
> The current kernel driver does not consider I2C_IPGCLK_SEL (424 bit
> of RCW) in deciding i2c_clk_rate in function
On Tue, Apr 30, 2019 at 12:47:19PM +0800, Chuanhua Han wrote:
> For NXP ls1046a SoC, the i2c clock needs to be configured with the
> appropriate bit of RCW, so we add the guts node (GUTS/DCFG global
> utilities block) for the driver to read.
>
> Signed-off-by: Sumit Batra
> Signed-off-by:
On Sat, May 04, 2019 at 09:28:48AM +, Chuanhua Han wrote:
>
>
> > -Original Message-
> > From: Sascha Hauer
> > Sent: 2019年4月30日 20:51
> > To: Chuanhua Han
> > Cc: shawn...@kernel.org; Leo Li ; robh...@kernel.org;
> > mark.rutl...@arm.co
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