[PATCH v2 16/20] bus: cdmm: Add MIPS R5 arch support

2020-05-06 Thread Sergey.Semin
From: Serge Semin CDMM may be available not only MIPS R2 architectures, but also in newer MIPS R5 chips. For instance our P5600 chip has one. Lets mark the CDMM bus being supported for that MIPS arch too. Co-developed-by: Alexey Malahov Signed-off-by: Alexey Malahov Signed-off-by: Serge Semin

[PATCH v2 20/20] cpufreq: Return zero on success in boost sw setting

2020-05-06 Thread Sergey.Semin
From: Serge Semin Recent commit e61a41256edf ("cpufreq: dev_pm_qos_update_request() can return 1 on success") fixed a problem when active policies traverse was falsely stopped due to invalidly treating the non-zero return value from freq_qos_update_request() method as an error. Yes, that

[PATCH v2 17/20] mips: Add udelay lpj numbers adjustment

2020-05-06 Thread Sergey.Semin
From: Serge Semin Loops-per-jiffies is a special number which represents a number of noop-loop cycles per CPU-scheduler quantum - jiffies. As you understand aside from CPU-specific implementation it depends on the CPU frequency. So when a platform has the CPU frequency fixed, we have no problem

[PATCH v2 19/20] mips: cevt-r4k: Update the r4k-clockevent frequency in sync with CPU

2020-05-06 Thread Sergey.Semin
From: Serge Semin Due to being embedded into the CPU cores MIPS count/compare timer frequency is changed together with the CPU clocks alteration. In case if frequency really changes the kernel clockevent framework must be notified, otherwise the kernel timers won't work correctly. Fix this by

[PATCH v2 14/20] mips: Use offset-sized IO-mem accessors in CPS debug printout

2020-05-06 Thread Sergey.Semin
From: Serge Semin Similar to commit 8e5c62e38a88 ("mips: early_printk_8250: Use offset-sized IO-mem accessors") the IO-memory might require to use a proper load/store instructions (like Bailal-T1 IO-memory). To fix the cps-vec UART debug printout lets use the memory access instructions in

[PATCH v2 18/20] mips: csrc-r4k: Decrease r4k-clocksource rating if CPU_FREQ enabled

2020-05-06 Thread Sergey.Semin
From: Serge Semin Commit 07d69579e7fe ("MIPS: Don't register r4k sched clock when CPUFREQ enabled") disabled the r4k-clock usage for scheduler ticks counting due to the scheduler being non-tolerant for unstable clocks sources. For the same reason the clock should be used in the system

[PATCH v2 13/20] mips: early_printk_8250: Use offset-sized IO-mem accessors

2020-05-06 Thread Sergey.Semin
From: Serge Semin Some platforms may prohibit to access the IO-memory with instructions of certain memory widths. For instance Bailal-T1 has devices placed behind memory OCP port (which also the reason of DMA accesses being incoherent) and can't be accessed through CCA uncacheable memory with

[PATCH v2 12/20] mips: MAAR: Add XPA mode support

2020-05-06 Thread Sergey.Semin
From: Serge Semin When XPA mode is enabled the normally 32-bits MAAR pair registers are extended to be of 64-bits width as in pure 64-bits MIPS architecture. In this case the MAAR registers can enable the speculative loads/stores for addresses of up to 39-bits width. But in this case the process

[PATCH v2 15/20] mips: cdmm: Add mti,mips-cdmm dtb node support

2020-05-06 Thread Sergey.Semin
From: Serge Semin Since having and mapping the CDMM block is platform specific, then instead of just returning a zero-address, lets make the default CDMM base address search method (mips_cdmm_phys_base()) to do something useful. For instance to find the address in a dedicated dtb-node in order

[PATCH v2 11/20] mips: MAAR: Use more precise address mask

2020-05-06 Thread Sergey.Semin
From: Serge Semin Indeed according to the P5600/P6000 manual the MAAR pair register address field either takes [12:31] bits for 32-bits non-XPA systems and [12:35] otherwise. In any case the current address mask is just wrong for 64-bit and 32-bits XPA chips. So lets extend it to 39-bits value.

[PATCH v2 02/20] dt-bindings: bus: Add MIPS CDMM controller

2020-05-06 Thread Sergey.Semin
From: Serge Semin It's a Common Device Memory Map controller embedded into the MIPS IP cores, which dts node is supposed to have compatible and reg properties. Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Arnd Bergmann Cc:

[PATCH v2 07/20] mips: Add MIPS Warrior P5600 support

2020-05-06 Thread Sergey.Semin
From: Serge Semin This is a MIPS32 Release 5 based IP core with XPA, EVA, dual/quad issue exec pipes, MMU with two-levels TLB, UCA, MSA, MDU core level features and system level features like up to six P5600 calculation cores, CM2 with L2 cache, IOCU/IOMMU (though might be unused depending on

[PATCH v2 06/20] mips: Add MIPS32 Release 5 support

2020-05-06 Thread Sergey.Semin
From: Serge Semin There are five MIPS32/64 architecture releases currently available: from 1 to 6 except fourth one, which was intentionally skipped. Three of them can be called as major: 1st, 2nd and 6th, that not only have some system level alterations, but also introduced significant core/ISA

[PATCH v2 04/20] mips: cm: Fix an invalid error code of INTVN_*_ERR

2020-05-06 Thread Sergey.Semin
From: Serge Semin Commit 3885c2b463f6 ("MIPS: CM: Add support for reporting CM cache errors") adds cm2_causes[] array with map of error type ID and pointers to the short description string. There is a mistake in the table, since according to MIPS32 manual CM2_ERROR_TYPE = {17,18} correspond to

[PATCH v2 09/20] mips: Add CP0 Write Merge config support

2020-05-06 Thread Sergey.Semin
From: Serge Semin CP0 config register may indicate whether write-through merging is allowed. Currently there are two types of the merging available: SysAD Valid and Full modes. Whether each of them are supported by the core is implementation dependent. Moreover whether the ability to change the

[PATCH v2 08/20] mips: Fix cpu_has_mips64r1/2 activation for MIPS32 CPUs

2020-05-06 Thread Sergey.Semin
From: Serge Semin Commit 1aeba347b3a9 ("MIPS: Hardcode cpu_has_mips* where target ISA allows") updated the cpu_has_mips* macro to be replaced with a constant expression where it's possible. By mistake it wasn't done correctly for cpu_has_mips64r1/cpu_has_mips64r2 macro. They are defined to be

[PATCH v2 10/20] mips: Add CONFIG/CONFIG6/Cause reg fields macro

2020-05-06 Thread Sergey.Semin
From: Serge Semin There are bit fields which persist in the MIPS CONFIG and CONFIG6 registers, but haven't been described in the generic mipsregs.h header so far. In particular, the generic CONFIG bitfields are BE - endian mode, BM - burst mode, SB - SimpleBE, OCP interface mode indicator, UDI -

[PATCH v2 05/20] mips: cm: Add L2 ECC/parity errors reporting

2020-05-06 Thread Sergey.Semin
From: Serge Semin According to the MIPS32 InterAptiv software manual error codes 24 - 26 of CM2 indicate L2 ECC/parity error with switching to a corresponding errors info fields. This patch provides these errors parsing code, which handles the read/write uncorrectable and correctable ECC/parity

[PATCH v2 00/20] mips: Prepare MIPS-arch code for Baikal-T1 SoC support

2020-05-06 Thread Sergey.Semin
From: Serge Semin This is a first patchset of a series of about 25 ones, which are intended to add the full Baikal-T1 SoC [1] support to the Linux kernel. Since they will concern various kernel subsystems, I decided to split the whole work up into the patchesets in accordance with the

[PATCH v2 03/20] dt-bindings: Add vendor prefix for Baikal Electronics, JSC

2020-05-06 Thread Sergey.Semin
From: Serge Semin Add "BAIKAL ELECTRONICS, JSC" to the list of devicetree vendor prefixes as "baikal". Website: http://www.baikalelectronics.com Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Arnd Bergmann Cc:

[PATCH v2 01/20] dt-bindings: power: Convert mti,mips-cpc to DT schema

2020-05-06 Thread Sergey.Semin
From: Serge Semin It's a Cluster Power Controller embedded into the MIPS IP cores. Currently the corresponding dts node is supposed to have compatible and reg properties. Signed-off-by: Serge Semin Cc: Alexey Malahov Cc: Thomas Bogendoerfer Cc: Paul Burton Cc: Ralf Baechle Cc: Arnd