66MHz PCI

All, is it possible to detect whether a device is running at 66MHz (as opposed to 33)? PCI defines a 66MHz capable bit, but not a 66MHz enabled bit. We have a silly device that seems to need to know what it's bus speed is, but have no way to tell from software (that I know of). So, pray tell -

Re: how mmap() works?

> Without syncing, Linux writes whenever it thinks it's appropriate, e.g. > when pages have to be freed (I think also when the bdflush writes back > data, i.e. every 30 seconds by default). what about mmap() on non-filesystem files (/dev/mem, /proc/bus/pci...) ? - To unsubscribe from this list:

Re: IDE not fully found (2.4.2) PDC20265

> On Mon, 15 Jan 2001, Tim Hockin wrote: > > > Motherboard (MSI 694D-AR) has Via Apollo Pro chipset, those IDE drives seem > > fine. Board also has a promise PDC20265 RAID/ATA100 controller. On each > > channel of this controller I have an IBM 45 GB ATA100 drive as

mtrr message

I'm noticing these messages: mtrr: base(0xd400) is not aligned on a size(0x180) boundary :many times in dmesg. System is a dual P3-933 on a MSI 694D board (Apollo Pro 133). Is it worrisome? - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of

Re: SMP: bind process to cpu

> Is it possible to bind a process to a specific > cpu on this SMP machine (process affinity) ? > > I there something like pset ? http://isunix.it.ilstu.edu/~thockin/pset - pset for linux-2.2 (not ported to 2.4 yet) - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in th

Re: PCI IRQ routing problem in 2.4.0

> > Device 00:01.0 (slot 0): ISA bridge > > INTA: link 0x01, irq mask 0x1eb8 [3,4,5,7,9,10,11,12] > > INTB: link 0x02, irq mask 0x1eb8 [3,4,5,7,9,10,11,12] > > INTC: link 0x03, irq mask 0x1eb8 [3,4,5,7,9,10,11,12] > > INTD: link 0x04, irq mask 0x1eb8 [3,4,5,7,9,10,11,12] > > Your "link" v

Re: [PATCH] PCI-Devices and ServerWorks chipset

> > patch is wrong -- it doesn't make any sense to scan a bus _range_. The registers > > 0x44 and 0x45 are probably ID's of two primary buses and the code should scan > > both of them, but not the space between them. > 0x44 is the primary bus number of the host bridge, and 0x45 is the subordinat

Re: int. assignment on SMP + ServerWorks chipset

> And if anybody else understands pirq routing, speak up. It's a black art. > I have some experience with PIRQ and Serverworks, but I missed the first bit of this discussion - can someone catch me up? - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a mess

IDE not fully found (2.4.0)

Just built a new system with Linux-2.4.0. Motherboard (MSI 694D-AR) has Via Apollo Pro chipset, those IDE drives seem fine. Board also has a promise PDC20265 RAID/ATA100 controller. On each channel of this controller I have an IBM 45 GB ATA100 drive as master. (hde and hdg?). BIOS sees these

List down or am I unsubscribed?

I haven't received messages in a few days at least... - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] Please read the FAQ at http://www.tux.org/lkml/

Re: National Semiconductor DP83815 ethernet driver?

> >From searching Google, I know some sort of driver exists. In July, Adam J. > Richter ([EMAIL PROTECTED]) posted a 2.2.16 driver he obtained from Dave > Gotwisner at Wyse Technologies. And Tim Hockin mentioned that he was using > an NSC driver, but had made some minor modifi

Re: Can EINTR be handled the way BSD handles it? -- a plea from a

> "THIS CHANGE CAUSED PROBLEMS FOR SOME APPLICATION CODE." > > _Which_ applications? > > _Why_ did they have a problem? Was this due to a bug or were they > designed to do stuff this way? I, for one, have an app that relies on syscalls not being restarted: app g

<    1   2