the performance degradation caused by high L1 exit
penalties.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=211187
Signed-off-by: Victor Ding
---
Changes in v2:
- Updated commit message to remove unnecessary information
- Fixed a bug reading wrong register in pcie_save_aspm_control
- Updated
On Fri, Jan 29, 2021 at 12:44 AM Krzysztof Wilczyński wrote:
>
> Hi Victor,
>
> Thank you for working on this!
>
> [...]
> > i = pci_save_pcie_state(dev);
> > if (i != 0)
> > - return i;
> > + goto Exit;
> >
> > i = pci_save_pcix_state(dev);
> > if
the performance degradation caused by high L1 exit
penalties.
Therefore, this patch proposes to disable ASPM during a suspend/resume
process.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=211187
Signed-off-by: Victor Ding
---
drivers/pci/pci.c | 18 +++---
drivers/pci/pci.h
On Thu, Jan 14, 2021 at 8:48 AM Bjorn Helgaas wrote:
>
> [+cc Rafael, suspend/resume expert]
>
> On Wed, Jan 13, 2021 at 01:16:23PM +1100, Victor Ding wrote:
> > On Wed, Jan 13, 2021 at 9:38 AM Bjorn Helgaas wrote:
> > > On Tue, Jan 12, 2021 at 04:02:05AM +, Victor
On Thu, Jan 14, 2021 at 7:54 AM Bjorn Helgaas wrote:
>
> On Wed, Jan 13, 2021 at 01:16:05PM +1100, Victor Ding wrote:
> > On Wed, Jan 13, 2021 at 9:32 AM Bjorn Helgaas wrote:
> > > On Tue, Jan 12, 2021 at 04:02:04AM +, Victor Ding wrote:
> > > > Right after
On Wed, Jan 13, 2021 at 9:38 AM Bjorn Helgaas wrote:
>
> On Tue, Jan 12, 2021 at 04:02:05AM +, Victor Ding wrote:
> > GL9750 has a 3100us PortTPowerOnTime; however, it enters L1.2 after
> > only ~4us inactivity per PCIe trace. During a suspend/resume process,
> &g
Hi Bjorn,
On Wed, Jan 13, 2021 at 9:32 AM Bjorn Helgaas wrote:
>
> Hi Victor,
>
> Thanks for the patch. Improving suspend/resume performance is always
> a good thing!
>
> On Tue, Jan 12, 2021 at 04:02:04AM +, Victor Ding wrote:
> > Right after powering up, the d
ing benefit from
ASPM during suspend/resume does not overweight the performance
degradation caused by long L1.2 exit latency.
Therefore, this patch proposes to disable ASPM during a suspend/resume
process.
Signed-off-by: Victor Ding
---
drivers/mmc/host/sdhci-pci-core.c | 2 +-
drivers/mmc/host/sd
a suspension.
Therefore, ASPM should disabled until its LTR and L1ss states are
fully restored.
Signed-off-by: Victor Ding
---
drivers/pci/pci.c | 11 +++
drivers/pci/pci.h | 2 ++
drivers/pci/pcie/aspm.c | 2 +-
3 files changed, 14 insertions(+), 1 deletion(-)
diff
ore, the little power-saving benefit from ASPM during
suspend/resume does not overweight the performance degradation caused by
long L1.2 exit latency.
Therefore, I am proposing to disable ASPM during a suspend/resume process.
Victor Ding (2):
PCI/ASPM: Disable ASPM until its LTR and L1ss state is resto
On Wed, Nov 4, 2020 at 1:17 PM Srinivas Pandruvada
wrote:
>
> On Wed, 2020-11-04 at 12:43 +1100, Victor Ding wrote:
> > On Wed, Nov 4, 2020 at 4:09 AM Srinivas Pandruvada
> > wrote:
> > > On Tue, 2020-11-03 at 17:10 +1100, Victor Ding wrote:
> > > > On
On Wed, Nov 4, 2020 at 4:09 AM Srinivas Pandruvada
wrote:
>
> On Tue, 2020-11-03 at 17:10 +1100, Victor Ding wrote:
> > On Mon, Nov 2, 2020 at 12:39 PM Zhang Rui
> > wrote:
> > > On Tue, 2020-10-27 at 07:23 +, Victor Ding wrote:
> > > > Thi
On Mon, Nov 2, 2020 at 12:39 PM Zhang Rui wrote:
>
> On Tue, 2020-10-27 at 07:23 +, Victor Ding wrote:
> > This patch enables AMD Fam17h RAPL support for the power capping
> > framework. The support is as per AMD Fam17h Model31h (Zen2) and
> > model 00-ffh (Z
will have properly set presets. So this change will
support both new and old platforms.
Signed-off-by: Raul E Rangel
Signed-off-by: Victor Ding
---
Changes in v2:
By Victor Ding
- Rebased the patch by using FIELD_GET for preset value bit masks.
- (No functional changes).
The original patch
From: Kim Phillips
AMD Family 19h's RAPL MSRs are identical to Family 17h's. Extend
Family 17h's support to Family 19h.
Signed-off-by: Kim Phillips
Signed-off-by: Victor Ding
---
Changes in v3:
By Victor Ding
- Rebased to the latest code.
- Created a new rapl_defaults for AMD CPUs
:
/sys/class/powercap/intel-rapl/intel-rapl:0/energy_uj
/sys/class/powercap/intel-rapl/intel-rapl:0/intel-rapl:0:0/energy_uj
Signed-off-by: Victor Ding
Acked-by: Kim Phillips
---
Changes in v3:
By Victor Ding
- Rebased to the latest code.
- Created a new rapl_defaults for AMD CPUs.
- Removed
This patch changes the static struct rapl_msr_priv to a pointer to allow
using a different set of RAPL MSR interface, preparing for supporting AMD's
RAPL MSR interface.
No functional changes.
Signed-off-by: Victor Ding
Acked-by: Kim Phillips
---
(no changes since v2)
Changes in v2:
By Kim
MSRs in the rest of this file are sorted by their addresses; fixing the
two outliers.
No functional changes.
Signed-off-by: Victor Ding
Acked-by: Kim Phillips
---
(no changes since v2)
Changes in v2:
By Kim Phillips :
- Added Kim's Acked-by.
- Added Daniel Lezcano to Cc.
- (No code changes
to seamlessly run on AMD.
>From the user's point view, this series enables the following two sysfs
entry on AMD Fam17h or Fam19h:
/sys/class/powercap/intel-rapl/intel-rapl:0/energy_uj
/sys/class/powercap/intel-rapl/intel-rapl:0/intel-rapl:0:0/energy_uj
Changes in v3:
By Victor Ding
- Reba
On Fri, Oct 9, 2020 at 2:47 PM Zhang Rui wrote:
>
> On Wed, 2020-10-07 at 11:14 -0500, Kim Phillips wrote:
> > From: Victor Ding
> >
> > This patch enables AMD Fam17h RAPL support for the power capping
> > framework. The support is as per AMD Fam17h Model31h (Ze
a correct time64_t is expensive and
hence should be avoided.
Signed-off-by: Victor Ding
---
Changes in v2:
- Initialize the struct to 0 instead of -1;
- Initialize the whole struct rtc_wkalrm.
drivers/rtc/rtc-cmos.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/rtc/rtc-cmos.c
Hi Alexandre,
On Fri, Aug 14, 2020 at 6:15 PM Alexandre Belloni
wrote:
>
> On 14/08/2020 16:10:13+1000, Victor Ding wrote:
> > Hi Alexandre,
> >
> > On Thu, Aug 13, 2020 at 5:33 PM Alexandre Belloni
> > wrote:
> > >
> > > Hi,
> >
Hi Alexandre,
On Thu, Aug 13, 2020 at 5:33 PM Alexandre Belloni
wrote:
>
> Hi,
>
> On 13/08/2020 15:41:34+1000, Victor Ding wrote:
> > cmos_read_alarm() may leave certain fields of a struct rtc_time
> > untouched; therefore, these fields contain garbage if not properly
().
Signed-off-by: Victor Ding
---
drivers/rtc/rtc-cmos.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index bcc96ab7793f..c99af567780d 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -1006,6 +1006,7 @@ static int
:
/sys/class/powercap/intel-rapl/intel-rapl:0/energy_uj
/sys/class/powercap/intel-rapl/intel-rapl:0/intel-rapl:0:0/energy_uj
Signed-off-by: Victor Ding
---
arch/x86/include/asm/msr-index.h | 1 +
drivers/powercap/intel_rapl_common.c | 2 ++
drivers/powercap/intel_rapl_msr.c| 27
This patch changes the static struct rapl_msr_priv to a pointer to allow
using a different set of of RAPL MSR interface, preparing for supporting
AMD's RAPL MSR interface.
No functional changes.
Signed-off-by: Victor Ding
---
drivers/powercap/intel_rapl_msr.c | 33
MSRs in the rest of this file are sorted by their addresses; fixing the
two outliers.
No functional changes.
Signed-off-by: Victor Ding
---
arch/x86/include/asm/msr-index.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include
on AMD.
>From the user's point view, this series enables the following two sysfs
entry on AMD Fam17h:
/sys/class/powercap/intel-rapl/intel-rapl:0/energy_uj
/sys/class/powercap/intel-rapl/intel-rapl:0/intel-rapl:0:0/energy_uj
Victor Ding (3):
x86/msr-index: sort AMD RAPL MSRs by addr
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