On 24/02/19 1:49 AM, Sergei Shtylyov wrote:
> Hello!
>
> On 02/19/2019 09:36 AM, Vignesh R (by way of Boris Brezillon
> ) wrote:
>
>> Cypress HyperBus is Low Signal Count, High Performance Double Data Rate Bus
>> interface between a host system master and o
On 26/02/19 1:03 AM, Sergei Shtylyov wrote:
> On 02/25/2019 09:21 PM, Vignesh R wrote:
>
> [...]
>
>>>> HyperBus specification can be found at[1]
>>>> HyperFlash datasheet can be found at[2]
>>>>
>>>> [1] https://www.cypress.co
On 25/02/19 9:59 PM, Sergei Shtylyov wrote:
> Hello!
>
> On 02/19/2019 09:36 AM, Vignesh R (by way of Boris Brezillon
> ) wrote:
>
>> Add driver for Hyperbus memory controller on TI's AM654 SoC. Programming
>> IP is pretty simple and provides direct memory mapped a
Hi Sergei,
On 24/02/19 1:49 AM, Sergei Shtylyov wrote:
> Hello!
>
> On 02/19/2019 09:36 AM, Vignesh R (by way of Boris Brezillon
> ) wrote:
>
>> Cypress HyperBus is Low Signal Count, High Performance Double Data Rate Bus
>> interface between a host system m
On 22-Feb-19 8:20 PM, liujian (CE) wrote:
>
>> -Original Message-
>> From: Vignesh R [mailto:vigne...@ti.com]
>> Sent: Friday, February 22, 2019 1:59 PM
>> To: liujian (CE) ; dw...@infradead.org;
>> computersforpe...@gmail.com; bbrezil...@kernel.or
On 20/02/19 2:17 AM, Liu Jian wrote:
> In function do_write_buffer(), in the for loop, there is a case
> chip_ready() returns 1 while chip_good() returns 0, so it never
> break the loop.
> To fix this, chip_good() is enough and it should timeout if it stay
> bad for a while.
>
> Fixes:
IP also supports 8-8-8 DTR mode. But supporting those modes
require enabling, configuring and calibrating OSPI PHY module within the
IP.
I am planning to do that, after moving driver over to spi-mem layer.
>> Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
>>
>> Signed-off-by:
On 19/02/19 12:06 PM, Vignesh R wrote:
[...]
>
> Tested on modified TI AM654 EVM with Cypress Hyperflash S26KS512 by
> creating a UBIFS partition and writing and reading files to it.
> Stress tested by writing/reading 16MB flash repeatedly at different
> offsets using dd com
orted.
[1] https://www.cypress.com/file/213346/download
Signed-off-by: Vignesh R
---
Note: PRI extended query table size is bigger on 1.5 than on older
revision. Not sure if this causes problems on older rev. because of
reading beyond current size.
drivers/mtd/chips/cfi_cmdset_0
ash datasheet can be found at[2]
TI's HBMC controller details at[3]
[1] https://www.cypress.com/file/213356/download
[2] https://www.cypress.com/file/213346/download
[3] http://www.ti.com/lit/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Vignesh R (5):
mtd: cfi_cmdset_0002:
/ug/spruid7b/spruid7b.pdf
Table 12-5741. HyperFlash Access Sequence
Signed-off-by: Vignesh R
---
MAINTAINERS | 7 ++
drivers/mtd/Kconfig | 2 +
drivers/mtd/Makefile | 1 +
drivers/mtd/hyperbus/Kconfig | 23 +
drivers/mtd/hyperbus/Makefile |
Add driver for Hyperbus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.
Add basic support for the IP without DMA. Second ChipSelect is not
supported for now.
Signed-off-by: Vignesh R
---
drivers/mtd
Add binding documentation for TI's Hyperbus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh R
---
.../devicetree/bindings/mtd/ti,am654-hbmc.txt | 27 +++
MAINTAINERS | 1 +
2 files changed, 28 insertions(+)
create mode 100644
Add DT binding documentation for Hyperbus memory devices. For now only
Hyperflash is supported.
Signed-off-by: Vignesh R
---
Documentation/devicetree/bindings/mtd/cypress,hyperbus.txt | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/cypress
On 15/02/19 8:45 PM, Colin King wrote:
> From: Colin Ian King
>
> There is a spelling mistake in a dev_error message. Fix it.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/mtd/spi-nor/cadence-quadspi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
TI AM654 SoC has two ADC instances in the MCU domain. Add DT nodes for
the same.
Signed-off-by: Vignesh R
---
Tero,
Could you also pick up DT bindings here:
https://patchwork.kernel.org/patch/10751429/
All the Acks are in place.
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 30
AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence
QSPI controller but supports Octal IO(x8 data lines) and Double Data
Rate(DDR) mode. Add new compatible to support OSPI controller on TI's
AM654 SoCs.
Signed-off-by: Vignesh R
Reviewed-by: Rob Herring
---
v6: No change
of Yogesh's series[1]
v2:
spi-nor core patches dropped, are now part of Yogesh's series [1]
Declare Octal mode capability based on compatible.
Vignesh R (2):
dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC
mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller
is supported for now.
Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
Signed-off-by: Vignesh R
---
v6: Return error when driver data is not found
drivers/mtd/spi-nor/cadence-quadspi.c | 59 +--
1 file changed, 47 insertions(+), 12 deletions(-)
diff --git
Hi Dmitry,
On 08/01/19 10:56 AM, Vignesh R wrote:
> AM654 SoCs has ADC IP which is similar to AM335x, but without the
> touchscreen part. Add new compatible to handle AM654 SoCs. Also, it
> seems that existing compatible strings used in the kernel DTs were never
> documented. So, d
On 10/02/19 6:49 PM, Boris Brezillon wrote:
> On Tue, 5 Feb 2019 11:43:46 +0530
> Vignesh R wrote:
>
>>>> static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node
>>>> *np)
>>>> {
>>>> - const struct spi_nor_h
On 05/02/19 12:30 PM, Mandal, Purna Chandra wrote:
>
>
> On 04-Feb-19 7:07 PM, Vignesh R wrote:
>> Hi,
>>
>> On 03/02/19 5:50 PM, tudor.amba...@microchip.com wrote:
>>> + Vignesh
>>>
>>
>> Thanks for looping in.
>>
>>>
Hi,
On 29/01/19 9:02 PM, tudor.amba...@microchip.com wrote:
>
>
> On 01/28/2019 07:49 AM, Vignesh R wrote:
>> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
>> It also has an integrated PHY. IP register layout is very
>> similar to existing QSPI IP
Hi,
On 03/02/19 5:50 PM, tudor.amba...@microchip.com wrote:
> + Vignesh
>
Thanks for looping in.
> On 01/28/2019 07:02 AM, Purna Chandra Mandal wrote:
>> cadence-quadspi controller allows upto eight bytes of data to
>> be written in software Triggered Instruction generator (STIG) mode
>> of
han
one CS is in use. Fix this by correcting the order of parameters when
calling regmap_update_bits().
Fixes: 4dea6c9b0b64 ("spi: spi-ti-qspi: add mmap mode read support")
Cc: sta...@vger.kernel.org
Signed-off-by: Vignesh R
---
drivers/spi/spi-ti-qspi.c | 6 +++---
1 file changed, 3 insert
of Yogesh's series[1]
v2:
spi-nor core patches dropped, are now part of Yogesh's series [1]
Declare Octal mode capability based on compatible.
Vignesh R (2):
dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC
mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller
is supported for now.
Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
Signed-off-by: Vignesh R
Reviewed-by: Tudor Ambarus
---
v5:
s/cqsi_base_hwcaps_mask/CQSPI_BASE_HWCAPS_MASK/g
Add back cqspi_driver_platdata definition for base compatible.
v4: Fix comments by Tudor on v3
v3
AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence
QSPI controller but supports Octal IO(x8 data lines) and Double Data
Rate(DDR) mode. Add new compatible to support OSPI controller on TI's
AM654 SoCs.
Signed-off-by: Vignesh R
Reviewed-by: Rob Herring
---
Documentation
On 23-Jan-19 2:15 PM, Boris Brezillon wrote:
> On Tue, 22 Jan 2019 12:11:37 +0530
> Vignesh R wrote:
>
>> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
>> It also has an integrated PHY. IP register layout is very
>> similar to existing QSPI IP
is supported for now.
Tested with mt35xu512aba Octal flash on TI's AM654 EVM.
Signed-off-by: Vignesh R
---
v4: Fix comments by Tudor on v3
v3: No changes
v2: Declare Octal mode capability based on compatible.
drivers/mtd/spi-nor/cadence-quadspi.c | 53 +--
1 file
AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence
QSPI controller but supports Octal IO(x8 data lines) and Double Data
Rate(DDR) mode. Add new compatible to support OSPI controller on TI's
AM654 SoCs.
Signed-off-by: Vignesh R
Reviewed-by: Rob Herring
---
v4: No changes
core patches dropped, are now part of Yogesh's series [1]
Declare Octal mode capability based on compatible.
Vignesh R (2):
dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC
mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller
.../bindings/mtd/cadence-quadspi.txt
Hi, Tudor,
On 20/01/19 8:26 PM, tudor.amba...@microchip.com wrote:
> Hi, Vignesh,
>
> On 01/16/2019 12:30 PM, Vignesh R wrote:
>> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
>> It also has an integrated PHY. IP register layout is very
>> similar
On 20/01/19 8:58 PM, tudor.amba...@microchip.com wrote:
> Vignesh,
>
> On 01/20/2019 04:56 PM, tudor.amba...@microchip.com wrote:
>> Looks good.
>
> one more thing: in cqspi_read_setup() I see that the dummy cycles are adjusted
> if (f_pdata->inst_width != CQSPI_INST_TYPE_QUAD).
>
> Should
AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence
QSPI controller but supports Octal IO(x8 data lines) and Double Data
Rate(DDR) mode. Add new compatible to support OSPI controller on TI's
AM654 SoCs.
Signed-off-by: Vignesh R
Reviewed-by: Rob Herring
---
v3: No changes
Cadence OSPI controller IP supports Octal IO (x8 IO lines),
It also has an integrated PHY. IP register layout is very
similar to existing QSPI IP except for additional bits to support Octal
and Octal DDR mode. Therefore, extend current driver to support Octal
mode.
Signed-off-by: Vignesh R
:
spi-nor core patches dropped, are now part of Yogesh's series [1]
Declare Octal mode capability based on compatible.
Vignesh R (2):
dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC
mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller
.../bindings/mtd/cadence
g
Reported-by: David Lechner
Tested-by: David Lechner
Signed-off-by: Vignesh R
---
drivers/spi/spi-omap2-mcspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 2fd8881fcd65..8be304379628 100644
--- a/d
t = es;
+ cfg.src_maxburst = width / es;
+ cfg.dst_maxburst = width / es;
rx = xfer->rx_buf;
tx = xfer->tx_buf;
--
Regards
Vignesh
> Cc: Vignesh R
> Signed-off-by: David Lechner
> ---
> drivers/spi/spi-omap2-mcspi.c | 26 +++--
On 10-Jan-19 5:37 PM, Sebastian Reichel wrote:
> Hi,
>
> On Wed, Jan 09, 2019 at 01:44:03PM -0800, Tony Lindgren wrote:
>> * Vignesh R [190109 09:11]:
>>> 8250_omap is DT only driver so dev->of_node always exists. Drop check
>>> for existence of valid dev
Document clocks property used to pass phandle to functional clk.
Signed-off-by: Vignesh R
---
Documentation/devicetree/bindings/serial/omap_serial.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt
b/Documentation/devicetree
is not defined.
Suggested-by: Lokesh Vutla
Signed-off-by: Vignesh R
---
drivers/tty/serial/8250/8250_omap.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/8250/8250_omap.c
b/drivers/tty/serial/8250/8250_omap.c
index a74126569785..0a8316632d75
8250_omap is DT only driver so dev->of_node always exists. Drop check
for existence of valid dev->of_node to simplify omap8250_probe().
Signed-off-by: Vignesh R
---
drivers/tty/serial/8250/8250_omap.c | 63 +
1 file changed, 28 insertions(+), 35 deletions(-)
This series adds support obtain clk frequency of functional clk via
clocks phandle instead of hard coding it in DT as part of
clock-frequency DT parameter. This eliminates need to calculate
frequency offline and populate it.
Vignesh R (3):
serial: 8250_omap: Drop check for of_node
dt-bindings
AM654 SoCs has ADC IP which is similar to AM335x, but without the
touchscreen part. Add new compatible to handle AM654 SoCs. Also, it
seems that existing compatible strings used in the kernel DTs were never
documented. So, document them now.
Signed-off-by: Vignesh R
Reviewed-by: Rob Herring
Hi,
On 20/12/18 11:02 AM, Yogesh Narayan Gaur wrote:
[...]
>>> Yogesh Gaur (7):
>>> spi: add support for octal mode I/O data transfer
>>> spi: spi-mem: add support for octal mode I/O data transfer
>>
>>
>> These two patches are already merged and is now part of linux-next[1].
>> Its preferred
Hi,
On 19/12/18 3:41 PM, Yogesh Narayan Gaur wrote:
> Add support for octal mode IO data transfer.
> Micron flash, mt35xu512aba, supports octal mode data transfer and
> NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
>
> Patch series
> * Add support for octal mode flags
On 13-Dec-18 8:29 PM, Tero Kristo wrote:
> On 09/12/2018 12:22, Vignesh R wrote:
>> There are 3 instances of McSPI in MCU domain and 4 instances in Main
>> domain.
>> Add DT nodes for all McSPI instances present on AM654 SoC.
>>
>> Signed-off-by: Vignesh R
>
are not initialized before Linux boots up and current
speed is unknown.
Signed-off-by: Vignesh R
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++--
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi| 1 +
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 1 +
3 files changed, 5 insertions(+), 2
AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence
QSPI controller but supports Octal IO(x8 data lines) and Double Data
Rate(DDR) mode. Add new compatible to support OSPI controller on TI's
AM654 SoCs.
Signed-off-by: Vignesh R
Reviewed-by: Rob Herring
---
v2
Collect
of Yogesh's series [1]
Declare Octal mode capability based on compatible.
Vignesh R (2):
dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC
mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller
.../bindings/mtd/cadence-quadspi.txt | 1 +
drivers/mtd/spi-nor
Cadence OSPI controller IP supports Octal IO (x8 IO lines),
It also has an integrated PHY. IP register layout is very
similar to existing QSPI IP except for additional bits to support Octal
and Octal DDR mode. Therefore, extend current driver to support Octal
mode.
Signed-off-by: Vignesh R
On 07/12/18 2:12 PM, Faiz Abbas wrote:
> On the am654x-evm, sdhci0 node is connected to an eMMC while sdhci1
> is connected to an SD card slot. Add nodes and pinmuxes for the same.
>
> Signed-off-by: Faiz Abbas
> ---
> .../arm64/boot/dts/ti/k3-am654-base-board.dts | 46 +++
>
On 10/12/18 2:15 PM, Boris Brezillon wrote:
> On Wed, 3 Oct 2018 22:26:03 +0530
> Vignesh R wrote:
>
>> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
>> It also has an integrated PHY. IP register layout is very
>> similar to existing QSPI IP except for
Couple of patches to add support for McSPIs in AM654 SoC.
Vignesh R (2):
arm64: dts: ti: k3-am654: Add McSPI DT nodes
arm64: dts: ti: k3-am654: Enable main domain McSPI0
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 52 +++
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
There are 3 instances of McSPI in MCU domain and 4 instances in Main domain.
Add DT nodes for all McSPI instances present on AM654 SoC.
Signed-off-by: Vignesh R
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 52
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 30
Enable McSPI0 of main domain and add DT node for the SPI NOR flash
connected to CS0.
Signed-off-by: Vignesh R
---
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 27 +++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
b/arch/arm64
Hi Boris,
On 03/10/18 10:26 PM, Vignesh R wrote:
> This series adds support for octal mode of mt35x flash. Also, adds
> support for OSPI version of Cadence QSPI controller.
>
> Based on top of patches adding basic support for mt35xu512aba here:
> https://patchwork.ozlabs.o
On 07/12/18 2:12 PM, Faiz Abbas wrote:
> There are two MMC host controller instances present on the TI's
> Am654 SOCs. Add device tree nodes for the same.
>
> Signed-off-by: Faiz Abbas
> ---
> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 28
> 1 file changed, 28
On 07/12/18 2:12 PM, Faiz Abbas wrote:
> There are two MMC host controller instances present on the TI's
> Am654 SOCs. Add device tree nodes for the same.
>
> Signed-off-by: Faiz Abbas
> ---
> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 28
> 1 file changed, 28
Enable ECAP PWM which is used for LCD backlight.
Signed-off-by: Vignesh R
---
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index
Enable ECAP PWM which is used for LCD backlight.
Signed-off-by: Vignesh R
---
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index
Couple of patches to add ECAP PWM support for AM654 SoC. Based on top of
git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux.git
4.20-rc1-am65x-queue
Vignesh R (2):
arm64: dts: ti: k3-am65-main: Add ECAP PWM node
arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM
arch/arm64/boot
Couple of patches to add ECAP PWM support for AM654 SoC. Based on top of
git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux.git
4.20-rc1-am65x-queue
Vignesh R (2):
arm64: dts: ti: k3-am65-main: Add ECAP PWM node
arm64: dts: ti: k3-am654-base-board: Enable ECAP PWM
arch/arm64/boot
Add DT entry for ECAP0 PWM node present in main domain
Signed-off-by: Vignesh R
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 916434839603
Add DT entry for ECAP0 PWM node present in main domain
Signed-off-by: Vignesh R
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 916434839603
Hi Boris,
On 03/12/18 2:49 PM, Boris Brezillon wrote:
> Hi Mark,
>
> On Mon, 3 Dec 2018 08:39:00 +
> Yogesh Narayan Gaur wrote:
>
>>
>> Yogesh Gaur (7):
>> spi: add support for octal mode I/O data transfer
>> spi: spi-mem: add support for octal mode I/O data transfer
>
> Can you take
Hi Boris,
On 03/12/18 2:49 PM, Boris Brezillon wrote:
> Hi Mark,
>
> On Mon, 3 Dec 2018 08:39:00 +
> Yogesh Narayan Gaur wrote:
>
>>
>> Yogesh Gaur (7):
>> spi: add support for octal mode I/O data transfer
>> spi: spi-mem: add support for octal mode I/O data transfer
>
> Can you take
Hi,
On 19/11/18 3:15 PM, Vignesh R wrote:
> AM654 SoCs has ADC IP which is similar to AM335x. Add new compatible to
> handle AM654 SoCs. Also, it seems that existing compatible strings used
> in the kernel DTs were never documented. So, document them now.
>
> Signed-of
Hi,
On 19/11/18 3:15 PM, Vignesh R wrote:
> AM654 SoCs has ADC IP which is similar to AM335x. Add new compatible to
> handle AM654 SoCs. Also, it seems that existing compatible strings used
> in the kernel DTs were never documented. So, document them now.
>
> Signed-of
Use PLATFORM_DEVID_AUTO to number mfd cells while registering, so that
different instances are uniquely identified. This is required in order
to support registering of multiple instances of same ti_am335x_tscadc IP.
Signed-off-by: Vignesh R
---
v2: use PLATFORM_DEVID_AUTO as suggested by Lee
Use PLATFORM_DEVID_AUTO to number mfd cells while registering, so that
different instances are uniquely identified. This is required in order
to support registering of multiple instances of same ti_am335x_tscadc IP.
Signed-off-by: Vignesh R
---
v2: use PLATFORM_DEVID_AUTO as suggested by Lee
to VREFP and VREFN
respectively in STEP_CONFIGx register.
Without these changes, there may be variation of as much as ~2% in the
ADC's digital output which is bad for precise measurement.
Signed-off-by: Vignesh R
Acked-by: Jonathan Cameron
Acked-by: Lee Jones
---
v2: No change
drivers/iio/adc
Couple of fixes for tscadc drivers that I found while adding support for
new SoC.
Vignesh R (2):
mfd: ti_am335x_tscadc: Use PLATFORM_DEVID_AUTO while registering mfd
cells
iio: adc: ti_am335x_tscadc: Improve accuracy of measurement
drivers/iio/adc/ti_am335x_adc.c | 5
to VREFP and VREFN
respectively in STEP_CONFIGx register.
Without these changes, there may be variation of as much as ~2% in the
ADC's digital output which is bad for precise measurement.
Signed-off-by: Vignesh R
Acked-by: Jonathan Cameron
Acked-by: Lee Jones
---
v2: No change
drivers/iio/adc
Couple of fixes for tscadc drivers that I found while adding support for
new SoC.
Vignesh R (2):
mfd: ti_am335x_tscadc: Use PLATFORM_DEVID_AUTO while registering mfd
cells
iio: adc: ti_am335x_tscadc: Improve accuracy of measurement
drivers/iio/adc/ti_am335x_adc.c | 5
On 28/11/18 4:33 PM, Lee Jones wrote:
> On Wed, 28 Nov 2018, Vignesh R wrote:
>
>> Hi,
>>
>> On 28/11/18 2:37 PM, Lee Jones wrote:
>>> On Mon, 19 Nov 2018, Vignesh R wrote:
>>>
>>>> Provide unique names for child mfd cells, this is req
On 28/11/18 4:33 PM, Lee Jones wrote:
> On Wed, 28 Nov 2018, Vignesh R wrote:
>
>> Hi,
>>
>> On 28/11/18 2:37 PM, Lee Jones wrote:
>>> On Mon, 19 Nov 2018, Vignesh R wrote:
>>>
>>>> Provide unique names for child mfd cells, this is req
Hi,
On 28/11/18 2:37 PM, Lee Jones wrote:
> On Mon, 19 Nov 2018, Vignesh R wrote:
>
>> Provide unique names for child mfd cells, this is required in order to
>> support registering of multiple instances of same ti_am335x_tscadc IP.
>
> I don't think it is. What is the
Hi,
On 28/11/18 2:37 PM, Lee Jones wrote:
> On Mon, 19 Nov 2018, Vignesh R wrote:
>
>> Provide unique names for child mfd cells, this is required in order to
>> support registering of multiple instances of same ti_am335x_tscadc IP.
>
> I don't think it is. What is the
t for K3 platforms.
>
> Signed-off-by: Vignesh R
> Reviewed-by: Grygorii Strashko
> Signed-off-by: Wolfram Sang
> Signed-off-by: Sasha Levin
> ---
> drivers/i2c/busses/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/dr
t for K3 platforms.
>
> Signed-off-by: Vignesh R
> Reviewed-by: Grygorii Strashko
> Signed-off-by: Wolfram Sang
> Signed-off-by: Sasha Levin
> ---
> drivers/i2c/busses/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/dr
On 20/11/18 4:07 PM, Tero Kristo wrote:
> On 20/11/2018 12:09, Vignesh R wrote:
>> On 19/11/18 12:49 PM, Tero Kristo wrote:
>>> On 17/11/2018 18:05, Nishanth Menon wrote:
>>>> On 11:31-20181113, Vignesh R wrote:
>>>>> The dt-bindings hea
On 20/11/18 4:07 PM, Tero Kristo wrote:
> On 20/11/2018 12:09, Vignesh R wrote:
>> On 19/11/18 12:49 PM, Tero Kristo wrote:
>>> On 17/11/2018 18:05, Nishanth Menon wrote:
>>>> On 11:31-20181113, Vignesh R wrote:
>>>>> The dt-bindings hea
On 19/11/18 12:49 PM, Tero Kristo wrote:
> On 17/11/2018 18:05, Nishanth Menon wrote:
>> On 11:31-20181113, Vignesh R wrote:
>>> The dt-bindings header for TI K3 AM6 SoCs define a set of macros for
>>
[...]
>>
>> Thanks for reducing the combinations down to
On 19/11/18 12:49 PM, Tero Kristo wrote:
> On 17/11/2018 18:05, Nishanth Menon wrote:
>> On 11:31-20181113, Vignesh R wrote:
>>> The dt-bindings header for TI K3 AM6 SoCs define a set of macros for
>>
[...]
>>
>> Thanks for reducing the combinations down to
AM654 SoCs has ADC IP which is similar to AM335x. Add new compatible to
handle AM654 SoCs. Also, it seems that existing compatible strings used
in the kernel DTs were never documented. So, document them now.
Signed-off-by: Vignesh R
---
.../devicetree/bindings/input/touchscreen/ti-tsc-adc.txt
AM654 SoCs has ADC IP which is similar to AM335x. Add new compatible to
handle AM654 SoCs. Also, it seems that existing compatible strings used
in the kernel DTs were never documented. So, document them now.
Signed-off-by: Vignesh R
---
.../devicetree/bindings/input/touchscreen/ti-tsc-adc.txt
to VREFP and VREFN
respectively in STEP_CONFIGx register.
Without these changes, there may be variation of as much as ~2% in the
ADC's digital output which is bad for precise measurement.
Signed-off-by: Vignesh R
---
drivers/iio/adc/ti_am335x_adc.c | 5 -
include/linux/mfd
to VREFP and VREFN
respectively in STEP_CONFIGx register.
Without these changes, there may be variation of as much as ~2% in the
ADC's digital output which is bad for precise measurement.
Signed-off-by: Vignesh R
---
drivers/iio/adc/ti_am335x_adc.c | 5 -
include/linux/mfd
Provide unique names for child mfd cells, this is required in order to
support registering of multiple instances of same ti_am335x_tscadc IP.
Signed-off-by: Vignesh R
---
drivers/mfd/ti_am335x_tscadc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd
Provide unique names for child mfd cells, this is required in order to
support registering of multiple instances of same ti_am335x_tscadc IP.
Signed-off-by: Vignesh R
---
drivers/mfd/ti_am335x_tscadc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mfd
Couple of fixes for tscadc drivers that I found while adding support for
new SoC. Patches are standalone and can go via individual domain trees.
Vignesh R (2):
mfd: ti_am335x_tscadc: Provide unique name for child mfd cells
iio: adc: ti_am335x_tscadc: Improve accuracy of measurement
drivers
Couple of fixes for tscadc drivers that I found while adding support for
new SoC. Patches are standalone and can go via individual domain trees.
Vignesh R (2):
mfd: ti_am335x_tscadc: Provide unique name for child mfd cells
iio: adc: ti_am335x_tscadc: Improve accuracy of measurement
drivers
Hi,
On 15/11/18 3:53 AM, Sasha Levin wrote:
> From: Vignesh R
>
> [ Upstream commit 5b277402deac0691226a947df71c581686bd4020 ]
This patch depends on c77245722fb4 ("arm64: Add support for TI's K3
Multicore SoC architecture") which adds ARCH_K3 Kconfig symbol and
merged t
Hi,
On 15/11/18 3:53 AM, Sasha Levin wrote:
> From: Vignesh R
>
> [ Upstream commit 5b277402deac0691226a947df71c581686bd4020 ]
This patch depends on c77245722fb4 ("arm64: Add support for TI's K3
Multicore SoC architecture") which adds ARCH_K3 Kconfig symbol and
merged t
Hi,
On 13/11/18 11:02 PM, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> The current Cadence QSPI driver caused a kernel panic sporadically
> when writing to QSPI. The problem was caused by writing more bytes
> than needed because the QSPI operated on 4 bytes at a time.
>
> [
Hi,
On 13/11/18 11:02 PM, thor.tha...@linux.intel.com wrote:
> From: Thor Thayer
>
> The current Cadence QSPI driver caused a kernel panic sporadically
> when writing to QSPI. The problem was caused by writing more bytes
> than needed because the QSPI operated on 4 bytes at a time.
>
> [
Hi Yogesh
On 23/10/18 3:07 PM, Yogesh Narayan Gaur wrote:
> Add support for octo mode IO data transfer.
> Micron flash, mt35xu512aba, supports octal mode data transfer and
> NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
>
> Patch series
> * Add support for octo mode
Hi Yogesh
On 23/10/18 3:07 PM, Yogesh Narayan Gaur wrote:
> Add support for octo mode IO data transfer.
> Micron flash, mt35xu512aba, supports octal mode data transfer and
> NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
>
> Patch series
> * Add support for octo mode
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