On 14-01-21, 18:47, AngeloGioacchino Del Regno wrote:
> The TCSR's PHY_CLK_SCHEME register is not available on all SoC
> models, but some may still use a differential reference clock.
>
> In preparation for these SoCs, add a se_clk_scheme_default
> configuration entry and declare it to true for al
On 15-01-21, 09:47, Jack Pham wrote:
> Add the compatible strings for the USB2 PHYs found on QCOM
> SM8250 & SM8350 SoCs.
>
> Note that the SM8250 compatible is already in use in the dts and
> driver implementation but was missing from the documentation.
Applied, thanks
--
~Vinod
On 15-01-21, 09:47, Jack Pham wrote:
> Add support for the USB DP & UNI PHYs found on SM8350. These use
> version 5.0.0 of the QMP PHY IP and thus require new "V5"
> definitions of the register offset macros for the QSERDES RX
> and TX blocks. The QSERDES common and QPHY PCS blocks' register
> offs
On 15-01-21, 09:47, Jack Pham wrote:
> Add the compatible strings for the USB3 PHYs found on SM8150, SM8250
> and SM8350 SoCs. These require separate subschemas due to the different
> required clock entries.
>
> Note the SM8150 and SM8250 compatibles have already been in place in
> the dts as well
On 15-01-21, 13:37, Bard Liao wrote:
> The existing code reports a NAK only when ACK=0
> This is not aligned with the SoundWire 1.x specifications.
>
> Table 32 in the SoundWire 1.2 specification shows that a Device shall
> not set NAK=1 if ACK=1. But Table 33 shows the Combined Response
> may ver
On 15-01-21, 14:16, Bard Liao wrote:
> From: Pierre-Louis Bossart
>
> Currently the timeout for SoundWire individual transactions is 2s.
>
> This is too large in comparison with the enumeration and completion
> timeouts used in codec drivers.
>
> A command will typically be handled in less than
On 15-01-21, 16:25, Srinivas Kandagatla wrote:
> link_id can be zero and if we have multiple controller instances
> in a system like Qualcomm debugfs will end-up with duplicate namespace
> resulting in incorrect debugfs entries.
>
> Using id should give a unique debugfs directory entry and should
On 14-01-21, 11:02, Bard Liao wrote:
> dev->power.runtime_error will be set to the return value of the runtime
> suspend callback function, and runtime resume function will return
> -EINVAL if dev->power.runtime_error is not 0.
>
> Somehow the codec rarely doesn't return an ACK to the clock prepar
On 17-01-21, 23:16, Rikard Falkeborn wrote:
> The only place sdw_slave_dev_attr_group is used is when its address is
> passed to devm_device_add_group() which takes a pointer to const struct
> attribute_group. Make it const to allow the compiler to put it in
> read-only memory. This makes all attri
From: Vivek Aknurwar
This adds Global Clock controller (GCC) driver for SM8350 SoC
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/Kconfig |8 +
drivers/clk/qcom/Makefile |1
From: Vivek Aknurwar
Lucid 5LPE is a slightly different Lucid PLL with different offsets and
porgramming sequence so add support for these
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/clk
Add device tree bindings for global clock controller on SM8350 SoCs.
Reviewed-by: Rob Herring
Signed-off-by: Vinod Koul
---
.../bindings/clock/qcom,gcc-sm8350.yaml | 96 +++
include/dt-bindings/clock/qcom,gcc-sm8350.h | 261 ++
2 files changed, 357 insertions
Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but
with different registers. Modularize these by moving out latch and latch
ack bits so that we can reuse the function.
Suggested-by: AngeloGioacchino Del Regno
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/clk-alpha-pll.c
Driver uses regval variable for holding register values, replace with a
shorter one val
Suggested-by: Stephen Boyd
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/clk-alpha-pll.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/qcom/clk
for clocks defined in DT, use floor ops for sdcc clocks, remove
critical clocks and enable them in probe, add comments for clks using
BRANCH_HALT_SKIP and BRANCH_HALT_DELAY
Changes in v2:
- Add r-b from Bjorn
- Add the gcc_qupv3_wrap_1_{m|s}_ahb_clk and gcc_qupv3_wrap1_s5_clk
Vinod Koul (3
[1] mentions the IOAT entry contains dmaengine subsystem file. So update
the entry and remove the dmaengine files
1: https://lwn.net/Articles/842415/
Signed-off-by: Vinod Koul
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0d62310a31f8
On 11-01-21, 17:00, Manivannan Sadhasivam wrote:
> Hello,
>
> This series adds USB3 PHY support for SDX55 platform. The USB3 PHY is of
> type QMP and revision 4.0.0. In this revision, "com_aux" clock is not
> utilized.
>
> This series has been tested on SDX55-MTP along with the relevant DT node.
On 15-01-21, 10:00, Xu Wang wrote:
> fix semicolon.cocci warning:
> drivers/dma/qcom/gpi.c:1703:2-3: Unneeded semicolon
Applied, thanks
--
~Vinod
On 15-01-21, 17:56, Amireddy Mallikarjuna reddy wrote:
> Add DMA controller driver for Lightning Mountain (LGM) family of SoCs.
>
> The main function of the DMA controller is the transfer of data from/to any
> peripheral to/from the memory. A memory to memory copy capability can also
> be configur
On 13-01-21, 23:39, AngeloGioacchino Del Regno wrote:
> Il 05/01/21 16:46, Vinod Koul ha scritto:
> > From: Vivek Aknurwar
> >
> > Lucid 5LPE is a slightly different Lucid PLL with different offsets and
> > porgramming sequence so add support for these
> >
On 15-01-21, 12:54, Konrad Dybcio wrote:
> Hi,
>
>
> I might be wrong but it looks as if you forgot to add a compatible for the
> "sm8350_usb3_uniphy_cfg" configuration.
It seems to be documented in patch 2, ideally we should have the
bindings patches first and this as patch 3...
>
>
> Konra
Add the compatible string for SM8250 SoC from Qualcomm. This compatible
is used already in DTS files but not documented yet
Signed-off-by: Vinod Koul
Reviewed-by: Bjorn Andersson
Acked-by: Rob Herring
---
Reposting this with acks collected
.../devicetree/bindings/interrupt-controller/qcom
Add the compatible string for SM8350 SoC from Qualcomm.
Signed-off-by: Vinod Koul
---
.../devicetree/bindings/interrupt-controller/qcom,pdc.txt| 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
b/Documentation
Add SM8350 qcom iommu implementation to the table of
qcom_smmu_impl_of_match table which brings in iommu support for SM8350
SoC
Signed-off-by: Vinod Koul
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
Add compatible string for sm8350 iommu to documentation.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree/bindings/iommu/arm
On 14-01-21, 01:20, mda...@codeaurora.org wrote:
> On 2021-01-12 15:40, Vinod Koul wrote:
> > On 12-01-21, 15:01, mda...@codeaurora.org wrote:
> > > On 2020-12-21 23:03, mda...@codeaurora.org wrote:
> > > > On 2020-12-21 14:53, Vinod Koul wrote:
> > > > &g
On 14-01-21, 10:11, Jon Hunter wrote:
>
> On 06/08/2020 08:30, Rajesh Gumasta wrote:
> > Changes in patch v2:
> > Addressed review comments in patch v1
>
>
> Is there any update on this series? Would be good to get this upstream.
Not sure why, this is is not in my queue, can someone please rese
On 14-01-21, 09:10, Andy Shevchenko wrote:
> On Thursday, January 14, 2021, Jakub Kicinski wrote:
>
> > On Tue, 12 Jan 2021 17:37:09 +0200 Andy Shevchenko wrote:
> > > We have currently three users of the PSEC_PER_SEC each of them defining
> > it
> > > individually. Instead, move it to time64.h t
On 13-01-21, 15:05, Andy Shevchenko wrote:
> On Wed, Jan 13, 2021 at 5:23 AM Ferry Toth wrote:
> >
> > On Intel Tangier B0 and Anniedale the interrupt line, disregarding
> > to have different numbers, is shared between HSU DMA and UART IPs.
> > Thus on such SoCs we are expecting that IRQ handler i
On 13-01-21, 13:49, Peter Ujfalusi wrote:
> Hi,
>
> Changes since v1:
> - Added Kishon's tested-by to the first two patch
> - Moved the variable definitions to the start of their respective functions
> - Remove braces where they are not needed
> - correct indentation of cases
> - additional patch
On 05-01-21, 10:05, Amelie Delaunay wrote:
> STM32 USBPHYC controls the USB PLL. PLL requires to be powered with 1v1 and
> 1v8
> supplies. To ensure a good behavior of the PLL, during boot, runtime and
> suspend/resume sequences, this series reworks its management to fix regulators
> issues and im
On 13-01-21, 11:59, Mauro Carvalho Chehab wrote:
> Changeset ba2bf1f090eb ("dt-bindings: phy: Add Cadence Sierra PHY bindings in
> YAML format")
> renamed: Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
> to: Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml.
>
> Update
On 06-01-21, 21:58, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> Changes that require mentioning:
> 1. interrupt-names
>Name "wakeup" was changed to the "wake". It matches example and what
>Linux driver looks for in the first place
> 2. brcm,ipp and brcm,ioc
>Both were described as
On 12-01-21, 09:38, Zou Wei wrote:
> Fix the following sparse warning:
>
> drivers/phy/mediatek/phy-mtk-mipi-dsi.c:237:24: warning: symbol
> 'mtk_mipi_tx_driver' was not declared. Should it be static?
Applied, thanks
--
~Vinod
On 24-12-20, 17:12, Kishon Vijay Abraham I wrote:
> cmn_refclk_ lines in Torrent SERDES is used for connecting external
> reference clock. cmn_refclk_ can also be configured to output the
> reference clock. In order to drive the refclk out from the SERDES
> (Cadence Torrent), PHY_EN_REFCLK should b
On 24-12-20, 17:12, Kishon Vijay Abraham I wrote:
> The frequency of the txmclk between PCIe and SERDES has
> changed to 250MHz from 500MHz. Configure full rate divider
> for AM64 accordingly.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> drivers/phy/ti/phy-j721e-wiz.c | 43 +
On 07-01-21, 23:49, Mathias Kresin wrote:
> Commit 65dc2e725286 ("usb: dwc2: Update Core Reset programming flow.")
> revealed that the phy isn't ready immediately after enabling it's
> clocks. The dwc2_check_core_version() fails and the dwc2 usb driver
> errors out.
>
> Add a short delay to let th
On 25-12-20, 15:52, Chunfeng Yun wrote:
> Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml
Applied, thanks
--
~Vinod
On 25-12-20, 15:52, Chunfeng Yun wrote:
> Convert HDMI PHY binding to YAML schema mediatek,hdmi-phy.yaml
Applied, thanks
--
~Vinod
On 25-12-20, 15:52, Chunfeng Yun wrote:
> Convert phy-mtk-ufs.txt to YAML schema mediatek,ufs-phy.yaml
Applied, thanks
--
~Vinod
On 25-12-20, 15:52, Chunfeng Yun wrote:
> Convert phy-mtk-tphy.txt to YAML schema mediatek,tphy.yaml
Applied, thanks
--
~Vinod
On 25-12-20, 15:52, Chunfeng Yun wrote:
> Convert phy-mtk-xsphy.txt to YAML schema mediatek,xsphy.yaml
Applied, thanks
--
~Vinod
On 23-12-20, 12:45, Paul Cercueil wrote:
> Remove the useless field .version from the private structure, which is
> set but never read.
Applied, thanks
--
~Vinod
On 17-12-20, 14:04, Dan Carpenter wrote:
> This error path should return -EINVAL, but currently it returns
> success.
Applied, thanks
--
~Vinod
On 16-12-20, 15:33, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> 1. Use of_device_get_match_data() helper to simplify the code
> 2. Check for NULL as a good practice
Applied both, thanks
--
~Vinod
On 15-12-20, 09:44, Chris Ruehl wrote:
> Following the reference in vendor-prefixes.yaml, update implementation
> and documentation for the phy-rockchip-emmc.
> This patchset follow up with
> commit 8b5c2b45b8f0a ("phy: rockchip: set pulldown for strobe line in dts")
> commit a8cef928276bb ("phy:
On 11-12-20, 14:12, Liam Beguin wrote:
> From: Liam Beguin
>
> Start by reading the content of the VENDOR_SPECIFIC2 register and update
> each bit field based on device properties when defined.
>
> The use of bit masks prevents fields from overriding each other and
> enables users to clear bits
On 10-12-20, 19:11, Tian Tao wrote:
> Fix the following warning:
> drivers/phy/motorola/phy-cpcap-usb.c:146:31-36: WARNING: conversion to
> bool not needed here.
Applied, thanks
--
~Vinod
On 10-12-20, 16:04, Chris Ruehl wrote:
> rockchip_emmc_phy_init() return variable is not set with the error value
> if clk_get() failed. 'emmcclk' is optional, thus use clk_get_optional()
> and if the return value != NULL make error processing and set the
> return code accordingly.
Applied, thanks
On 12-01-21, 12:12, Nathan Chancellor wrote:
> When building with CONFIG_UBSAN_UNSIGNED_OVERFLOW, clang decides not to
> inline gpi_update_reg, which causes a linkage failure around __bad_mask:
>
> ld.lld: error: undefined symbol: __bad_mask
> >>> referenced by bitfield.h:119 (include/linux/bitfie
On 13-01-21, 09:39, Péter Ujfalusi wrote:
> Hi Vinod,
>
> On 1/12/21 12:16 PM, Vinod Koul wrote:
> > On 14-12-20, 10:13, Peter Ujfalusi wrote:
> >> The UDMA and BCDMA can provide higher throughput if the burst_size of the
> >> channel is changed from it's
On 12-01-21, 16:01, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 11, 2021 at 7:17 AM Vinod Koul wrote:
> >
> > We can use GPI DMA for devices where it is enabled by firmware. Add
> > support for this mode
> >
> > Signed-off-by: Vinod Koul
> &g
On 12-01-21, 16:01, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 11, 2021 at 7:17 AM Vinod Koul wrote:
> >
> > +static int geni_se_select_gpi_mode(struct geni_se *se)
> > +{
> > + unsigned int geni_dma_mode = 0;
> > + unsigned int gpi
Hello Doug,
On 12-01-21, 16:01, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 11, 2021 at 7:17 AM Vinod Koul wrote:
> >
> > Hello,
> >
> > This series add the GPI DMA in qcom geni spi and i2c drivers. For this we
> > first need to move GENI_IF_DISAB
On 12-01-21, 16:54, Geert Uytterhoeven wrote:
> Hi Vinod,
>
> On Tue, Jan 12, 2021 at 11:36 AM Vinod Koul wrote:
> > On 07-01-21, 19:15, Geert Uytterhoeven wrote:
> > > The DMACs (both SYS-DMAC and RT-DMAC) on R-Car V3U differ slightly from
> > > the DMACs on R-C
On 12-12-20, 17:05, Christophe JAILLET wrote:
> A 'irq_dispose_mapping()' call is missing in the remove function.
> Add it.
>
> This is needed to undo the 'irq_of_parse_and_map() call from the probe
> function and already part of the error handling path of the probe function.
>
> It was added in
On 12-12-20, 17:25, Christophe JAILLET wrote:
> A 'dma_pool_destroy()' call is missing in the remove function.
> Add it.
>
> This call is already made in the error handling path of the probe function.
Applied, thanks
--
~Vinod
On 03-12-20, 12:10, Amireddy Mallikarjuna reddy wrote:
> Add DMA controller driver for Lightning Mountain (LGM) family of SoCs.
>
> The main function of the DMA controller is the transfer of data from/to any
> peripheral to/from the memory. A memory to memory copy capability can also
> be configur
On 06-01-21, 16:53, Rob Herring wrote:
> > > > + dma-channel-mask:
> > > > +description:
> > > > + For DMA capability, We will know the addressing capability of
> > > > + MediaTek Command-Queue DMA controller through dma-channel-mask.
> > > > + minimum: 1
> > > > + maxim
On 23-12-20, 17:30, EastL Lee wrote:
> This patch introduces active_vdec to indicate the virtual descriptor
> under processing by the CQDMA dmaengine, and simplify the control logic
> by removing redundant queue structure, tasklets, and completion
> management.
Can we split these changes up..
>
On 15-12-20, 11:09, Dongjiu Geng wrote:
> Hisilicon EDMA Controller(EDMAC) directly transfers data
> between a memory and a peripheral, between peripherals, or
> between memories. This avoids the CPU intervention and reduces
> the interrupt handling overhead of the CPU, this driver enables
> this c
On 15-12-20, 11:09, Dongjiu Geng wrote:
> v6->v7:
> 1. rename hisi,misc-control to hisi,misc-control to hisilicon,misc-control
>
> v5->v6:
> 1. Drop #size-cells and #address-cell in the hisilicon,hi3559av100-clock.yaml
> 2. Add discription for #reset-cells in the hisilicon,hi3559av100-clock.yaml
>
On 12-01-21, 11:26, Geert Uytterhoeven wrote:
> Hi Vinod,
>
> On Tue, Jan 12, 2021 at 11:19 AM Vinod Koul wrote:
> > On 07-01-21, 19:15, Geert Uytterhoeven wrote:
> > > Add and helper macro for iterating over all DMAC channels, taking into
> > > accoun
On 07-01-21, 19:15, Geert Uytterhoeven wrote:
> The DMACs (both SYS-DMAC and RT-DMAC) on R-Car V3U differ slightly from
> the DMACs on R-Car Gen2 and other R-Car Gen3 SoCs:
> 1. The per-channel registers are located in a second register block.
> Add support for mapping the second block, usin
On 07-01-21, 19:15, Geert Uytterhoeven wrote:
> Add and helper macro for iterating over all DMAC channels, taking into
> account the channel mask. Use it where appropriate, to simplify code.
>
> Restore "reverse Christmas tree" order of local variables while adding a
> new variable.
>
> Signed-o
On 14-12-20, 10:13, Peter Ujfalusi wrote:
> The UDMA and BCDMA can provide higher throughput if the burst_size of the
> channel is changed from it's default (which is 64 bytes) for Ultra-high
> and high capacity channels.
>
> This performance benefit is even more visible when the buffers are align
On 12-01-21, 15:01, mda...@codeaurora.org wrote:
> On 2020-12-21 23:03, mda...@codeaurora.org wrote:
> > On 2020-12-21 14:53, Vinod Koul wrote:
> > > Hello,
> > >
> > > On 17-12-20, 20:07, Md Sadre Alam wrote:
> > > > This change will add support f
On 11-01-21, 12:14, Bjorn Andersson wrote:
> On Mon 11 Jan 09:16 CST 2021, Vinod Koul wrote:
>
> > This adds capability to use GSI DMA for I2C transfers
> >
> > Signed-off-by: Vinod Koul
> > ---
> > drivers/i2c/busses/i2c-qcom-geni.c | 246 ++
On 11-01-21, 12:23, Bjorn Andersson wrote:
> On Mon 11 Jan 09:16 CST 2021, Vinod Koul wrote:
>
> > This add the device node for gpi dma0 instances found in sdm845.
>
> I think the 0 in "dma0" should go?
oops, will update
>
> Apart from that, this looks good
On 11-01-21, 21:45, Konrad Dybcio wrote:
>
> > If it is working without GPI enabled, it would work.. GPI for QUP is
> > something that requires firmware and would have to be enabled by
> > firmware
>
>
> I think with the new code of yours:
>
>
> mas->tx = dma_request_slave_channel(mas->dev, "t
On 11-01-21, 08:47, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 11, 2021 at 7:18 AM Vinod Koul wrote:
> >
> > @@ -2622,6 +2626,13 @@ pinmux {
> >"gpio2", "gpio3";
> >
Hi Konrad,
On 11-01-21, 17:04, Konrad Dybcio wrote:
> Hi,
>
> looks like sdm845-cheza also uses the spi0 bus, which as far as I
> understand is going to break with the GPI DMA disabled. Perhaps it
> should also be enabled over there?
If it is working without GPI enabled, it would work.. GPI for
On 11-01-21, 09:34, Bjorn Andersson wrote:
> On Mon 11 Jan 09:16 CST 2021, Vinod Koul wrote:
>
> > I2C geni driver needs to access struct geni_wrapper, so move it to
> > header.
> >
>
> Please tell me more!
>
> Glanced through the other patches and the
On 11-01-21, 09:40, Bjorn Andersson wrote:
> On Mon 11 Jan 09:16 CST 2021, Vinod Koul wrote:
>
> > GPI DMA is one of the DMA modes supported on geni, this adds support to
> > enable that mode
> >
> > Signed-off-by: Vinod Koul
> > ---
>
Add dmas property for spi@88 and pinconf setting so that we can use
dma for this spi device. Also, add iommu properties for qup and spi.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4
arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +++
2 files
This adds capability to use GSI DMA for I2C transfers
Signed-off-by: Vinod Koul
---
drivers/i2c/busses/i2c-qcom-geni.c | 246 -
1 file changed, 244 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c
b/drivers/i2c/busses/i2c-qcom-geni.c
We can use GPI DMA for devices where it is enabled by firmware. Add
support for this mode
Signed-off-by: Vinod Koul
---
drivers/spi/spi-geni-qcom.c | 395 +++-
1 file changed, 384 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers
This add the device node for gpi dma0 instances found in sdm845.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 46
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
GPI DMA is one of the DMA modes supported on geni, this adds support to
enable that mode
Signed-off-by: Vinod Koul
---
drivers/soc/qcom/qcom-geni-se.c | 39 -
include/linux/qcom-geni-se.h| 4
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git
I2C geni driver needs to access struct geni_wrapper, so move it to
header.
Signed-off-by: Vinod Koul
---
drivers/soc/qcom/qcom-geni-se.c | 15 ---
include/linux/qcom-geni-se.h| 15 +++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/soc/qcom
GENI_IF_DISABLE_RO is used by geni spi driver as well to check the
status if GENI, so move this to common header qcom-geni-se.h
Signed-off-by: Vinod Koul
---
drivers/soc/qcom/qcom-geni-se.c | 1 -
include/linux/qcom-geni-se.h| 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git
dma nodes and enable dma for spi found in Rb3 board.
To merge this, we could merge all thru qcom tree with ack on spi/i2c.
Vinod Koul (7):
soc: qcom: geni: move GENI_IF_DISABLE_RO to common header
soc: qcom: geni: move struct geni_wrapper to header
soc: qcom: geni: Add support for gpi dma
Hello Linus,
Please pull to receive fixes for dmaengine drivers. Odd fixes for few
drivers.
The following changes since commit 5c8fe583cce542aa0b84adc939ce85293de36e5e:
Linux 5.11-rc1 (2020-12-27 15:30:22 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/ker
Hi Greg,
Please pull to receive couple of driver fixes for generic phy subsystem.
All these are in linux-next
The following changes since commit 5c8fe583cce542aa0b84adc939ce85293de36e5e:
Linux 5.11-rc1 (2020-12-27 15:30:22 -0800)
are available in the Git repository at:
git://git.kernel.org
On 07-01-21, 17:40, Thomas Bogendoerfer wrote:
> On Wed, Jan 06, 2021 at 11:10:38AM -0800, Joe Perches wrote:
> > On Tue, 2021-01-05 at 15:02 +0100, Thomas Bogendoerfer wrote:
> > > Signed-off-by: Thomas Bogendoerfer
> > []
> > > diff --git a/drivers/dma/txx9dmac.h b/drivers/dma/txx9dmac.h
> > []
Hi Bjorn,
On 07-01-21, 11:17, Bjorn Andersson wrote:
> On Tue 05 Jan 23:49 CST 2021, Vinod Koul wrote:
> > +#PIN CONFIGURATION NODES
> > +patternProperties:
> > + '-pinmux$':
>
> I believe that what Rob was asking for was the matter of describing the
>
T.
>
> This was done for the MTP and the Pocophone, but not for DB845c and the
> Lenovo Yoga C630 - causing these to fail to boot if the LPASS clock
> controller is enabled (which it typically isn't).
Reviewed-by: Vinod Koul
Tested-by: Vinod Koul #on db845c
--
~Vinod
On 24-12-20, 21:22, Zheng Yongjun wrote:
> mutex lock can be initialized automatically with DEFINE_MUTEX()
> rather than explicitly calling mutex_init().
Applied, thanks
--
~Vinod
On 28-12-20, 21:30, Alexandre Belloni wrote:
> linux/platform_data/dma-atmel.h is only used by the at_hdmac driver. Move
> the CFG bits definitions back in at_hdmac_regs.h and the remaining
> definitions in the driver.
Applied, thanks...
> /* Bitfields in CFG */
> -/* are in at_hdmac.h */
> +#de
On 29-12-20, 23:17, Cristian Ciocaltea wrote:
> The DMA controller present on the Actions Semi S500 SoC is compatible
> with the S900 variant, so add it to the list of devices supported by
> the Actions Semi Owl DMA driver. Additionally, order the entries
> alphabetically.
Applied, thanks
--
~Vi
On 29-12-20, 23:17, Cristian Ciocaltea wrote:
> Add a new compatible string corresponding to the DMA controller found
> in the S500 variant of the Actions Semi Owl SoCs family. Additionally,
> order the entries alphabetically.
Applied, thanks
--
~Vinod
On 05-01-21, 15:02, Thomas Bogendoerfer wrote:
> Signed-off-by: Thomas Bogendoerfer
Applied after fixing subsystem name, thanks
--
~Vinod
On 29-12-20, 21:50, Zheng Yongjun wrote:
> Use kzalloc rather than kcalloc(1,...)
>
> The semantic patch that makes this change is as follows:
> (http://coccinelle.lip6.fr/)
>
> //
> @@
> @@
>
> - kcalloc(1,
> + kzalloc(
> ...)
> //
Applied, thanks
--
~Vinod
HeY Mark,
On 09-12-20, 13:34, Bard Liao wrote:
> sdw_update_slave_status will be invoked when a codec is attached,
> and the codec driver will initialize the codec with regmap functions
> while the codec device is pm_runtime suspended.
>
> regmap routines currently rely on regular SoundWire IO fu
This add binding and driver for TLMM block found in SM8350 SoC
Changes since v2:
- rename to qcom,sm8350-tlmm along with binding and driver structs
- fix some nits in binding pointer by Rob
Raghavendra Rao Ananta (1):
pinctrl: qcom: Add SM8350 pinctrl driver
Vinod Koul (1):
dt-bindings
Add device tree binding Documentation details for Qualcomm SM8350
pinctrl driver.
Signed-off-by: Vinod Koul
---
.../bindings/pinctrl/qcom,sm8350-tlmm.yaml| 149 ++
1 file changed, 149 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,sm8350
From: Raghavendra Rao Ananta
This adds pincontrol driver for tlmm block found in SM8350 SoC
Signed-off-by: Raghavendra Rao Ananta
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers
Hi Mani,
On 05-01-21, 21:20, Vinod Koul wrote:
> On 05-01-21, 17:56, Manivannan Sadhasivam wrote:
> > Add qpic_bam node to support QPIC BAM DMA controller on SDX55 platform.
>
> Reviewed-by: Vinod Koul
>
> >
> > Signed-off-by: Manivannan Sadhasivam
> > -
cs404-sdhci", "qcom,sdhci-msm-v5"
> "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
> + "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
Keep this sorted?
With that:
Reviewed-by: Vinod Koul
> NOTE that some old device tree files m
On 05-01-21, 17:56, Manivannan Sadhasivam wrote:
> Add smem node to support shared memory manager on SDX55 platform.
Reviewed-by: Vinod Koul
>
> Signed-off-by: Manivannan Sadhasivam
> ---
> arch/arm/boot/dts/qcom-sdx55.dtsi | 6 ++
> 1 file changed, 6 insertions(+)
>
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