On 10-11-20, 15:46, Geert Uytterhoeven wrote:
> The Intel Keem Bay eMMC PHY is only present on Intel Keem Bay SoCs.
> Hence add a dependency on ARCH_KEEMBAY, to prevent asking the user about
> this driver when configuring a kernel without Intel Keem Bay platform
> support.
Applied, thanks
--
On 10-11-20, 11:23, Amelie Delaunay wrote:
> Change stm32-usbphyc driver to not print an error message when the device
> probe operation is deferred.
Applied all, thanks
--
~Vinod
On 09-11-20, 22:58, Rikard Falkeborn wrote:
> The only usage of tegra_xusb_pad_type and tegra_xusb_port_type is to
> assign their address to the type field in the device struct, which is a
> const pointer. Make them const to allow the compiler to put them in
> read-only memory.
Applied, thanks
On 03-11-20, 09:25, Kishon Vijay Abraham I wrote:
> Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
> de-asserts PHY_RESET even before the configurations are loaded in
> phy_init(). However PHY_RESET should be de-asserted only after
> all the configurations has been initialized,
On 03-11-20, 09:25, Kishon Vijay Abraham I wrote:
> From: Faiz Abbas
>
> Serdes lanes might be shared between multiple cores in some usecases
> and its not possible to lock PLLs for both the lanes independently
> by the two cores. This requires a bootloader to configure both the
> lanes at early
On 02-11-20, 07:08, Chun-Kuang Hu wrote:
> + Vinod:
>
> Hi, Chunfeng:
>
> Chunfeng Yun 於 2020年10月30日 週五 下午2:24寫道：
> >
> > On Thu, 2020-10-29 at 23:27 +0800, Chun-Kuang Hu wrote:
> > > mtk_mipi_dsi_phy is currently placed inside mediatek drm driver, but it's
> > > more suitable to place a phy
On 03-11-20, 12:37, Yejune Deng wrote:
> devm_reset_control_array_get_exclusive() looks more readable
Applied, thanks
--
~Vinod
On 06-11-20, 14:08, Chunfeng Yun wrote:
> Use devm_platform_ioremap_resource(_byname) to simplify code
Applied all, thanks
--
~Vinod
On 28-10-20, 16:22, Swapnil Jakhade wrote:
> Add Cadence Sierra PHY bindings in YAML format.
Applied, thanks
--
~Vinod
On 27-10-20, 22:30, Manivannan Sadhasivam wrote:
> SM8250 has multiple different PHY versions:
> QMP GEN3x1 PHY - 1 lane
> QMP GEN3x2 PHY - 2 lanes
> QMP Modem PHY - 2 lanes
>
> Add support for these with relevant init sequence. In order to abstract
> the init sequence, this commit introduces
On 27-10-20, 22:30, Manivannan Sadhasivam wrote:
> Add the below three PCIe PHYs found in SM8250 to the QMP binding:
>
> QMP GEN3x1 PHY - 1 lane
> QMP GEN3x2 PHY - 2 lanes
> QMP Modem PHY - 2 lanes
>
Applied, thanks
--
~Vinod
On 14-11-20, 19:17, Bjorn Andersson wrote:
> > > +enum {
> > > + P_BI_TCXO,
> > > + P_CORE_BI_PLL_TEST_SE,
> >
> > This is for test and we removed this for upstream, so can you do that as
> > well (not parent will decrease for clks below)
> >
>
> We have several other platforms that includes
HI Linus,
On 10-11-20, 15:47, Linus Walleij wrote:
> On Mon, Nov 9, 2020 at 7:26 AM Vinod Koul wrote:
>
> > This series add device tree binding documentation and driver for SDX55 SOC
> > pincontroller.
> >
> > Changes in v3:
> > - Add ack by Bjorn
> >
Commit be117ca32261 ("pinctrl: qcom: Kconfig: Rework PINCTRL_MSM to be a
dependency rather then a selected config") moved the qcom pinctrl drivers
to have PINCTRL_MSM as dependency rather then a selected config, so do
this change for SDX55 pinctrl driver as well.
Signed-off-by:
On 10-11-20, 16:51, Frank Lee wrote:
> On Tue, Nov 10, 2020 at 4:43 PM Krzysztof Kozlowski wrote:
> >
> > On Tue, 10 Nov 2020 at 07:00, Frank Lee wrote:
> > >
> > > It seems that sending too many e-mails at one time will cause some
> > > emails to fail to be sent out. I will try again.
> >
> >
On 09-11-20, 19:04, Jonathan McDowell wrote:
> On Mon, Nov 09, 2020 at 05:11:21PM +0530, Vinod Koul wrote:
> > HI Jonathan,
> >
> > On 23-09-20, 20:40, Jonathan McDowell wrote:
> > > Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
> &g
On 04-11-20, 12:30, Radhey Shyam Pandey wrote:
> This patchset fixes usage of mcdma tx segment and SG capability.
> It also make use of readl_poll_timeout_atomic variant.
Applied, thanks
--
~Vinod
HI Peter,
On 09-11-20, 14:09, Peter Ujfalusi wrote:
> Hi Vinod,
>
> On 09/11/2020 13.45, Vinod Koul wrote:
> >> Without a channel number I can not do anything.
> >> It is close to a chicken and egg problem.
> >
> > We get 'channel' in xlate, so won
On 30-10-20, 22:30, Grygorii Strashko wrote:
> The NAVSS UDMA will stuck if target IP module is disabled by PM while PSI-L
> threads are paired UDMA<->IP and no further transfers is possible. This
> could be the case for IPs J721E Main CPSW (cpsw9g).
>
> Hence, to avoid such situation do PSI-L
Hey Peter,
On 28-10-20, 11:56, Peter Ujfalusi wrote:
> Hi Vinod,
>
> On 28/10/2020 7.55, Vinod Koul wrote:
>
> >> To summarize:
> >> In of_dma_route_allocate() the router does not yet know the channel we
> >> are going to get.
> >> In
HI Jonathan,
On 23-09-20, 20:40, Jonathan McDowell wrote:
> Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
> controller found in the MSM8x60 and IPQ/APQ8064 platforms.
Mostly it looks good, some nitpicks
> The ADM supports both memory to memory transactions and memory
>
On 27-10-20, 14:38, Sia Jee Heng wrote:
> Add support for Intel KeemBay DMA registers. These registers are required
> to run data transfer between device to memory and memory to device on Intel
> KeemBay SoC.
Again this should come first, you need to add all the bits required to
support this soc
On 27-10-20, 14:38, Sia Jee Heng wrote:
> Add support for Intel KeemBay AxiDMA to the dw-axi-dmac
> Schemas DT binding.
This patch should be 10th one, we add binding before its use in the
drivers
>
> Signed-off-by: Sia Jee Heng
> ---
> .../bindings/dma/snps,dw-axi-dmac.yaml| 25
On 27-10-20, 14:38, Sia Jee Heng wrote:
> Add support for DMA_RESIDUE_GRANULARITY_BURST so that AxiDMA can report
> DMA residue.
>
> Existing AxiDMA driver only support data transfer between
> memory to memory operation, therefore reporting DMA residue
> to the DMA clients is not supported.
>
>
On 27-10-20, 14:38, Sia Jee Heng wrote:
> Add support for device_prep_dma_cyclic() callback function to benefit
> DMA cyclic client, for example ALSA.
>
> Existing AxiDMA driver only support data transfer between memory to memory.
> Data transfer between device to memory and memory to device in
On 27-10-20, 14:38, Sia Jee Heng wrote:
> YAML schemas Device Tree (DT) binding is the new format for DT to replace
> the old format. Introduce YAML schemas DT binding for dw-axi-dmac and
> remove the old version.
I see that Rob and DT folks have not been cced, please do so
>
> Signed-off-by:
Some complex dmaengine controllers have capability to program the
peripheral device, so pass on the peripheral configuration as part of
dma_slave_config
Signed-off-by: Vinod Koul
---
include/linux/dmaengine.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/linux/dmaengine.h b
This controller provides DMAengine capabilities for a variety of peripheral
buses such as I2C, UART, and SPI. By using GPI dmaengine driver, bus
drivers can use a standardize interface that is protocol independent to
transfer data between memory and peripheral.
Signed-off-by: Vinod Koul
Add devicetree binding documentation for GPI DMA controller
implemented on Qualcomm SoCs
Reviewed-by: Rob Herring
Signed-off-by: Vinod Koul
---
.../devicetree/bindings/dma/qcom,gpi.yaml | 88 +++
include/dt-bindings/dma/qcom-gpi.h| 11 +++
2 files changed, 99
- Move submit queue for transactions to issue_pending
Vinod Koul (3):
dt-bindings: dmaengine: Document qcom,gpi dma binding
dmaengine: add peripheral configuration
dmaengine: qcom: Add GPI dma driver
.../devicetree/bindings/dma/qcom,gpi.yaml | 88 +
drivers/dma/qcom/Kconfig
From: Jeevan Shriram
Add initial Qualcomm SDX55 pinctrl driver to support pin configuration
with pinctrl framewor for SDX55 SoC.
Signed-off-by: Jeevan Shriram
Reviewed-by: Bjorn Andersson
[ported from downstream and tidy up]
Signed-off-by: Vinod Koul
---
drivers/pinctrl/qcom/Kconfig
Add device tree binding Documentation details for Qualcomm SDX55
pinctrl driver.
Reviewed-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
.../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 154 ++
1 file changed, 154 insertions(+)
create mode 100644
Documentation/devicetree
Shriram (1):
pinctrl: qcom: Add SDX55 pincontrol driver
Vinod Koul (1):
dt-bindings: pinctrl: qcom: Add SDX55 pinctrl bindings
.../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 154 +++
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl/qcom/Makefile |1
On 05-11-20, 15:14, Linus Walleij wrote:
> On Tue, Nov 3, 2020 at 6:58 AM Vinod Koul wrote:
>
> > From: Jeevan Shriram
> >
> > Add initial Qualcomm SDX55 pinctrl driver to support pin configuration
> > with pinctrl framewor for SDX55 SoC.
> >
> > Signe
On 05-11-20, 16:18, Manivannan Sadhasivam wrote:
> Add support for following clocks maintained by RPMh in SDX55 SoCs.
>
> * BI TCXO
> * RF_CLK1
> * RF_CLK1_AO
> * RF_CLK2
> * RF_CLK2_AO
> * QPIC (Qualcomm Technologies, Inc. Parallel Interface Controller)
Reviewed-by: Vinod Koul
--
~Vinod
uot;
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "reset.h"
> +
> +enum {
> + P_BI_TCXO,
> + P_CORE_BI_PLL_TEST_SE,
This is for test and we removed this for upstream, so can you do that as
well (not parent will decrease for clks below)
With that updated:
Reviewed-by: Vinod Koul
--
~Vinod
Add devicetree binding documentation for GPI DMA controller
implemented on Qualcomm SoCs
Reviewed-by: Rob Herring
Signed-off-by: Vinod Koul
---
.../devicetree/bindings/dma/qcom,gpi.yaml | 90 +++
include/dt-bindings/dma/qcom-gpi.h| 11 +++
2 files changed, 101
This controller provides DMAengine capabilities for a variety of peripheral
buses such as I2C, UART, and SPI. By using GPI dmaengine driver, bus
drivers can use a standardize interface that is protocol independent to
transfer data between memory and peripheral.
Signed-off-by: Vinod Koul
Some complex dmaengine controllers have capability to program the
peripheral device, so pass on the peripheral configuration as part of
dma_slave_config
Signed-off-by: Vinod Koul
---
include/linux/dmaengine.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/linux/dmaengine.h b
to issue_pending
Vinod Koul (3):
dt-bindings: dmaengine: Document qcom,gpi dma binding
dmaengine: add peripheral configuration
dmaengine: qcom: Add GPI dma driver
.../devicetree/bindings/dma/qcom,gpi.yaml | 90 +
drivers/dma/qcom/Kconfig | 12 +
drivers/dma/qcom/Makefile
Hi,
Thanks Doug for adding me
On 02-11-20, 08:37, Doug Anderson wrote:
> > On Thu, Oct 29, 2020 at 06:17:34PM -0700, Stephen Boyd wrote:
> > Any chance we can convince you to prepare this bridge driver for use in
> > a chained bridge setup where the connector is created by the display
> >
e
> might be fatal. For systems getting past this the default timeout of 0
> seconds for probe deferral of many subsystems causes the system to be
> completely useless.
>
> So, make Command DB builtin.
Reviewed-by: Vinod Koul
--
~Vinod
From: Jeevan Shriram
Add initial Qualcomm SDX55 pinctrl driver to support pin configuration
with pinctrl framewor for SDX55 SoC.
Signed-off-by: Jeevan Shriram
[ported from downstream and tidy up]
Signed-off-by: Vinod Koul
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl
Add device tree binding Documentation details for Qualcomm SDX55
pinctrl driver.
Signed-off-by: Vinod Koul
---
.../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 145 ++
1 file changed, 145 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,sdx55
On 26-09-20, 01:58, Lubomir Rintel wrote:
> Hi,
>
> please consider applying this patch set. It adds the HSIC PHY driver for
> Marvell MMP3 along with related DT binding changes.
>
> In response to previous submission it was suggested that a cast of
> private data be removed, but it actually
On 28-10-20, 11:35, Bjorn Andersson wrote:
> On Wed 28 Oct 03:30 CDT 2020, Vinod Koul wrote:
> > diff --git a/drivers/pinctrl/qcom/pinctrl-sdx55.c
> > b/drivers/pinctrl/qcom/pinctrl-sdx55.c
> [..]
> > +static const struct msm_function sdx55_functions[] = {
> [..]
On 29-10-20, 13:20, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the phy-next tree got a conflict in:
>
> MAINTAINERS
>
> between commit:
>
> 43c3e148830a ("MAINTAINERS: Add entry for Qualcomm IPQ4019 VQMMC regulator")
>
> from the regulator-fixes tree and commit:
>
On 13-10-20, 10:58, Marc Zyngier wrote:
> If, for some reason, the xusb PHY fails to probe, it leaves
> a dangling pointer attached to the platform device structure.
>
> This would normally be harmless, but the Tegra XHCI driver then
> goes and extract that pointer from the PHY device. Things go
On 16-10-20, 22:46, Robert Marko wrote:
> Add maintainers entry for the Qualcomm IPQ4019 USB PHY driver.
Applied, thanks
--
~Vinod
On 08-10-20, 09:41, Peter Ujfalusi wrote:
>
>
> On 07/10/2020 18.55, Vinod Koul wrote:
> > On 07-10-20, 11:08, Peter Ujfalusi wrote:
> >
> >> Not really. In DT an event triggered channel can be requested via router
> >> (when this is used) fo
On 16-10-20, 11:17, Eugen Hristev wrote:
> Add compatible to sama7g5 SoC.
Applied all, thanks
Btw the threading was broken in this series, please do ensure that
patches are threaded properly.
--
~Vinod
From: Jeevan Shriram
Add initial Qualcomm SDX55 pinctrl driver to support pin configuration
with pinctrl framewor for SDX55 SoC.
Signed-off-by: Jeevan Shriram
[ported from downstream and tidy up]
Signed-off-by: Vinod Koul
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl
On 08-10-20, 09:18, Gustavo A. R. Silva wrote:
> Make use of the new struct_size() helper instead of the offsetof() idiom.
Applied, thanks
--
~Vinod
On 25-10-20, 18:11, Jonathan McDowell wrote:
> Gentle ping on this one; looks like I missed the window for 5.10, but is
> there anything outstanding for it to hit 5.11 or should I just have
> patience?
That would be appreciated, it is in my queue and I should be able to
review in few days or
On 26-09-20, 22:58, Rikard Falkeborn wrote:
> The only usage of imx8mp_usb_phy_ops is to assign its address to the
> data field in the of_device_id struct, which is a const void pointer.
> Make it const to allow the compiler to put it in read-only memory.
Applied, thanks
--
~Vinod
Add device tree binding Documentation details for Qualcomm SDX55
pinctrl driver.
Signed-off-by: Vinod Koul
---
.../bindings/pinctrl/qcom,sdx55-pinctrl.yaml | 144 ++
1 file changed, 144 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,sdx55
On 16-10-20, 16:03, Surendran K wrote:
> _setup_req(..) never returns negative value.
> Hence the condition ret < 0 is never met
Applied, thanks
--
~Vinod
On 19-10-20, 17:57, Krzysztof Kozlowski wrote:
> The ppc440spe_adma_chan_list file-scope variable is not used outside of
> the unit so it can be made static.
Applied both, thanks
--
~Vinod
On 02-10-20, 15:01, Al Cooper wrote:
> The 7211a0 has a tca_drv_sel bit in the USB SETUP register that
> should never be enabled. This feature is only used if there is a
> USB Type-C PHY, and the 7211 does not have one. If the bit is
> enabled, the VBUS signal will never be asserted. In the
best to avoid any
> > potential build breakage.
> >
> > Cc: Nikhil Rao
> > Reviewed-by: Ashutosh Dixit
> > Signed-off-by: Sudeep Dutt
>
> I like deleting code, can this go into 5.10-final?
I would like that, if unused lets get it cleaned now rather than later
:-)
Said that, for all dmaengine bits:
Acked-By: Vinod Koul
--
~Vinod
On 26-10-20, 17:01, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> gcc warns about a mismatch argument type when passing
> 'false' into a function that expects an enum:
>
> drivers/dma/ti/k3-udma-private.c: In function 'xudma_tchan_get':
> drivers/dma/ti/k3-udma-private.c:86:34: warning:
On 28-10-20, 16:59, Zou Wei wrote:
> Fixes coccicheck error:
>
> ./drivers/phy/motorola/phy-cpcap-usb.c:365:9-34: ERROR:
> Threaded IRQ with no primary handler requested without IRQF_ONESHOT
Applied, thanks
--
~Vinod
On 26-10-20, 13:59, Stephen Boyd wrote:
> This probe function is too complicated and should be refactored. For now
> let's just set this variable to NULL and keep the static analysis tools
> happy.
Applied, thanks
--
~Vinod
DMA controller binding describes the node name should be dma-controller
and not dma, so fix the node name
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64
DMA controller binding describes the node name should be dma-controller
and not dma, so fix the node name
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi
b/arch/arm64
DMA controller binding describes the node name should be dma-controller
and not dma, so fix the node name
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi
b/arch/arm64
DMA controller binding describes the node name should be dma-controller
and not dma, so fix the node name
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi
b/arch
DMA controller binding describes the node name should be dma-controller
and not dma, so fix the node name
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64
DMA controller binding describes the node name should be dma-controller
and not dma, so fix the node name
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi
b/arch/arm64
DMA controller binding describes the node name should be dma-controller
and not dma, so fix the node name
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64
DMA controller binding describes the node name should be dma-controller
and not dma, so fix the node name
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
b/arch
DMA controller binding describes the node name should be dma-controller
and not dma, so fix the node name
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch
DMA controller binding describes the node name should be dma-controller
and not dma, so fix the node name in the qcom dts files
Vinod Koul (9):
arm64: dts: sdm845: Fix dma node name
arm64: dts: sdm630: Fix dma node name
arm64: dts: qcs404: Fix dma node name
arm64: dts: msm8916: Fix dma
Hi Bjorn, Steve,
On 20-10-20, 08:03, Bjorn Andersson wrote:
> From: Stephen Boyd
>
> The SMMU that sits in front of the QUP needs to be programmed properly
> so that the i2c geni driver can allocate DMA descriptors. Failure to do
> this leads to faults when using devices such as an i2c
Hi Eugen,
On 16-10-20, 06:45, eugen.hris...@microchip.com wrote:
> On 23.09.2020 02:33, Rob Herring wrote:
>
> > On Mon, Sep 14, 2020 at 05:09:55PM +0300, Eugen Hristev wrote:
> >> Add optional microchip,m2m property that specifies if a controller is
> >> dedicated to memory to memory operations
generic power management
Vinod Koul (12):
Merge tag 'v5.9-rc4' into next
dmaengine: sf-pdma: remove unused 'desc'
dmaengine: sf-pdma: remove unused 'desc'
Merge branch 'fixes' into next
dmaengine: pl330: fix argument for tasklet
Merge branch 'topic/tasklet
On 13-10-20, 17:17, Surendran K wrote:
> _setup_req(..) never returns negative value.
> Hence the condition ret < 0 is never met
The subsystem is "dmaengine", git log would tell you the tags to use
>
> Signed-off-by: Surendran K
> ---
> drivers/dma/pl330.c | 2 --
> 1 file changed, 2
On 13-10-20, 07:12, Sia, Jee Heng wrote:
>
>
> > -Original Message-
> > From: Vinod Koul
> > Sent: 13 October 2020 3:01 PM
> > To: Sia, Jee Heng
> > Cc: Andy Shevchenko ;
> > eugeniy.palt...@synopsys.com; dmaeng...@vger.kernel.org; linux-
On 12-10-20, 13:57, Rob Herring wrote:
> On Thu, Oct 08, 2020 at 06:01:49PM +0530, Vinod Koul wrote:
> > Add devicetree binding documentation for GPI DMA controller
> > implemented on Qualcomm SoCs
> >
> > Signed-off-by: Vinod Koul
> > ---
> > .../devicet
On 13-10-20, 05:49, Sia, Jee Heng wrote:
> > >
> > > This patch set is to replace the patch series submitted at:
> > > https://lore.kernel.org/dmaengine/1599213094-30144-1-git-send-email-je
> > > e.heng@intel.com/
> >
> > And it means effectively the bumped version, besides the fact that you
On 09-10-20, 14:29, Peter Ujfalusi wrote:
>
>
> On 09/10/2020 14.15, Vinod Koul wrote:
> >>> If for any any reason subsequent txn is for different direction, I would
> >>> expect that parameters are set again before prep_ calls
> >>
> >>
On 09-10-20, 13:45, Peter Ujfalusi wrote:
> Hi Vinod,
>
> On 09/10/2020 13.30, Vinod Koul wrote:
> > Hi Peter,
> >
> > On 09-10-20, 12:04, Peter Ujfalusi wrote:
> >> On 08/10/2020 15.31, Vinod Koul wrote:
> >>> Some complex dmaengine controllers
On 09-10-20, 12:00, Peter Ujfalusi wrote:
> Hi Vinod,
>
> On 08/10/2020 15.31, Vinod Koul wrote:
> > This controller provides DMAengine capabilities for a variety of peripheral
> > buses such as I2C, UART, and SPI. By using GPI dmaengine driver, bus
> > drivers can
Hi Peter,
On 09-10-20, 12:04, Peter Ujfalusi wrote:
> On 08/10/2020 15.31, Vinod Koul wrote:
> > Some complex dmaengine controllers have capability to program the
> > peripheral device, so pass on the peripheral configuration as part of
> > dma_slave_config
> >
&g
On 08-10-20, 19:34, Manivannan Sadhasivam wrote:
> On Wed, Oct 07, 2020 at 02:01:13PM +0530, Vinod Koul wrote:
> > Driver doesn't use keyword enum for enum owl_dmadesc_offsets resulting
> > in warning:
> >
> > drivers/dma/owl-dma.c:139: warning: cannot understand fu
This controller provides DMAengine capabilities for a variety of peripheral
buses such as I2C, UART, and SPI. By using GPI dmaengine driver, bus
drivers can use a standardize interface that is protocol independent to
transfer data between memory and peripheral.
Signed-off-by: Vinod Koul
Some complex dmaengine controllers have capability to program the
peripheral device, so pass on the peripheral configuration as part of
dma_slave_config
Signed-off-by: Vinod Koul
---
include/linux/dmaengine.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/linux/dmaengine.h b
Add devicetree binding documentation for GPI DMA controller
implemented on Qualcomm SoCs
Signed-off-by: Vinod Koul
---
.../devicetree/bindings/dma/qcom,gpi.yaml | 86 +++
include/dt-bindings/dma/qcom-gpi.h| 11 +++
2 files changed, 97 insertions(+)
create mode
on testing feedback
Changes in v2:
- Update the binding and drop qcom specific properties
- Move peripheral configuration as a pointer
- Move submit queue for transactions to issue_pending
Vinod Koul (3):
dt-bindings: dmaengine: Document qcom,gpi dma binding
dmaengine: add peripheral configuration
On 07-10-20, 11:08, Peter Ujfalusi wrote:
> Not really. In DT an event triggered channel can be requested via router
> (when this is used) for example:
>
> dmas = <_l2g a b c>;
> a - the input number of the DMA request in l2g
> b - edge or level trigger to be selected
> c - ASEL number for the
On 07-10-20, 12:04, Borislav Petkov wrote:
> On Wed, Oct 07, 2020 at 03:23:13PM +0530, Vinod Koul wrote:
> > Right my build failed for x86 and I have dropped these now. I would have
> > expected the dependency to be a signed tag to be cross merged when I was
> > asked to m
Hi Peter,
On 02-10-20, 11:48, Peter Ujfalusi wrote:
> It depends which is best for the use case.
> I see the metadata useful when you need to send different
> metadata/configuration with each transfer.
> It can be also useful when you need it seldom, but for your use case and
> setup the
On 07-10-20, 10:48, Borislav Petkov wrote:
> On Wed, Oct 07, 2020 at 12:31:32PM +0530, Vinod Koul wrote:
> > Applied, thanks
>
> I'm tired of repeating what you should've done - your branch doesn't
> even build. How did you test it?
Right my build failed for x86 and I have dr
let_setup() API")
Signed-off-by: Vinod Koul
---
drivers/dma/xilinx/zynqmp_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c
index 15b0f961fdf8..d8419565b92c 100644
--- a/drivers/dma/xilinx/zynqmp_dma.c
+++
() API")
Signed-off-by: Vinod Koul
---
drivers/dma/qcom/bam_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c
index 0ea9b9c9ce85..4eeb8bb27279 100644
--- a/drivers/dma/qcom/bam_dma.c
+++ b/drivers/dma/qcom/bam_dma.
Driver doesn't use keyword enum for enum owl_dmadesc_offsets resulting
in warning:
drivers/dma/owl-dma.c:139: warning: cannot understand function prototype:
'enum owl_dmadesc_offsets '
So add the keyword to fix it and also add documentation for missing
OWL_DMADESC_SIZE
Signed-off-by: Vinod Koul
let_setup() API")
Signed-off-by: Vinod Koul
---
drivers/dma/xilinx/xilinx_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index a9eb85ee6daf..ecff35402860 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++
or member 't'
not described in 'xilinx_dma_do_tasklet'
drivers/dma/xilinx/xilinx_dma.c:1050: warning: Excess function parameter 'data'
description in 'xilinx_dma_do_tasklet'
Vinod Koul (5):
dmaengine: altera-msgdma: fix kernel-doc style for tasklet
dmaengine: qcom: bam_dma: fix kernel-doc style
lets to use new
tasklet_setup() API")
Signed-off-by: Vinod Koul
---
drivers/dma/altera-msgdma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/altera-msgdma.c b/drivers/dma/altera-msgdma.c
index 4d6751bf6f11..9a841ce5f0c5 100644
--- a/drivers/dma/altera-msgdma.c
+++
On 05-10-20, 08:11, Dave Jiang wrote:
> == Background ==
> A typical DMA device requires the driver to translate application buffers to
> hardware addresses,
> and a kernel-user transition to notify the hardware of new work. Shared
> Virtual Addressing (SVA)
> allows the processor and device to
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