> -Original Message-
> From: Rob Herring
> Sent: 2019年10月18日 3:03
> To: Xiaowei Bao
> Cc: Z.q. Hou ; bhelg...@google.com;
> mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h. Lian
> ; andrew.mur...@arm.c
> -Original Message-
> From: Russell King - ARM Linux admin
> Sent: 2019年10月15日 17:08
> To: Xiaowei Bao
> Cc: Z.q. Hou ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h
This PCIe controller is based on the Mobiveil GPEX IP, it work in EP
mode if select this config opteration.
Signed-off-by: Xiaowei Bao
---
v2:
- Modify the Copyright.
MAINTAINERS| 2 +
drivers/pci/controller/mobiveil/Kconfig| 17
Add the documentation for the Device Tree binding of the layerscape
PCIe GEN4 controller with EP mode.
Signed-off-by: Xiaowei Bao
---
v2:
- remove the status entry in EP Example.
.../bindings/pci/layerscape-pcie-gen4.txt | 27 +-
1 file changed, 26 insertions
Add the layerscape PCIE GEN4 EP device support in pci_endpoint_test driver.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
drivers/misc/pci_endpoint_test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 6e208a0
Errata: unsupported request error on inbound posted write
transaction, PCIe controller reports advisory error instead
of uncorrectable error message to RC.
Signed-off-by: Xiaowei Bao
---
v3:
- Use BIT replce the expression.
drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c | 13
Add the EP driver support for Mobiveil base on endpoint framework.
Signed-off-by: Xiaowei Bao
---
v2:
- Modify the Copyright.
MAINTAINERS| 1 +
drivers/pci/controller/mobiveil/Kconfig| 5 +
drivers/pci/controller/mobiveil/Makefile
Add the LX2160A PCIe EP node.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 56 ++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl
This patch set are for adding Mobiveil EP driver and adding PCIe Gen4
EP driver of NXP Layerscape platform.
This patch set depends on:
https://patchwork.kernel.org/project/linux-pci/list/?series=159139
Xiaowei Bao (6):
PCI: mobiveil: Add the EP driver support
dt-bindings: Add DT binding
> -Original Message-
> From: Russell King - ARM Linux admin
> Sent: 2019年9月25日 0:50
> To: Xiaowei Bao
> Cc: Z.q. Hou ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h
> -Original Message-
> From: Russell King - ARM Linux admin
> Sent: 2019年9月25日 0:39
> To: Xiaowei Bao
> Cc: Z.q. Hou ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h
> -Original Message-
> From: Shawn Guo
> Sent: 2019年10月6日 11:20
> To: Ashish Kumar
> Cc: devicet...@vger.kernel.org; r...@kernel.org; mark.rutl...@arm.com;
> linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Xiaowei
> Bao
> Subject: Re: [PA
> -Original Message-
> From: Shawn Guo
> Sent: 2019年10月3日 17:11
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; Leo Li
> ; M.h. Lian ; Mingkai Hu
> ; Roy Zang ;
> lorenzo.pieral...@arm.com; linux-...@vger.kernel.org;
> devicet...@vg
> -Original Message-
> From: Rob Herring
> Sent: 2019年10月1日 6:22
> To: Xiaowei Bao
> Cc: Z.q. Hou ; bhelg...@google.com;
> mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h. Lian
> ; andrew.mur...@arm.c
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月30日 22:57
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gm
Add PCIe EP mode support for ls1088a and ls2088a, there are some
difference between LS1 and LS2 platform, so refactor the code of
the EP driver.
Signed-off-by: Xiaowei Bao
---
v2:
- This is a new patch for supporting the ls1088a and ls2088a platform.
v3:
- Adjust the some struct assignment
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao
---
v2:
- Remove the pf-offset proparty.
v3:
- No change.
v4:
- No change.
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 ++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64
Add the doorbell mode of MSI-X in DWC EP driver.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
---
v2:
- Remove the macro of no used.
v3:
- No change.
v4:
- Modify the commit message.
drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++
drivers/pci/controller/dwc
feature.
Signed-off-by: Xiaowei Bao
---
v2:
- Remove duplicate redundant code.
- Reimplement the PF config space access way.
v3:
- Integrate duplicate code for func_select.
- Move PCIE_ATU_FUNC_NUM(pf) (pf << 20) to ((pf) << 20).
- Add the comments for func_conf_select function.
v4
Move the function of getting MSI capability to the front of init
function, because the init function of the EP platform driver will use
the return value by the function of getting MSI capability.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
---
v2:
- No change.
v3:
- No change.
v4
Each PF of EP device should have it's own MSI or MSIX capabitily
struct, so create a dw_pcie_ep_func struct and remove the msi_cap
and msix_cap to this struct from dw_pcie_ep, and manage the PFs
with a list.
Signed-off-by: Xiaowei Bao
---
v3:
- This is a new patch, to fix the issue of MSI
Add the PCIe EP multiple PF support for DWC and Layerscape, add
the doorbell MSIX function for DWC, use list to manage the PF of
one PCIe controller, and refactor the Layerscape EP driver due to
some platforms difference.
Xiaowei Bao (11):
PCI: designware-ep: Add multiple PFs support for DWC
Add LS1088a in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in LS1088a.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
v3:
- No change.
v4:
- Use a maco to define the LS1088a device ID.
drivers/misc/pci_endpoint_test.c | 2 ++
1 file changed, 2 insertions
The different PCIe controller in one board may be have different
capability of MSI or MSIX, so change the way of getting the MSI
capability, make it more flexible.
Signed-off-by: Xiaowei Bao
---
v2:
- Remove the repeated assignment code.
v3:
- Use ep_func msi_cap and msix_cap to decide
the doorbell method to
support the MSIX feature.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
---
v2:
- No change
v3:
- Modify the commit message make it clearly.
v4:
- No change
drivers/pci/controller/dwc/pci-layerscape-ep.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
Fix some format issue of the code in EP driver.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
---
v2:
- No change.
v3:
- No change.
v4:
- No change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci
Add compatible strings for ls1088a and ls2088a.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
v3:
- Use one valid combination of compatible strings.
v4:
- Add the comma between the two compatible.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 2 ++
1 file changed, 2
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月16日 22:38
> To: Xiaowei Bao ; robh...@kernel.org
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ;
Errata: unsupported request error on inbound posted write
transaction, PCIe controller reports advisory error instead
of uncorrectable error message to RC.
Signed-off-by: Xiaowei Bao
---
drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c | 13 +
drivers/pci/controller
Add the layerscape PCIE GEN4 EP device support in pci_endpoint_test driver.
Signed-off-by: Xiaowei Bao
---
drivers/misc/pci_endpoint_test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 6e208a0..8b145a7 100644
Add the documentation for the Device Tree binding of the layerscape
PCIe GEN4 controller with EP mode.
Signed-off-by: Xiaowei Bao
---
.../bindings/pci/layerscape-pcie-gen4.txt | 28 +-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/Documentation
Add the LX2160A PCIe EP node.
Signed-off-by: Xiaowei Bao
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 56 ++
1 file changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index
Add the EP driver support for Mobiveil base on endpoint framework.
Signed-off-by: Xiaowei Bao
---
MAINTAINERS| 1 +
drivers/pci/controller/mobiveil/Kconfig| 5 +
drivers/pci/controller/mobiveil/Makefile | 1 +
drivers/pci
This patch set are for adding Mobiveil EP driver and adding PCIe Gen4
EP driver of NXP Layerscape platform.
This patch set depends on:
https://patchwork.kernel.org/project/linux-pci/list/?series=159139
Xiaowei Bao (6):
PCI: mobiveil: Add the EP driver support
dt-bindings: Add DT binding
This PCIe controller is based on the Mobiveil GPEX IP, it work in EP
mode if select this config opteration.
Signed-off-by: Xiaowei Bao
---
MAINTAINERS| 2 +
drivers/pci/controller/mobiveil/Kconfig| 17 ++-
drivers/pci/controller/mobiveil
> -Original Message-
> From: Gustavo Pimentel
> Sent: 2019年9月12日 19:24
> To: Andrew Murray ; Xiaowei Bao
>
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai H
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月12日 21:02
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gm
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月12日 21:00
> To: Xiaowei Bao ; helg...@kernel.org
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ;
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月12日 20:50
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gm
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月3日 0:26
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gm
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 23:07
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gm
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 21:38
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gm
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 21:37
> To: Xiaowei Bao
> Cc: Kishon Vijay Abraham I ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; lorenzo.pieral...@arm.co
> ; a...@arndb.de; gr
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 21:06
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gm
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 20:55
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gm
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 20:46
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gm
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 20:32
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gm
> -Original Message-
> From: Z.q. Hou
> Sent: 2019年9月2日 11:52
> To: Xiaowei Bao ; robh...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h. Lian
> ; Mingkai Hu ; Roy Zang
> ; jingooh...@gm
Add the PCIe compatible string for LS1028A
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Rob Herring
---
v2:
- No change.
v3:
- No change.
v4:
- No change.
v5:
- No change.
v6:
- No change.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
1 file
Add support for the LS1028a PCIe controller.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
v2:
- No change.
v3:
- Reuse the ls2088 driver data structurt.
v4:
- No change.
v5:
- No change.
v6:
- No change.
drivers/pci/controller/dwc/pci-layerscape.c | 1 +
1 file changed, 1
LS1028a implements 2 PCIe 3.0 controllers.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
v2:
- Fix up the legacy INTx allocate failed issue.
v3:
- No change.
v4:
- Remove the num-lanes property.
v5:
- Add the num-viewport property.
v6:
- move num-viewport to 8.
arch/arm64
Move the function of getting MSI capability to the front of init
function, because the init function of the EP platform driver will use
the return value by the function of getting MSI capability.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
---
v2:
- No change.
v3:
- No change
Add PCIe EP mode support for ls1088a and ls2088a, there are some
difference between LS1 and LS2 platform, so refactor the code of
the EP driver.
Signed-off-by: Xiaowei Bao
---
v2:
- This is a new patch for supporting the ls1088a and ls2088a platform.
v3:
- Adjust the some struct assignment
Fix some format issue of the code in EP driver.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
---
v2:
- No change.
v3:
- No change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci
the doorbell method to
support the MSIX feature.
Signed-off-by: Xiaowei Bao
---
v2:
- No change
v3:
- Modify the commit message make it clearly.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci
Add LS1088a in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in LS1088a.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
v3:
- No change.
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao
---
v2:
- Remove the pf-offset proparty.
v3:
- No change.
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 ++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale
Add compatible strings for ls1088a and ls2088a.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
v3:
- Use one valid combination of compatible strings.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation
The different PCIe controller in one board may be have different
capability of MSI or MSIX, so change the way of getting the MSI
capability, make it more flexible.
Signed-off-by: Xiaowei Bao
---
v2:
- Remove the repeated assignment code.
v3:
- Use ep_func msi_cap and msix_cap to decide
Each PF of EP device should have it's own MSI or MSIX capabitily
struct, so create a dw_pcie_ep_func struct and remover the msi_cap
and msix_cap to this struce, and manage the PFs with a list.
Signed-off-by: Xiaowei Bao
---
v1:
- This is a new patch, to fix the issue of MSI and MSIX CAP way
Add the doorbell mode of MSI-X in EP mode.
Signed-off-by: Xiaowei Bao
Reviewed-by: Andrew Murray
---
v2:
- Remove the macro of no used.
v3:
- No change.
drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++
drivers/pci/controller/dwc/pcie-designware.h| 12
2
*** BLURB HERE ***
Xiaowei Bao (11):
PCI: designware-ep: Add multiple PFs support for DWC
PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode
PCI: designware-ep: Move the function of getting MSI capability
forward
PCI: designware-ep: Modify MSI and MSIX CAP way of finding
Add multiple PFs support for DWC, different PF have different config space
we use pf-offset property which get from the DTS to access the different pF
config space.
Signed-off-by: Xiaowei Bao
---
v2:
- Remove duplicate redundant code.
- Reimplement the PF config space access way.
v3
Add the PCIe compatible string for LS1028A
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Rob Herring
---
v2:
- No change.
v3:
- No change.
v4:
- No change.
v5:
- No change.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
1 file changed, 1 insertion
Add support for the LS1028a PCIe controller.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
v2:
- No change.
v3:
- Reuse the ls2088 driver data structurt.
v4:
- No change.
v5:
- No change.
drivers/pci/controller/dwc/pci-layerscape.c | 1 +
1 file changed, 1 insertion(+)
diff
LS1028a implements 2 PCIe 3.0 controllers.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
v2:
- Fix up the legacy INTx allocate failed issue.
v3:
- No change.
v4:
- Remove the num-lanes property.
v5:
- Add the num-viewport property.
arch/arm64/boot/dts/freescale/fsl
> -Original Message-
> From: Rob Herring
> Sent: 2019年8月28日 6:26
> To: Xiaowei Bao
> Cc: bhelg...@google.com; mark.rutl...@arm.com; shawn...@kernel.org;
> Leo Li ; kis...@ti.com; lorenzo.pieral...@arm.co;
> a...@arndb.de; gre...@linuxfoundation.org; M.h. Lian
>
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月28日 17:01
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月27日 21:11
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月27日 21:34
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月27日 22:49
> To: Xiaowei Bao
> Cc: christophe leroy ; mark.rutl...@arm.com; Roy
> Zang ; lorenzo.pieral...@arm.co; a...@arndb.de;
> devicet...@vger.kernel.org; gre...@linuxfoundation.org;
> linuxppc-...
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月27日 21:25
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月23日 22:28
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
> -Original Message-
> From: Lorenzo Pieralisi
> Sent: 2019年8月23日 22:05
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; M.h. Lian ; Mingkai Hu
> ; Roy Zang ;
> linux-...@vger.kernel.org; devicet...@vger.ke
> -Original Message-
> From: christophe leroy
> Sent: 2019年8月24日 14:45
> To: Xiaowei Bao ; Andrew Murray
>
> Cc: mark.rutl...@arm.com; Roy Zang ;
> lorenzo.pieral...@arm.co; a...@arndb.de; devicet...@vger.kernel.org;
> gre...@linuxfoundation.org; linuxppc-...@l
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月23日 21:39
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月23日 22:28
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月23日 21:58
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月23日 21:45
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月23日 21:36
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月23日 21:25
> To: Xiaowei Bao
> Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> lorenzo.pieral...@arm.co; a...@arndb.de; gre...@linuxfounda
Add the PCIe compatible string for LS1028A
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Reviewed-by: Rob Herring
---
v2:
- No change.
v3:
- No change.
v4:
- No change.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
LS1028a implements 2 PCIe 3.0 controllers.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
v2:
- Fix up the legacy INTx allocate failed issue.
v3:
- No change.
v4:
- Remove the num-lanes proparty.
depends on: https://patchwork.kernel.org/project/linux-pci/list/?series=162215
Add support for the LS1028a PCIe controller.
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
---
v2:
- No change.
v3:
- Reuse the ls2088 driver data structurt.
v4:
- No change.
drivers/pci/controller/dwc/pci-layerscape.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: 2019年8月23日 11:40
> To: Xiaowei Bao ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; lorenzo.pieral...@arm.co
> ; a...@arndb.de; gre...@linuxfoundation.org;
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: 2019年8月22日 19:44
> To: Xiaowei Bao ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; lorenzo.pieral...@arm.co; a...@arndb.de;
> gre...@linuxfoundation.org
Add LS1088a in pci_device_id table so that pci-epf-test can be used
for testing PCIe EP in LS1088a.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
drivers/misc/pci_endpoint_test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc
Add PCIe EP mode support for ls1088a and ls2088a, there are some
difference between LS1 and LS2 platform, so refactor the code of
the EP driver.
Signed-off-by: Xiaowei Bao
---
v2:
- New mechanism for layerscape EP driver.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 76
Add multiple PFs support for DWC, different PF have different config space
we use pf-offset property which get from the DTS to access the different pF
config space.
Signed-off-by: Xiaowei Bao
---
v2:
- Remove duplicate redundant code.
- Reimplement the PF config space access way.
drivers/pci
Add compatible strings for ls1088a and ls2088a.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
b
Add PCIe EP node for ls1088a to support EP mode.
Signed-off-by: Xiaowei Bao
---
v2:
- Remove the pf-offset proparty.
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 ++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
b
The layerscape platform use the doorbell way to trigger MSIX
interrupt in EP mode.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape
Add the doorbell mode of MSI-X in EP mode.
Signed-off-by: Xiaowei Bao
---
v2:
- Remove the macro of no used.
drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++
drivers/pci/controller/dwc/pcie-designware.h| 12
2 files changed, 26 insertions(+)
diff --git
The different PCIe controller in one board may be have different
capability of MSI or MSIX, so change the way of getting the MSI
capability, make it more flexible.
Signed-off-by: Xiaowei Bao
---
v2:
- Remove the repeated assignment code.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 26
Move the function of getting MSI capability to the front of init
function, because the init function of the EP platform driver will use
the return value by the function of getting MSI capability.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
drivers/pci/controller/dwc/pcie-designware-ep.c
Fix some format issue of the code in EP driver.
Signed-off-by: Xiaowei Bao
---
v2:
- No change.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
b/drivers/pci/controller/dwc
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月16日 20:35
> To: Xiaowei Bao
> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
> mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; kis...@ti.com; lorenzo.pieral...@arm.com;
> a...@arndb.de; gr
> -Original Message-
> From: Kishon Vijay Abraham I
> Sent: 2019年8月16日 18:50
> To: Xiaowei Bao ; Andrew Murray
>
> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
> bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; L
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月16日 18:26
> To: Xiaowei Bao
> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
> bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> l
> -Original Message-
> From: Andrew Murray
> Sent: 2019年8月16日 18:20
> To: Xiaowei Bao
> Cc: jingooh...@gmail.com; gustavo.pimen...@synopsys.com;
> bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ; kis...@ti.com;
> l
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