[PATCH 0/3] irqchip: meson-gpio: add support for Meson-AXG SoCs

This series try to add GPIO interrupt controller support for Meson-AXG SoCs. The first patch is a trivial typo fix, I can fold the first two patches together if necessary. Yixun Lan (3): dt-bindings: interrupt-controller: fix the double quotes dt-bindings: interrupt-controller: New

[PATCH 0/3] irqchip: meson-gpio: add support for Meson-AXG SoCs

This series try to add GPIO interrupt controller support for Meson-AXG SoCs. The first patch is a trivial typo fix, I can fold the first two patches together if necessary. Yixun Lan (3): dt-bindings: interrupt-controller: fix the double quotes dt-bindings: interrupt-controller: New

[PATCH v2] ARM64: dts: meson-axg: enable the eMMC controller

Nan Li <nan...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- Hi Kevin Please note this patch actually depend on the eMMC driver here [0]. Still a few problem to solve, to improve the tuning phase driver to make the clock running at 200MHz, and to further supp

[PATCH v2] ARM64: dts: meson-axg: enable the eMMC controller

From: Nan Li The IP of eMMC controller in AXG is similiar to Meson-GX series. Here we add the initial support of the HS200 mode with clock running at 166MHz (to be safe), since we found some eMMC chip fail to run at 200MHz due to tunning phase error. Signed-off-by: Nan Li Signed-off-by: Yixun

[PATCH v4 5/7] clk: meson-axg: Add AO Clock and Reset controller driver

From: Qiufang Dai <qiufang@amlogic.com> Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson-AXG SoC. Signed-off-by: Qiufang Dai <qiufang@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/Makefile|

[PATCH v4 6/7] clk: meson: drop CLK_SET_RATE_PARENT flag

The clk81 is not expected to be changed, so drop this flag. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/gxbb-aoclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 59db8e

[PATCH v4 5/7] clk: meson-axg: Add AO Clock and Reset controller driver

From: Qiufang Dai Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson-AXG SoC. Signed-off-by: Qiufang Dai Signed-off-by: Yixun Lan --- drivers/clk/meson/Makefile| 2 +- drivers/clk/meson/axg-aoclk.c | 164

[PATCH v4 6/7] clk: meson: drop CLK_SET_RATE_PARENT flag

The clk81 is not expected to be changed, so drop this flag. Signed-off-by: Yixun Lan --- drivers/clk/meson/gxbb-aoclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 59db8e92f8cf..0a2641d6fd33 100644

[PATCH v4 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag

Rely on drivers to request the clock explicitly. Previous the kernel will leave the clock on while bootloader adready initilized the clock, this wasn't optimal way, so fix it here. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/axg-aoclk.c | 1 - drivers/clk/meso

[PATCH v4 7/7] clk: meson: drop CLK_IGNORE_UNUSED flag

Rely on drivers to request the clock explicitly. Previous the kernel will leave the clock on while bootloader adready initilized the clock, this wasn't optimal way, so fix it here. Signed-off-by: Yixun Lan --- drivers/clk/meson/axg-aoclk.c | 1 - drivers/clk/meson/gxbb-aoclk.c | 1 - 2 files

[PATCH v4 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

/20180328025050.221585-1-yixun@amlogic.com Qiufang Dai (1): clk: meson-axg: Add AO Clock and Reset controller driver Yixun Lan (6): clk: meson: aoclk: refactor common code into dedicated file clk: meson: migrate to devm_of_clk_add_hw_provider API dt-bindings: clock: axg-aoclkc: New

[PATCH v4 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

/20180328025050.221585-1-yixun@amlogic.com Qiufang Dai (1): clk: meson-axg: Add AO Clock and Reset controller driver Yixun Lan (6): clk: meson: aoclk: refactor common code into dedicated file clk: meson: migrate to devm_of_clk_add_hw_provider API dt-bindings: clock: axg-aoclkc: New

[PATCH v4 2/7] clk: meson: migrate to devm_of_clk_add_hw_provider API

There is a protential memory leak, as of_clk_del_provider is never called if of_clk_add_hw_provider has been executed. Fix this by using devm variant API. Suggested-by: Stephen Boyd <sb...@kernel.org> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/meson-aoclk

[PATCH v4 2/7] clk: meson: migrate to devm_of_clk_add_hw_provider API

There is a protential memory leak, as of_clk_del_provider is never called if of_clk_add_hw_provider has been executed. Fix this by using devm variant API. Suggested-by: Stephen Boyd Signed-off-by: Yixun Lan --- drivers/clk/meson/meson-aoclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[PATCH v4 3/7] dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC

Update the dt-binding documentation to support new compatible string for the Amlogic's Meson-AXG SoC. Reviewed-by: Rob Herring <r...@kernel.org> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + 1 file changed,

[PATCH v4 3/7] dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC

Update the dt-binding documentation to support new compatible string for the Amlogic's Meson-AXG SoC. Reviewed-by: Rob Herring Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation

[PATCH v4 1/7] clk: meson: aoclk: refactor common code into dedicated file

We try to refactor the common code into one dedicated file, while preparing to add new Meson-AXG aoclk driver, this would help us to better share the code by all aoclk drivers. Suggested-by: Jerome Brunet <jbru...@baylibre.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> ---

[PATCH v4 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

Add dt-bindings headers for the Meson-AXG's AO clock and reset controller. Reviewed-by: Rob Herring <r...@kernel.org> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- include/dt-bindings/clock/axg-aoclkc.h | 26 ++ include/dt-bindings/reset/axg-a

[PATCH v4 1/7] clk: meson: aoclk: refactor common code into dedicated file

We try to refactor the common code into one dedicated file, while preparing to add new Meson-AXG aoclk driver, this would help us to better share the code by all aoclk drivers. Suggested-by: Jerome Brunet Signed-off-by: Yixun Lan --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson

[PATCH v4 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

Add dt-bindings headers for the Meson-AXG's AO clock and reset controller. Reviewed-by: Rob Herring Signed-off-by: Yixun Lan --- include/dt-bindings/clock/axg-aoclkc.h | 26 ++ include/dt-bindings/reset/axg-aoclkc.h | 20 2 files changed, 46

Re: [PATCH v3 1/6] clk: meson: aoclk: refactor common code into dedicated file

HI Stephen thanks for the review On 04/07/18 02:39, Stephen Boyd wrote: > Quoting Yixun Lan (2018-03-27 19:50:45) >> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c >> index 9ec23ae9a219..5a922639a264 100644 >> --- a/drivers/clk/meson/gxbb-aoc

Re: [PATCH v3 1/6] clk: meson: aoclk: refactor common code into dedicated file

HI Stephen thanks for the review On 04/07/18 02:39, Stephen Boyd wrote: > Quoting Yixun Lan (2018-03-27 19:50:45) >> diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c >> index 9ec23ae9a219..5a922639a264 100644 >> --- a/drivers/clk/meson/gxbb-aoc

Re: [PATCH] ARM64: dts: meson-axg: enable the eMMC controller

rong git tree, please drop us a note to > help improve the system] > > url: > https://github.com/0day-ci/linux/commits/Yixun-Lan/ARM64-dts-meson-axg-enable-the-eMMC-controller/20180403-224314 > config: arm64-allyesconfig (attached as .config) > compiler: aarch64-linux-gnu-

Re: [PATCH] ARM64: dts: meson-axg: enable the eMMC controller

rong git tree, please drop us a note to > help improve the system] > > url: > https://github.com/0day-ci/linux/commits/Yixun-Lan/ARM64-dts-meson-axg-enable-the-eMMC-controller/20180403-224314 > config: arm64-allyesconfig (attached as .config) > compiler: aarch64-linux-gnu-

[PATCH] ARM64: dts: meson-axg: enable the eMMC controller

Nan Li <nan...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- Hi Kevin Please note this patch actually depend on the eMMC driver here [0]. Still a few problem to solve, to improve the tuning phase driver to make the clock running at 200MHz, and to further supp

[PATCH] ARM64: dts: meson-axg: enable the eMMC controller

From: Nan Li The IP of eMMC controller in AXG is similiar to Meson-GX series. Here we add the initial support of the HS200 mode with clock running at 166MHz (to be safe), since we found some eMMC chip fail to run at 200MHz due to tunning phase error. Signed-off-by: Nan Li Signed-off-by: Yixun

[PATCH 1/3] mmc: dt-bindings: update bindings doc to support Meson-AXG SoC

From: Nan Li <nan...@amlogic.com> Update the documentation to list support for Meson-AXG SoC explicitly. The new binding string is necessary since this SoC introduce a few IP difference comparing to previous old generation. Signed-off-by: Nan Li <nan...@amlogic.com> Signed-off-b

[PATCH 1/3] mmc: dt-bindings: update bindings doc to support Meson-AXG SoC

From: Nan Li Update the documentation to list support for Meson-AXG SoC explicitly. The new binding string is necessary since this SoC introduce a few IP difference comparing to previous old generation. Signed-off-by: Nan Li Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/mmc

[PATCH 0/3] mmc: meson-axg: initial support for AXG SoC platform

The patches series try to enable basic eMMC support in the Meson-AXG platfrom. Currently HS200 mode is tested with clock running at 166MHz, since not all boards are stable to running 200MHz (due to tuning phase error), we will further improve the tuning phase driver in the future, but in

[PATCH 0/3] mmc: meson-axg: initial support for AXG SoC platform

The patches series try to enable basic eMMC support in the Meson-AXG platfrom. Currently HS200 mode is tested with clock running at 166MHz, since not all boards are stable to running 200MHz (due to tuning phase error), we will further improve the tuning phase driver in the future, but in

[PATCH 3/3] mmc: meson: update doc to support Meson-AXG platform

From: Nan Li <nan...@amlogic.com> Explicitly update the docomentation to support the Meson-AXG platform. Signed-off-by: Nan Li <nan...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/mmc/host/Kconfig| 4 ++-- drivers/mmc/host/meson-gx-mmc

[PATCH 3/3] mmc: meson: update doc to support Meson-AXG platform

From: Nan Li Explicitly update the docomentation to support the Meson-AXG platform. Signed-off-by: Nan Li Signed-off-by: Yixun Lan --- drivers/mmc/host/Kconfig| 4 ++-- drivers/mmc/host/meson-gx-mmc.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc

[PATCH 2/3] mmc: meson-axg: add support for the Meson-AXG platform

From: Nan Li <nan...@amlogic.com> Introduce the compatible data to cover the register offset & mask change of the eMMC controller in Amlogic's Meson-AXG SoC. Signed-off-by: Nan Li <nan...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/mmc/ho

[PATCH 2/3] mmc: meson-axg: add support for the Meson-AXG platform

From: Nan Li Introduce the compatible data to cover the register offset & mask change of the eMMC controller in Amlogic's Meson-AXG SoC. Signed-off-by: Nan Li Signed-off-by: Yixun Lan --- drivers/mmc/host/meson-gx-mmc.c | 61 ++--- 1 file changed

Re: [PATCH 1/3] iio: adc: meson-saradc: squash and share the common adc platform data

On 03/30/18 17:48, Jonathan Cameron wrote: > On Mon, 26 Mar 2018 16:46:27 +0800 > Yixun Lan <yixun@amlogic.com> wrote: > >> Extract and promote common adc platform data into a new structure, >> to make it better share the info between several SoCs, >> this wi

Re: [PATCH 1/3] iio: adc: meson-saradc: squash and share the common adc platform data

On 03/30/18 17:48, Jonathan Cameron wrote: > On Mon, 26 Mar 2018 16:46:27 +0800 > Yixun Lan wrote: > >> Extract and promote common adc platform data into a new structure, >> to make it better share the info between several SoCs, >> this will avoid duplicating the code

[PATCH v3 0/3] ARM64: dts: meson-axg: add AO clock driver

://lkml.kernel.org/r/20180326081809.49493-4-yixun@amlogic.com [2] https://lkml.kernel.org/r/20180328025050.221585-1-yixun@amlogic.com Qiufang Dai (1): arm64: dts: meson-axg: add AO clock driver DT info Yixun Lan (2): ARM64: dts: meson-axg: add an 32K alt aoclk ARM64: dts: meson: fix clock

[PATCH v3 0/3] ARM64: dts: meson-axg: add AO clock driver

://lkml.kernel.org/r/20180326081809.49493-4-yixun@amlogic.com [2] https://lkml.kernel.org/r/20180328025050.221585-1-yixun@amlogic.com Qiufang Dai (1): arm64: dts: meson-axg: add AO clock driver DT info Yixun Lan (2): ARM64: dts: meson-axg: add an 32K alt aoclk ARM64: dts: meson: fix clock

[PATCH v3 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO

lag in another patch, but before doing that, we need to fix the clock in the DTS file. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi |

[PATCH v3 2/3] ARM64: dts: meson-axg: add an 32K alt aoclk

The ao_clk81 in AO domain have two clock source, one from a 32K alt crystal we name it as ao_alt_clk, another is the clk81 signal from EE domain. Acked-by: Jerome Brunet <jbru...@baylibre.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-

[PATCH v3 1/3] arm64: dts: meson-axg: add AO clock driver DT info

From: Qiufang Dai <qiufang@amlogic.com> This add the AO (Always-On part) clock DT info for Meson-AXG SoC Signed-off-by: Qiufang Dai <qiufang@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 12

[PATCH v3 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO

lag in another patch, but before doing that, we need to fix the clock in the DTS file. Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4 ++-- 3 files changed

[PATCH v3 2/3] ARM64: dts: meson-axg: add an 32K alt aoclk

The ao_clk81 in AO domain have two clock source, one from a 32K alt crystal we name it as ao_alt_clk, another is the clk81 signal from EE domain. Acked-by: Jerome Brunet Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++ 1 file changed, 7 insertions(+) diff

[PATCH v3 1/3] arm64: dts: meson-axg: add AO clock driver DT info

From: Qiufang Dai This add the AO (Always-On part) clock DT info for Meson-AXG SoC Signed-off-by: Qiufang Dai Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi

[PATCH v3 5/6] clk: meson: drop CLK_SET_RATE_PARENT flag

The clk81 is not expected to be changed, so drop this flag. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/gxbb-aoclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 5a9226

[PATCH v3 5/6] clk: meson: drop CLK_SET_RATE_PARENT flag

The clk81 is not expected to be changed, so drop this flag. Signed-off-by: Yixun Lan --- drivers/clk/meson/gxbb-aoclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 5a922639a264..89b048aad239 100644

[PATCH v3 6/6] clk: meson: drop CLK_IGNORE_UNUSED flag

Rely on drivers to request the clock explicitly. Previous the kernel will leave the clock on while bootloader adready initilized the clock, this wasn't optimal way, so fix it here. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/axg-aoclk.c | 1 - drivers/clk/meso

[PATCH v3 6/6] clk: meson: drop CLK_IGNORE_UNUSED flag

Rely on drivers to request the clock explicitly. Previous the kernel will leave the clock on while bootloader adready initilized the clock, this wasn't optimal way, so fix it here. Signed-off-by: Yixun Lan --- drivers/clk/meson/axg-aoclk.c | 1 - drivers/clk/meson/gxbb-aoclk.c | 1 - 2 files

[PATCH v3 3/6] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

Add dt-bindings headers for the Meson-AXG's AO clock and reset controller. Reviewed-by: Rob Herring <r...@kernel.org> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- include/dt-bindings/clock/axg-aoclkc.h | 26 ++ include/dt-bindings/reset/axg-a

[PATCH v3 3/6] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

Add dt-bindings headers for the Meson-AXG's AO clock and reset controller. Reviewed-by: Rob Herring Signed-off-by: Yixun Lan --- include/dt-bindings/clock/axg-aoclkc.h | 26 ++ include/dt-bindings/reset/axg-aoclkc.h | 20 2 files changed, 46

[PATCH v3 2/6] dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC

Update the dt-binding documentation to support new compatible string for the Amlogic's Meson-AXG SoC. Reviewed-by: Rob Herring <r...@kernel.org> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + 1 file changed,

[PATCH v3 0/6] clk: meson-axg: Add AO Cloclk and Reset driver

-yixun@amlogic.com [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun@amlogic.com Qiufang Dai (1): clk: meson-axg: Add AO Clock and Reset controller driver Yixun Lan (5): clk: meson: aoclk: refactor common code into dedicated file dt-bindings: clock: axg-aoclkc: New binding

[PATCH v3 2/6] dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC

Update the dt-binding documentation to support new compatible string for the Amlogic's Meson-AXG SoC. Reviewed-by: Rob Herring Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation

[PATCH v3 0/6] clk: meson-axg: Add AO Cloclk and Reset driver

-yixun@amlogic.com [3] https://lkml.kernel.org/r/20180326081809.49493-4-yixun@amlogic.com Qiufang Dai (1): clk: meson-axg: Add AO Clock and Reset controller driver Yixun Lan (5): clk: meson: aoclk: refactor common code into dedicated file dt-bindings: clock: axg-aoclkc: New binding

[PATCH v3 4/6] clk: meson-axg: Add AO Clock and Reset controller driver

From: Qiufang Dai <qiufang@amlogic.com> Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson-AXG SoC. Signed-off-by: Qiufang Dai <qiufang@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/Makefile|

[PATCH v3 4/6] clk: meson-axg: Add AO Clock and Reset controller driver

From: Qiufang Dai Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson-AXG SoC. Signed-off-by: Qiufang Dai Signed-off-by: Yixun Lan --- drivers/clk/meson/Makefile| 2 +- drivers/clk/meson/axg-aoclk.c | 164

[PATCH v3 1/6] clk: meson: aoclk: refactor common code into dedicated file

We try to refactor the common code into one dedicated file, while preparing to add new Meson-AXG aoclk driver, this would help us to better share the code by all aoclk drivers. Suggested-by: Jerome Brunet <jbru...@baylibre.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> ---

[PATCH v3 1/6] clk: meson: aoclk: refactor common code into dedicated file

We try to refactor the common code into one dedicated file, while preparing to add new Meson-AXG aoclk driver, this would help us to better share the code by all aoclk drivers. Suggested-by: Jerome Brunet Signed-off-by: Yixun Lan --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson

Re: [PATCH 0/3] clk: meson: drop unnecessary AO clock flags

HI Jerome On 03/27/2018 05:21 PM, Jerome Brunet wrote: > On Mon, 2018-03-26 at 16:18 +0800, Yixun Lan wrote: >> This first two patches will drop unnecessary flags for >> the AO clock driver. >> The third DTS patch is a follow-up fix for the second patch, >> and I'v

Re: [PATCH 0/3] clk: meson: drop unnecessary AO clock flags

HI Jerome On 03/27/2018 05:21 PM, Jerome Brunet wrote: > On Mon, 2018-03-26 at 16:18 +0800, Yixun Lan wrote: >> This first two patches will drop unnecessary flags for >> the AO clock driver. >> The third DTS patch is a follow-up fix for the second patch, >> and I'v

Re: [PATCH 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO

On 03/27/2018 05:20 PM, Jerome Brunet wrote: > On Mon, 2018-03-26 at 16:18 +0800, Yixun Lan wrote: >> From the hardware perspective, the clk81 is the parent of >> the UART_AO clocks. So it make more sense to mark >> the CLKID_AO_UART1/2 as the pclk. >> >> Previ

Re: [PATCH 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO

On 03/27/2018 05:20 PM, Jerome Brunet wrote: > On Mon, 2018-03-26 at 16:18 +0800, Yixun Lan wrote: >> From the hardware perspective, the clk81 is the parent of >> the UART_AO clocks. So it make more sense to mark >> the CLKID_AO_UART1/2 as the pclk. >> >> Previ

[PATCH] ARM64: dts: meson-axg: add saradc support

From: Xingyu Chen <xingyu.c...@amlogic.com> Add the DT info for SAR ADC of the Amlogic's Meson-AXG SoC. Signed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- Hi Kevin: Please note, the saradc driver in Meson-AXG platfr

[PATCH] ARM64: dts: meson-axg: add saradc support

From: Xingyu Chen Add the DT info for SAR ADC of the Amlogic's Meson-AXG SoC. Signed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- Hi Kevin: Please note, the saradc driver in Meson-AXG platfrom actually depend on the AO clock driver [0] & saradc patch itself [1]. And I've reb

[PATCH 1/3] iio: adc: meson-saradc: squash and share the common adc platform data

Extract and promote common adc platform data into a new structure, to make it better share the info between several SoCs, this will avoid duplicating the code all over the place, Save a few memory and make the code more maintainable. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- d

[PATCH 1/3] iio: adc: meson-saradc: squash and share the common adc platform data

Extract and promote common adc platform data into a new structure, to make it better share the info between several SoCs, this will avoid duplicating the code all over the place, Save a few memory and make the code more maintainable. Signed-off-by: Yixun Lan --- drivers/iio/adc/meson_saradc.c

[PATCH 3/3] iio: adc: meson-axg: add saradc driver

From: Xingyu Chen Add the SAR ADC driver for the Amlogic Meson-AXG SoC. Signed-off-by: Xingyu Chen --- drivers/iio/adc/meson_saradc.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/iio/adc/meson_saradc.c

[PATCH 3/3] iio: adc: meson-axg: add saradc driver

From: Xingyu Chen Add the SAR ADC driver for the Amlogic Meson-AXG SoC. Signed-off-by: Xingyu Chen --- drivers/iio/adc/meson_saradc.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 799ed929ab99..a5d481a2b4ef

[PATCH 2/3] dt-bindings: iio: adc: document the Meson AXG support

From: Xingyu Chen Update the documentation to expicitly support the Meson-AXG SoC. Signed-off-by: Xingyu Chen --- Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH 2/3] dt-bindings: iio: adc: document the Meson AXG support

From: Xingyu Chen Update the documentation to expicitly support the Meson-AXG SoC. Signed-off-by: Xingyu Chen --- Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH 0/3] iio: adc: meson-axg: add saradc driver support

/20180323143816.200573-1-yixun@amlogic.com Xingyu Chen (2): dt-bindings: iio: adc: document the Meson AXG support iio: adc: meson-axg: add saradc driver Yixun Lan (1): iio: adc: meson-saradc: squash and share the common adc platform data .../bindings/iio/adc/amlogic,meson-saradc.txt | 1 + drivers

[PATCH 0/3] iio: adc: meson-axg: add saradc driver support

/20180323143816.200573-1-yixun@amlogic.com Xingyu Chen (2): dt-bindings: iio: adc: document the Meson AXG support iio: adc: meson-axg: add saradc driver Yixun Lan (1): iio: adc: meson-saradc: squash and share the common adc platform data .../bindings/iio/adc/amlogic,meson-saradc.txt | 1 + drivers

[PATCH 1/3] clk: meson: drop CLK_SET_RATE_PARENT flag

The clk81 is not expected to be changed, so drop this flag. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/gxbb-aoclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 0f089c

[PATCH 1/3] clk: meson: drop CLK_SET_RATE_PARENT flag

The clk81 is not expected to be changed, so drop this flag. Signed-off-by: Yixun Lan --- drivers/clk/meson/gxbb-aoclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 0f089cbce594..e7bc04d3e24f 100644

[PATCH 2/3] clk: meson: drop CLK_IGNORE_UNUSED flag

Rely on drivers to request the clock explicitly. Previous the kernel will leave the clock on while bootloader adready initilized the clock, this wasn't optimal way, so fix it here. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/axg-aoclk.c | 1 - drivers/clk/meso

[PATCH 2/3] clk: meson: drop CLK_IGNORE_UNUSED flag

Rely on drivers to request the clock explicitly. Previous the kernel will leave the clock on while bootloader adready initilized the clock, this wasn't optimal way, so fix it here. Signed-off-by: Yixun Lan --- drivers/clk/meson/axg-aoclk.c | 1 - drivers/clk/meson/gxbb-aoclk.c | 1 - 2 files

[PATCH 0/3] clk: meson: drop unnecessary AO clock flags

/20180323143816.200573-1-yixun@amlogic.com Yixun Lan (3): clk: meson: drop CLK_SET_RATE_PARENT flag clk: meson: drop CLK_IGNORE_UNUSED flag ARM64: dts: meson: fix clock source of the pclk for UART_AO arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4

[PATCH 0/3] clk: meson: drop unnecessary AO clock flags

/20180323143816.200573-1-yixun@amlogic.com Yixun Lan (3): clk: meson: drop CLK_SET_RATE_PARENT flag clk: meson: drop CLK_IGNORE_UNUSED flag ARM64: dts: meson: fix clock source of the pclk for UART_AO arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4

[PATCH 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO

off-by: Yixun Lan <yixun@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/amlo

[PATCH 3/3] ARM64: dts: meson: fix clock source of the pclk for UART_AO

off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/ar

[PATCH v2 6/7] arm64: dts: meson-axg: add AO clock driver DT info

From: Qiufang Dai <qiufang@amlogic.com> This add the AO (Always-On part) clock DT info for Meson-AXG SoC Signed-off-by: Qiufang Dai <qiufang@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 12

[PATCH v2 7/7] ARM64: dts: meson-axg: add an 32K alt aoclk

The ao_clk81 in AO domain have two clock source, one from a 32K alt crystal we name it as ao_alt_clk, another is the clk81 signal from EE domain. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++ 1 file changed, 7 insertions(+)

[PATCH v2 6/7] arm64: dts: meson-axg: add AO clock driver DT info

From: Qiufang Dai This add the AO (Always-On part) clock DT info for Meson-AXG SoC Signed-off-by: Qiufang Dai Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi

[PATCH v2 7/7] ARM64: dts: meson-axg: add an 32K alt aoclk

The ao_clk81 in AO domain have two clock source, one from a 32K alt crystal we name it as ao_alt_clk, another is the clk81 signal from EE domain. Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot

[PATCH v2 1/7] clk: meson: drop meson_aoclk_gate_regmap_ops

let's remove the unused meson_aoclk_gate_regmap_ops Fixes: 1f932d99710d ("clk: meson: remove superseded aoclk_gate_regmap") Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/gxbb-aoclk.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/meso

[PATCH v2 5/7] clk: meson-axg: Add AO Clock and Reset controller driver

From: Qiufang Dai <qiufang@amlogic.com> Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson-AXG SoC. Signed-off-by: Qiufang Dai <qiufang@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/Makefile|

[PATCH v2 1/7] clk: meson: drop meson_aoclk_gate_regmap_ops

let's remove the unused meson_aoclk_gate_regmap_ops Fixes: 1f932d99710d ("clk: meson: remove superseded aoclk_gate_regmap") Signed-off-by: Yixun Lan --- drivers/clk/meson/gxbb-aoclk.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/

[PATCH v2 5/7] clk: meson-axg: Add AO Clock and Reset controller driver

From: Qiufang Dai Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson-AXG SoC. Signed-off-by: Qiufang Dai Signed-off-by: Yixun Lan --- drivers/clk/meson/Makefile| 2 +- drivers/clk/meson/axg-aoclk.c | 162

[PATCH v2 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

://lkml.kernel.org/r/<20180209070026.193879-1-yixun@amlogic.com> Qiufang Dai (2): clk: meson-axg: Add AO Clock and Reset controller driver arm64: dts: meson-axg: add AO clock driver DT info Yixun Lan (5): clk: meson: drop meson_aoclk_gate_regmap_ops clk: meson: aoclk: refactor commo

[PATCH v2 0/7] clk: meson-axg: Add AO Cloclk and Reset driver

://lkml.kernel.org/r/<20180209070026.193879-1-yixun@amlogic.com> Qiufang Dai (2): clk: meson-axg: Add AO Clock and Reset controller driver arm64: dts: meson-axg: add AO clock driver DT info Yixun Lan (5): clk: meson: drop meson_aoclk_gate_regmap_ops clk: meson: aoclk: refactor commo

[PATCH v2 2/7] clk: meson: aoclk: refactor common code into dedicated file

We try to refactor the common code into one dedicated file, while preparing to add new Meson-AXG aoclk driver, this would help us to better share the code by all aoclk drivers. Suggested-by: Jerome Brunet <jbru...@baylibre.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> ---

[PATCH v2 2/7] clk: meson: aoclk: refactor common code into dedicated file

We try to refactor the common code into one dedicated file, while preparing to add new Meson-AXG aoclk driver, this would help us to better share the code by all aoclk drivers. Suggested-by: Jerome Brunet Signed-off-by: Yixun Lan --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson

[PATCH v2 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

Add dt-bindings headers for the Meson-AXG's AO clock and reset controller. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- include/dt-bindings/clock/axg-aoclkc.h | 26 ++ include/dt-bindings/reset/axg-aoclkc.h | 20 2 files changed, 46 inse

[PATCH v2 4/7] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

Add dt-bindings headers for the Meson-AXG's AO clock and reset controller. Signed-off-by: Yixun Lan --- include/dt-bindings/clock/axg-aoclkc.h | 26 ++ include/dt-bindings/reset/axg-aoclkc.h | 20 2 files changed, 46 insertions(+) create mode 100644

[PATCH v2 3/7] dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC

Update the dt-binding documentation to support new compatible string for the Amlogic's Meson-AXG SoC. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devi

[PATCH v2 3/7] dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC

Update the dt-binding documentation to support new compatible string for the Amlogic's Meson-AXG SoC. Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/amlogic

Re: [PATCH 1/2] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

Hi Philippe On 02/09/2018 07:07 PM, Philippe Ombredanne wrote: > On Fri, Feb 9, 2018 at 8:00 AM, Yixun Lan <yixun@amlogic.com> wrote: >> Add dt-bindings headers for the Meson-AXG's AO clock and >> reset controller. >> >> CC: <devicet...@vger.kernel.org

Re: [PATCH 1/2] dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings

Hi Philippe On 02/09/2018 07:07 PM, Philippe Ombredanne wrote: > On Fri, Feb 9, 2018 at 8:00 AM, Yixun Lan wrote: >> Add dt-bindings headers for the Meson-AXG's AO clock and >> reset controller. >> >> CC: >> Signed-off-by: Yixun Lan >> --- >>

Re: [PATCH 2/2] clk: meson-axg: Add AO Clock and Reset controller driver

Hi Jerome: On 02/12/2018 11:32 PM, Jerome Brunet wrote: > On Fri, 2018-02-09 at 15:00 +0800, Yixun Lan wrote: >> Adds a Clock and Reset controller driver for the Always-On part >> of the Amlogic Meson-AXG SoC. >> >> Signed-off-by: Qiufang Dai <qiufang@amlogic.co

Re: [PATCH 2/2] clk: meson-axg: Add AO Clock and Reset controller driver

Hi Jerome: On 02/12/2018 11:32 PM, Jerome Brunet wrote: > On Fri, 2018-02-09 at 15:00 +0800, Yixun Lan wrote: >> Adds a Clock and Reset controller driver for the Always-On part >> of the Amlogic Meson-AXG SoC. >> >> Signed-off-by: Qiufang Dai >> Signed-off-by:

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