Hi Marc,
On 2019/7/26 17:18, Marc Zyngier wrote:
> On Fri, 26 Jul 2019 09:51:45 +0800
> Shaokun Zhang wrote:
>
>> From: Nianyao Tang
>>
>> In its_vpe_init, when its_alloc_vpe_table fails, we should free
>> vpt_page allocated just before, instead of vpe->vpt_page.
>> Let's fix it.
>>
>> Cc: Thom
Hi Eric,
Thanks your quick reply.
On 2019/7/24 16:56, Eric Dumazet wrote:
>
>
> On 7/24/19 10:38 AM, Zhangshaokun wrote:
>> Hi,
>>
>> I've observed an significant performance regression with the following
>> commit-id
>> ("net: get rid o
Hi,
I've observed an significant performance regression with the following
commit-id
("net: get rid of an signed integer overflow in ip_idents_reserve()").
Here are my test scenes:
Server
Cmd: iperf3 -s xxx.xxx..xxx -p 1 -i 0 -A 0
Kenel: 4.19.34
Server number: 32
Port: 1 – 1
Hi Will,
On 2019/7/2 20:03, Will Deacon wrote:
> [+Joerg]
>
> On Tue, Jul 02, 2019 at 06:40:45PM +0800, Zhangshaokun wrote:
>> +Cc: Will Deacon
>>
>> There is a compiler failure on arm64 platform, as follow:
>> In file included from ./include/linux/list.h:9:0,
&
+Cc: Will Deacon
There is a compiler failure on arm64 platform, as follow:
In file included from ./include/linux/list.h:9:0,
from ./include/linux/kobject.h:19,
from ./include/linux/of.h:17,
from ./include/linux/irqdomain.h:35,
fro
Hi Catalin,
On 2019/6/17 18:45, Catalin Marinas wrote:
> On Sat, Jun 15, 2019 at 10:44:33AM +0800, Zhangshaokun wrote:
>> On 2019/6/14 21:11, Masayoshi Mizuma wrote:
>>> diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
>>> index 6eaf1c
Hi Masayoshi,
A few trivial comments inline.
On 2019/6/14 21:11, Masayoshi Mizuma wrote:
> From: Masayoshi Mizuma
>
> If the cache line size is greater than ARCH_DMA_MINALIGN (128),
> the warning shows and it's tainted as TAINT_CPU_OUT_OF_SPEC.
>
> However, it's not good because as discussed i
Hi Alexander,
A gentle ping.
On 2019/5/20 19:32, Shaokun Zhang wrote:
> drivers/hwtracing/intel_th/msu.c: In function ‘msc_buffer_win_alloc’:
> drivers/hwtracing/intel_th/msu.c:783:21: warning: unused variable ‘i’
> [-Wunused-variable]
> int ret = -ENOMEM, i;
> ^
> drivers
Hi Greg,
On 2019/5/27 14:08, Greg KH wrote:
> On Mon, May 27, 2019 at 10:06:08AM +0800, Shaokun Zhang wrote:
>> cache_line_size is derived from CTR_EL0.CWG field and is called mostly
>> for I/O device drivers. For HiSilicon certain plantform, like the
>> Kunpeng920 server SoC, cache line sizes are
Hi Alex,
On 2019/5/20 17:39, Alexander Shishkin wrote:
> Shaokun Zhang writes:
>
>> drivers/hwtracing/intel_th/msu.c: In function ‘msc_buffer_win_alloc’:
>> drivers/hwtracing/intel_th/msu.c:783:21: warning: unused variable ‘i’
>> [-Wunused-variable]
>> int ret = -ENOMEM, i;
>>
please ignore this patch, I will update it and resend it.
On 2019/5/20 11:23, Shaokun Zhang wrote:
> Fix this compiler warning on arm64 platform.
>
> Cc: Alexander Shishkin
> Cc: Greg Kroah-Hartman
> Signed-off-by: Shaokun Zhang
> ---
> drivers/hwtracing/intel_th/msu.c | 8 +++-
> 1 file
A little confused,
https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?h=x86/cleanups&id=691b9ab6c9676e5868a4787be9041dd990005311
On 2019/3/7 6:33, tip-bot for Qian Cai wrote:
> Commit-ID: 3609e31bc8dc03b701390f79c74fc7fe92b95039
> Gitweb:
> https://git.kernel.org/tip/3609e31
Hi Andrew,
On 2019/3/4 22:57, Andrew Lunn wrote:
> On Mon, Mar 04, 2019 at 10:16:08PM +0800, Zhangshaokun wrote:
>> Hi Andrew,
>>
>> On 2019/3/4 21:26, Andrew Lunn wrote:
>>> On Mon, Mar 04, 2019 at 08:43:01PM +0800, Shaokun Zhang wrote:
>>>> When CONFIG
Hi Andrew,
On 2019/3/4 21:26, Andrew Lunn wrote:
> On Mon, Mar 04, 2019 at 08:43:01PM +0800, Shaokun Zhang wrote:
>> When CONFIG_NET_DSA_LEGACY is n, there is a GCC bulid warning:
>> drivers/net/dsa/mv88e6xxx/chip.c:4623:13: warning:
>> ‘mv88e6xxx_ports_cmode_init’ defined but not used [-Wunused-
Hi Geert,
On 2019/2/21 16:03, Geert Uytterhoeven wrote:
> Hi Shaokun,
>
> On Thu, Feb 21, 2019 at 1:45 AM Zhangshaokun
> wrote:
>> On 2019/2/20 18:05, Ard Biesheuvel wrote:
>>> On Wed, 20 Feb 2019 at 10:58, Jarkko Sakkinen
>>> wrote:
>>>>
>&
Hi Ard,
On 2019/2/20 18:05, Ard Biesheuvel wrote:
> On Wed, 20 Feb 2019 at 10:58, Jarkko Sakkinen
> wrote:
>>
>> On Wed, Feb 20, 2019 at 11:52:52AM +0200, Jarkko Sakkinen wrote:
>>> On Wed, Feb 20, 2019 at 05:11:15PM +0800, Zhangshaokun wrote:
>>>> There
There is a compiler failure on arm64 platform, as follow:
AS arch/arm64/kvm/hyp.o
CC kernel/trace/ring_buffer.o
In file included from security/integrity/ima/ima_fs.c:30:0:
security/integrity/ima/ima.h:176:7: error: redeclaration of enumerator ‘NONE’
hook(NONE) \
^
security
Hi,
On 2017/11/17 11:53, Stephen Rothwell wrote:
> Hi all,
>
> On Fri, 17 Nov 2017 09:44:39 +1100 Stephen Rothwell
> wrote:
>>
>> On Mon, 13 Nov 2017 12:43:08 +0100 Arnd Bergmann wrote:
>>>
>>> On Mon, Nov 13, 2017 at 9:09 AM, Michal Hocko wrote:
On Mon 13-11-17 16:42:06, Stephen Rothw
Hi Mark/Will,
Thanks.
On 2017/10/19 23:32, Mark Rutland wrote:
> On Thu, Oct 19, 2017 at 04:28:35PM +0100, Will Deacon wrote:
>> On Thu, Oct 19, 2017 at 01:29:18PM +0100, Mark Rutland wrote:
>>> Will, are you happy to queue this?
>>>
>>> There's a minor fixup [1] needed in patch 2, but otherwise
Hi Mark,
Thanks for your further explanation.
On 2017/10/18 21:55, Mark Rutland wrote:
> On Wed, Oct 18, 2017 at 09:33:30PM +0800, Zhangshaokun wrote:
>> On 2017/10/17 23:16, Mark Rutland wrote:
>>> On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote
Hi Mark,
On 2017/10/17 23:21, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:56PM +0800, Shaokun Zhang wrote:
>> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
>> DDRC has own control, counter and interrupt registers and is an separate
>> PMU. For each DDRC PMU, it ha
Hi Mark,
On 2017/10/17 23:18, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
>> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
>> SoC. This patch adds support for HHA PMU driver, Each HHA has own
>> control, counter and interrupt regis
Hi Mark,
On 2017/10/17 23:16, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote:
>> +static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
>> + struct platform_device *pdev)
>> +{
>> +int irq, ret;
>> +
>> +/* Read and init
Hi Mark,
Thanks for your comments.
On 2017/10/17 23:06, Mark Rutland wrote:
> Hi,
>
> Apologies for the delay for this review.
>
> Largely this seems to look OK, but there are a couple of things which
> stick out.
>
> On Tue, Aug 22, 2017 at 04:07:53PM +0800, Shaokun Zhang wrote:
>> +int hisi_
Hi Will,
On 2017/10/12 18:58, Will Deacon wrote:
> On Thu, Oct 12, 2017 at 04:20:06PM +0530, Ganapatrao Kulkarni wrote:
>> Hi Robert,
>>
>> On Thu, Oct 12, 2017 at 4:08 PM, Robert Richter wrote:
>>> On 12.10.17 16:04:15, Ganapatrao Kulkarni wrote:
>>>
tools/perf/arch/arm64/util/Build
Hi All,
Do you have any comments on this patch set?
Thanks,
Shaokun
On 2017/9/21 18:40, Zhangshaokun wrote:
> Hi Mark/Will,
>
> Appreciate any comments from you.
>
> Thanks,
> Shaokun
>
> On 2017/8/22 16:07, Shaokun Zhang wrote:
>> This patchset adds support
Hi Mark/Will,
Appreciate any comments from you.
Thanks,
Shaokun
On 2017/8/22 16:07, Shaokun Zhang wrote:
> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
> includes L3C, Hydra Home Agent (HHA) and DDRC.
>
> Changes in v5:
> * remove unnecessary name/num_events member in his
Hi Robert,
On 2017/8/29 20:47, Robert Richter wrote:
> Shaokun,
>
> On 29.08.17 17:26:00, Zhangshaokun wrote:
>> On 2017/8/24 20:03, Ganapatrao Kulkarni wrote:
>>> This is not a full event list, but a short list of useful events.
>>>
>>> Signed-off-b
Hi Robert,
Got it and thanks your reply.
Shaokun
On 2017/8/29 20:47, Robert Richter wrote:
> Shaokun,
>
> On 29.08.17 17:26:00, Zhangshaokun wrote:
>> On 2017/8/24 20:03, Ganapatrao Kulkarni wrote:
>>> This is not a full event list, but a short list of useful event
Hi Jan,
Some trivial things i noticed, please consider if you are glad.
Thanks,
Shaokun
On 2017/8/29 21:12, Jan Glauber wrote:
> Add support for the PMU counters on Cavium SOC memory controllers.
>
> This patch also adds generic functions to allow supporting more
> devices with PMU counters.
>
Hi Mark/Will,
Do you have any comments on this patch set? Appreciate your comments.
Thanks,
Shaokun
On 2017/8/22 16:07, Shaokun Zhang wrote:
> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
> includes L3C, Hydra Home Agent (HHA) and DDRC.
>
> Changes in v5:
> * remove unnec
Hi Ganapat,
On 2017/8/24 20:03, Ganapatrao Kulkarni wrote:
> This is not a full event list, but a short list of useful events.
>
> Signed-off-by: Ganapatrao Kulkarni
> ---
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 15 ++
> .../arm64/thunderx2/implementation-defined.json| 6
Hi Mark,
On 2017/8/15 21:02, Mark Rutland wrote:
> On Tue, Jul 25, 2017 at 08:10:41PM +0800, Shaokun Zhang wrote:
>> This patch adds support for DDRC PMU driver in HiSilicon SoC chip, Each
>> DDRC has own control, counter and interrupt registers and is an separate
>> PMU. For each DDRC PMU, it has
Hi Mark,
On 2017/8/15 19:05, Mark Rutland wrote:
> On Tue, Jul 25, 2017 at 08:10:40PM +0800, Shaokun Zhang wrote:
>> +/* HHA register definition */
>> +#define HHA_INT_MASK0x0804
>> +#define HHA_INT_STATUS 0x0808
>> +#define HHA_INT_CLEAR 0x080C
>> +#defi
Hi Mark,
On 2017/8/15 18:41, Mark Rutland wrote:
> On Tue, Jul 25, 2017 at 08:10:39PM +0800, Shaokun Zhang wrote:
>> This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each
>> L3C has own control, counter and interrupt registers and is an separate
>> PMU. For each L3C PMU, it has 8-
Hi Mark,
On 2017/8/15 18:16, Mark Rutland wrote:
> Hi,
>
> On Tue, Jul 25, 2017 at 08:10:38PM +0800, Shaokun Zhang wrote:
>> +/* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1 */
>> +void hisi_read_sccl_and_ccl_id(u32 *sccl_id, u32 *ccl_id)
>> +{
>> +u64 mpidr;
>> +
>> +mpidr =
Hi Mark,
Thanks for your comments.
On 2017/8/15 17:50, Mark Rutland wrote:
> Hi,
>
> On Tue, Jul 25, 2017 at 08:10:37PM +0800, Shaokun Zhang wrote:
>> This patch adds documentation for the uncore PMUs on HiSilicon SoC.
>>
>> Reviewed-by: Jonathan Cameron
>> Signed-off-by: Shaokun Zhang
>> Sign
Hi Mark/Will,
Appreciate your comments.
Thanks.
Shaokun
On 2017/7/25 20:10, Shaokun Zhang wrote:
> This patchset adds support for HiSilicon SoC uncore PMUs driver. It
> includes L3C, Hydra Home Agent (HHA) and DDRC.
>
> Changes in v4:
> * remove redundant code and comments
> * reverse the funct
Hi Ganapat
I have tested patch-v4 on Hisilicon's hip08 board for implementation defined
PMU events,
and it works, So
Tested-by: Shaokun Zhang
Thanks.
Shaokun
On 2017/7/20 13:56, Ganapatrao Kulkarni wrote:
> Extending json/jevent framework for parsing arm64 event files.
> Adding jevents for Th
Hi Jonathan
On 2017/7/20 21:49, Jonathan Cameron wrote:
> On Thu, 20 Jul 2017 21:03:19 +0800
> Zhangshaokun wrote:
>
>> Hi Jonathan
>>
>> On 2017/7/19 17:19, Jonathan Cameron wrote:
>>> On Tue, 18 Jul 2017 15:59:55 +0800
>>> Shaokun Zhang wrote:
Hi Jonathan,
On 2017/7/19 17:28, Jonathan Cameron wrote:
> On Tue, 18 Jul 2017 15:59:56 +0800
> Shaokun Zhang wrote:
>
>> This patch adds support for L3C PMU driver in HiSilicon SoC chip, Each
>> L3C has own control, counter and interrupt registers and is an separate
>> PMU. For each L3C PMU, it
Hi Jonathan
On 2017/7/19 17:19, Jonathan Cameron wrote:
> On Tue, 18 Jul 2017 15:59:55 +0800
> Shaokun Zhang wrote:
>
>> This patch adds support HiSilicon SoC uncore PMU driver framework and
>> interfaces.
>>
>> Signed-off-by: Shaokun Zhang
>> Signed-off-by: Anurup M
> A couple of minor thin
Hi Jonathan,
Thanks for your comments firstly.
On 2017/7/19 17:17, Jonathan Cameron wrote:
> On Tue, 18 Jul 2017 15:59:54 +0800
> Shaokun Zhang wrote:
>
>> This patch adds documentation for the uncore PMUs on HiSilicon SoC.
>>
>> Signed-off-by: Shaokun Zhang
>> Signed-off-by: Anurup M
> Hi
Hi,
On 2017/6/28 9:49, kbuild test robot wrote:
> Hi Shaokun,
>
> [auto build test ERROR on next-20170619]
> [also build test ERROR on v4.12-rc7]
> [cannot apply to linus/master linux/master arm64/for-next/core v4.12-rc6
> v4.12-rc5 v4.12-rc4]
> [if your patch is applied to the wrong git tree, p
Hi Mark,
On 2017/6/9 21:26, Mark Rutland wrote:
> On Mon, May 22, 2017 at 08:48:37PM +0800, Shaokun Zhang wrote:
>> 1. Add support to count MN hardware events.
>> 2. Mn events are listed in sysfs at /sys/devices/hisi_mn_2/events/
>>The events can be selected as shown in perf list
>>e.g.: F
Hi Mark,
On 2017/6/9 21:23, Mark Rutland wrote:
> Hi,
>
> On Mon, May 22, 2017 at 08:48:35PM +0800, Shaokun Zhang wrote:
>> +/*
>> + * ARMv8 HiSilicon Hardware counter Index.
>> + */
>> +enum hisi_l3c_pmu_counters {
>> +HISI_IDX_L3C_COUNTER0 = 0x0,
>> +HISI_IDX_L3C_COUNTER_MAX
Hi Mark,
On 2017/6/9 0:35, Mark Rutland wrote:
> Hi,
>
> On Mon, May 22, 2017 at 08:48:32PM +0800, Shaokun Zhang wrote:
>> +/*
>> + * hisi_djtag_lock_v2: djtag lock to avoid djtag access conflict b/w kernel
>> + * and UEFI.
>
> The mention of UEFI here worries me somewhat, and I have a number of
Hi Ganapat
This patchset has been tested on Hisilicon's hip08 board for implementation
defined PMU events:
(1)perf list command is ok;
(2)perf stat command -e event_name:
When event number is less than 0x3ff, it is ok;
if event number is more than 0x3ff, it should be added this patch:
https://www
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