On Thu, May 29, 2014 at 04:09:48PM -0700, Andrew Morton wrote:
> On Fri, 9 May 2014 18:36:52 +0200 Johan Hovold wrote:
>
> > On Thu, May 08, 2014 at 07:28:04PM +0200, Boris BREZILLON wrote:
> >
> > > > You should also keep the flush (read of IMR) regardless (to make sure
> > > > the write has
On Thu, May 29, 2014 at 04:09:48PM -0700, Andrew Morton wrote:
On Fri, 9 May 2014 18:36:52 +0200 Johan Hovold jo...@hovold.com wrote:
On Thu, May 08, 2014 at 07:28:04PM +0200, Boris BREZILLON wrote:
You should also keep the flush (read of IMR) regardless (to make sure
the write has
On Fri, 9 May 2014 18:36:52 +0200 Johan Hovold wrote:
> On Thu, May 08, 2014 at 07:28:04PM +0200, Boris BREZILLON wrote:
>
> > > You should also keep the flush (read of IMR) regardless (to make sure
> > > the write has reached the peripheral), and remember to remove the now
> > > unused mask
On Fri, 9 May 2014 18:36:52 +0200 Johan Hovold jo...@hovold.com wrote:
On Thu, May 08, 2014 at 07:28:04PM +0200, Boris BREZILLON wrote:
You should also keep the flush (read of IMR) regardless (to make sure
the write has reached the peripheral), and remember to remove the now
unused
On Thu, May 08, 2014 at 07:28:04PM +0200, Boris BREZILLON wrote:
> > You should also keep the flush (read of IMR) regardless (to make sure
> > the write has reached the peripheral), and remember to remove the now
> > unused mask variable.
>
> Does it has something to do with memory barriers ?
>
On Thu, May 08, 2014 at 07:28:04PM +0200, Boris BREZILLON wrote:
You should also keep the flush (read of IMR) regardless (to make sure
the write has reached the peripheral), and remember to remove the now
unused mask variable.
Does it has something to do with memory barriers ?
If so,
On 08/05/2014 17:49, Johan Hovold wrote:
> On Wed, May 07, 2014 at 06:20:49PM +0200, Boris BREZILLON wrote:
>> The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
>> mask all interrupts no matter what IMR claims about already masked irqs.
> Crap, I totally forgot about this.
On 08/05/2014 05:10, Mark Roszko wrote:
> Atmel actually has this issue in the Errata of the SAM9G25 and SAM9G35
> datasheets which might be worth referencing in the description?
>
>> 49.7.1 RTC: Interrupt Mask Register cannot be used
>> Interrupt Mask Register read always returns 0.
Sure, I'll
[ Sorry for the resend -- forgot to add Doug as CC. ]
On Wed, May 07, 2014 at 06:20:49PM +0200, Boris BREZILLON wrote:
> The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
> mask all interrupts no matter what IMR claims about already masked irqs.
Crap, I totally forgot
On Wed, May 07, 2014 at 06:20:49PM +0200, Boris BREZILLON wrote:
> The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
> mask all interrupts no matter what IMR claims about already masked irqs.
Crap, I totally forgot about this. Doug reported the problem off-list
back in
On Wed, May 07, 2014 at 06:20:49PM +0200, Boris BREZILLON wrote:
The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
mask all interrupts no matter what IMR claims about already masked irqs.
Crap, I totally forgot about this. Doug reported the problem off-list
back in
[ Sorry for the resend -- forgot to add Doug as CC. ]
On Wed, May 07, 2014 at 06:20:49PM +0200, Boris BREZILLON wrote:
The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
mask all interrupts no matter what IMR claims about already masked irqs.
Crap, I totally forgot about
On 08/05/2014 05:10, Mark Roszko wrote:
Atmel actually has this issue in the Errata of the SAM9G25 and SAM9G35
datasheets which might be worth referencing in the description?
49.7.1 RTC: Interrupt Mask Register cannot be used
Interrupt Mask Register read always returns 0.
Sure, I'll quote
On 08/05/2014 17:49, Johan Hovold wrote:
On Wed, May 07, 2014 at 06:20:49PM +0200, Boris BREZILLON wrote:
The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
mask all interrupts no matter what IMR claims about already masked irqs.
Crap, I totally forgot about this. Doug
Atmel actually has this issue in the Errata of the SAM9G25 and SAM9G35
datasheets which might be worth referencing in the description?
>49.7.1 RTC: Interrupt Mask Register cannot be used
>Interrupt Mask Register read always returns 0.
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.org; linux-kernel@vger.kernel.org; Boris BREZILLON
> Subject: [PATCH] ARM: at91: fix rtc irq mask for sam9x5 SoCs
>
> The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
> mask all interrupts no matter what IMR claims about already masked irqs.
>
> Signed-off-by: B
The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
mask all interrupts no matter what IMR claims about already masked irqs.
Signed-off-by: Boris BREZILLON
Reported-by: Bryan Evenson
---
Hello Bryan,
Yet another patch for you ;-).
As usual, could you tell me if it fixes
The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
mask all interrupts no matter what IMR claims about already masked irqs.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Reported-by: Bryan Evenson beven...@melinkcorp.com
---
Hello Bryan,
Yet another
@vger.kernel.org; Boris BREZILLON
Subject: [PATCH] ARM: at91: fix rtc irq mask for sam9x5 SoCs
The RTC IMR register is not reliable on sam9x5 SoCs, hence why me have to
mask all interrupts no matter what IMR claims about already masked irqs.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Atmel actually has this issue in the Errata of the SAM9G25 and SAM9G35
datasheets which might be worth referencing in the description?
49.7.1 RTC: Interrupt Mask Register cannot be used
Interrupt Mask Register read always returns 0.
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