On Fri, 2014-02-07 at 09:51 -0600, Kumar Gala wrote:
> On Feb 7, 2014, at 3:02 AM, Torsten Duwe wrote:
>
> > On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
> >> On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
> >>> On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra
On Fri, 2014-02-07 at 10:02 +0100, Torsten Duwe wrote:
> > > > Can you pair lwarx with sthcx ? I couldn't immediately find the answer
> > > > in the PowerISA doc. If so I think you can do better by being able to
> > > > atomically load both tickets but only storing the head without affecting
> > >
On Thu, 2014-02-06 at 13:28 -0600, Tom Musta wrote:
> My read is consistent with Torsten's ... this looks like a bad idea.
>
> Look at the RTL for sthcx. on page 692 (Power ISA V2.06) and you will
> see this:
>
> if RESERVE then
> if RESERVE_LENGTH = 2 then
> ...
> else
>
On Thu, 2014-02-06 at 13:28 -0600, Tom Musta wrote:
My read is consistent with Torsten's ... this looks like a bad idea.
Look at the RTL for sthcx. on page 692 (Power ISA V2.06) and you will
see this:
if RESERVE then
if RESERVE_LENGTH = 2 then
...
else
undefined_case - 1
On Fri, 2014-02-07 at 10:02 +0100, Torsten Duwe wrote:
Can you pair lwarx with sthcx ? I couldn't immediately find the answer
in the PowerISA doc. If so I think you can do better by being able to
atomically load both tickets but only storing the head without affecting
the tail.
On Fri, 2014-02-07 at 09:51 -0600, Kumar Gala wrote:
On Feb 7, 2014, at 3:02 AM, Torsten Duwe d...@lst.de wrote:
On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra
On Fri, Feb 07, 2014 at 06:08:45PM +0100, Torsten Duwe wrote:
> > static inline unsigned int xadd(unsigned int *v, unsigned int i)
> > {
> > int t, ret;
> >
> > __asm__ __volatile__ (
> > "1: lwarx %0, 0, %4\n"
> > " mr %1, %0\n"
> > " add %0, %3, %0\n"
> > " stwcx.
On Fri, Feb 07, 2014 at 04:18:47PM +0100, Peter Zijlstra wrote:
> On Fri, Feb 07, 2014 at 01:28:37PM +0100, Peter Zijlstra wrote:
> > Anyway, you can do a version with lwarx/stwcx if you're looking get rid
> > of lharx.
>
> the below seems to compile into relatively ok asm. It can be done better
On Fri, Feb 07, 2014 at 09:51:16AM -0600, Kumar Gala wrote:
>
> On Feb 7, 2014, at 3:02 AM, Torsten Duwe wrote:
>
> > On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
> >> On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
> >>> On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter
On Feb 7, 2014, at 3:02 AM, Torsten Duwe wrote:
> On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
>> On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
>>> On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
>>
Can you pair lwarx with sthcx ? I couldn't
On Fri, Feb 07, 2014 at 04:18:47PM +0100, Peter Zijlstra wrote:
> void ticket_lock(tickets_t *lock)
> {
> tickets_t t;
>
> /*
>* Because @head is MSB, the direct increment wrap doesn't disturb
>* @tail.
>*/
> t.pair = xadd(>pair, 1<<16);
>
> if
On Fri, Feb 07, 2014 at 01:28:37PM +0100, Peter Zijlstra wrote:
> Anyway, you can do a version with lwarx/stwcx if you're looking get rid
> of lharx.
the below seems to compile into relatively ok asm. It can be done better
if you write the entire thing by hand though.
---
typedef unsigned short
On Fri, Feb 07, 2014 at 11:45:30AM +0100, Peter Zijlstra wrote:
>
> That might need to be lhz too, I'm confused on all the load variants.
;-)
> > unlock:
> > lhz %0, 0,
> > addic %0, %0, 1
No carry with this one, I'd say.
Besides, unlock increments the head.
> > lwsync
> >
On Fri, Feb 07, 2014 at 12:49:49PM +0100, Torsten Duwe wrote:
> On Fri, Feb 07, 2014 at 11:45:30AM +0100, Peter Zijlstra wrote:
> >
> > That might need to be lhz too, I'm confused on all the load variants.
>
> ;-)
>
> > > unlock:
> > > lhz %0, 0,
> > > addic %0, %0, 1
>
> No carry
On Fri, Feb 07, 2014 at 11:31:39AM +0100, Peter Zijlstra wrote:
> Anyway, what might work is something like (please forgive my ppc asm, I
> can barely read the thing, I've never before attempted writing it):
>
> lock:
> 1:lharx %0, 0,
> mov %1, %0
> addic %0, %0, 1
>
> So if you have ll/sc on the whole word concurrent with the half-word
> store, you can loose the half-word store like:
>
> lwarx
> ... sth
> stwcd
>
>
> The stwcd will over-write the tail store.
Oh wait, that's stupid, it will invalidate the lock and fail the store
On Fri, Feb 07, 2014 at 10:02:48AM +0100, Torsten Duwe wrote:
> On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
> > On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
> > > On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
> >
> > > > Can you pair lwarx with sthcx ?
On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
> On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
> > On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
>
> > > Can you pair lwarx with sthcx ? I couldn't immediately find the answer
> > > in the PowerISA doc. If so
On Thu, Feb 06, 2014 at 07:08:26PM +0100, Peter Zijlstra wrote:
> On Thu, Feb 06, 2014 at 06:37:27PM +0100, Torsten Duwe wrote:
> > I must admit that I haven't tested the patch on non-pseries ppc64 nor on
> > ppc32. Only ppc64 has the ldarx and I tried to atomically replace the
> > holder along
On Thu, Feb 06, 2014 at 07:08:26PM +0100, Peter Zijlstra wrote:
On Thu, Feb 06, 2014 at 06:37:27PM +0100, Torsten Duwe wrote:
I must admit that I haven't tested the patch on non-pseries ppc64 nor on
ppc32. Only ppc64 has the ldarx and I tried to atomically replace the
holder along with the
On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
Can you pair lwarx with sthcx ? I couldn't immediately find the answer
in the PowerISA doc. If so I think
On Fri, Feb 07, 2014 at 10:02:48AM +0100, Torsten Duwe wrote:
On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
Can you pair lwarx with sthcx ? I couldn't
So if you have ll/sc on the whole word concurrent with the half-word
store, you can loose the half-word store like:
lwarx tickets
... sth tail
stwcd tickets
The stwcd will over-write the tail store.
Oh wait, that's stupid, it will invalidate the lock and fail the
On Fri, Feb 07, 2014 at 11:31:39AM +0100, Peter Zijlstra wrote:
Anyway, what might work is something like (please forgive my ppc asm, I
can barely read the thing, I've never before attempted writing it):
lock:
1:lharx %0, 0, head
mov %1, %0
addic %0, %0, 1
On Fri, Feb 07, 2014 at 12:49:49PM +0100, Torsten Duwe wrote:
On Fri, Feb 07, 2014 at 11:45:30AM +0100, Peter Zijlstra wrote:
That might need to be lhz too, I'm confused on all the load variants.
;-)
unlock:
lhz %0, 0, tail
addic %0, %0, 1
No carry with this one,
On Fri, Feb 07, 2014 at 11:45:30AM +0100, Peter Zijlstra wrote:
That might need to be lhz too, I'm confused on all the load variants.
;-)
unlock:
lhz %0, 0, tail
addic %0, %0, 1
No carry with this one, I'd say.
Besides, unlock increments the head.
lwsync
sth
On Feb 7, 2014, at 3:02 AM, Torsten Duwe d...@lst.de wrote:
On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
Can you pair lwarx with sthcx ? I couldn't
On Fri, Feb 07, 2014 at 09:51:16AM -0600, Kumar Gala wrote:
On Feb 7, 2014, at 3:02 AM, Torsten Duwe d...@lst.de wrote:
On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote:
On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter
On Fri, Feb 07, 2014 at 04:18:47PM +0100, Peter Zijlstra wrote:
On Fri, Feb 07, 2014 at 01:28:37PM +0100, Peter Zijlstra wrote:
Anyway, you can do a version with lwarx/stwcx if you're looking get rid
of lharx.
the below seems to compile into relatively ok asm. It can be done better
if you
On Fri, Feb 07, 2014 at 06:08:45PM +0100, Torsten Duwe wrote:
static inline unsigned int xadd(unsigned int *v, unsigned int i)
{
int t, ret;
__asm__ __volatile__ (
1: lwarx %0, 0, %4\n
mr %1, %0\n
add %0, %3, %0\n
stwcx. %0, %0, %4\n
bne-
On Fri, Feb 07, 2014 at 04:18:47PM +0100, Peter Zijlstra wrote:
void ticket_lock(tickets_t *lock)
{
tickets_t t;
/*
* Because @head is MSB, the direct increment wrap doesn't disturb
* @tail.
*/
t.pair = xadd(lock-pair, 116);
if
On Fri, Feb 07, 2014 at 01:28:37PM +0100, Peter Zijlstra wrote:
Anyway, you can do a version with lwarx/stwcx if you're looking get rid
of lharx.
the below seems to compile into relatively ok asm. It can be done better
if you write the entire thing by hand though.
---
typedef unsigned short
On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
> On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
> > On Thu, Feb 06, 2014 at 11:37:37AM +0100, Torsten Duwe wrote:
> > > x86 has them, MIPS has them, ARM has them, even ia64 has them:
> > > ticket locks. They reduce memory bus
On 2/6/2014 12:08 PM, Peter Zijlstra wrote:
>>> Can you pair lwarx with sthcx ? I couldn't immediately find the answer
>>> > > in the PowerISA doc. If so I think you can do better by being able to
>>> > > atomically load both tickets but only storing the head without affecting
>>> > > the tail.
>>
On Thu, Feb 06, 2014 at 06:37:27PM +0100, Torsten Duwe wrote:
> On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
> > On Thu, Feb 06, 2014 at 11:37:37AM +0100, Torsten Duwe wrote:
> > > x86 has them, MIPS has them, ARM has them, even ia64 has them:
> > > ticket locks. They reduce
On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
> On Thu, Feb 06, 2014 at 11:37:37AM +0100, Torsten Duwe wrote:
> > x86 has them, MIPS has them, ARM has them, even ia64 has them:
> > ticket locks. They reduce memory bus and cache pressure especially
> > for contended spinlocks,
On Thu, Feb 06, 2014 at 11:37:37AM +0100, Torsten Duwe wrote:
> x86 has them, MIPS has them, ARM has them, even ia64 has them:
> ticket locks. They reduce memory bus and cache pressure especially
> for contended spinlocks, increasing performance.
>
> This patch is a port of the x86 spin locks,
On Thu, 2014-02-06 at 11:37 +0100, Torsten Duwe wrote:
> x86 has them, MIPS has them, ARM has them, even ia64 has them:
> ticket locks. They reduce memory bus and cache pressure especially
> for contended spinlocks, increasing performance.
>
> This patch is a port of the x86 spin locks, mostly
x86 has them, MIPS has them, ARM has them, even ia64 has them:
ticket locks. They reduce memory bus and cache pressure especially
for contended spinlocks, increasing performance.
This patch is a port of the x86 spin locks, mostly written in C,
to the powerpc, introducing inline asm where needed.
x86 has them, MIPS has them, ARM has them, even ia64 has them:
ticket locks. They reduce memory bus and cache pressure especially
for contended spinlocks, increasing performance.
This patch is a port of the x86 spin locks, mostly written in C,
to the powerpc, introducing inline asm where needed.
On Thu, 2014-02-06 at 11:37 +0100, Torsten Duwe wrote:
x86 has them, MIPS has them, ARM has them, even ia64 has them:
ticket locks. They reduce memory bus and cache pressure especially
for contended spinlocks, increasing performance.
This patch is a port of the x86 spin locks, mostly written
On Thu, Feb 06, 2014 at 11:37:37AM +0100, Torsten Duwe wrote:
x86 has them, MIPS has them, ARM has them, even ia64 has them:
ticket locks. They reduce memory bus and cache pressure especially
for contended spinlocks, increasing performance.
This patch is a port of the x86 spin locks, mostly
On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
On Thu, Feb 06, 2014 at 11:37:37AM +0100, Torsten Duwe wrote:
x86 has them, MIPS has them, ARM has them, even ia64 has them:
ticket locks. They reduce memory bus and cache pressure especially
for contended spinlocks, increasing
On Thu, Feb 06, 2014 at 06:37:27PM +0100, Torsten Duwe wrote:
On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
On Thu, Feb 06, 2014 at 11:37:37AM +0100, Torsten Duwe wrote:
x86 has them, MIPS has them, ARM has them, even ia64 has them:
ticket locks. They reduce memory bus
On 2/6/2014 12:08 PM, Peter Zijlstra wrote:
Can you pair lwarx with sthcx ? I couldn't immediately find the answer
in the PowerISA doc. If so I think you can do better by being able to
atomically load both tickets but only storing the head without affecting
the tail.
V2.06b, Book
On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote:
On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote:
On Thu, Feb 06, 2014 at 11:37:37AM +0100, Torsten Duwe wrote:
x86 has them, MIPS has them, ARM has them, even ia64 has them:
ticket locks. They reduce memory bus and
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