Hi James,
> On Tuesday, February 5, 2019 9:31 AM, James Morse wrote:
>> We have firmware to config the memory controller and want to have an EDAC
>> driver to report ECC status.
>> Could you please elaborate a bit on the security concern on this
>> approach? Like some malicious app/driver can
Hi Rui,
On 23/01/2019 22:08, Rui Zhao wrote:
> On Wednesday, January 23, 2019 10:36 AM, James Morse wrote:
>>> If firmware enables it, they're suppose to handle the interrupt.
>> Ah, so you still have resident firmware!
>> How come your firmware trusts linux not to turn off the memory controller?
Hi Boris,
On 23/01/2019 18:46, Borislav Petkov wrote:
> On Wed, Jan 23, 2019 at 06:36:23PM +, James Morse wrote:
>>> Would like to know what's the impact if this error happens, and how to fit
>>> it
>>> with current reporting in EDAC core.
>>
>> At a guess the interrupt triggers when link_err
Hi James,
On Wednesday, January 23, 2019 10:36 AM, James Morse wrote:
> When the time comes, could you post a dt-binding as the first patch? These
> add the documentation under Documentation/device-tree/bindings, and need to
> be CC'd to the DT folks.
Sure, will do.
>> Will change scrub_mode t
On Wed, Jan 23, 2019 at 08:03:54PM +0100, Borislav Petkov wrote:
On Wed, Jan 23, 2019 at 01:50:07PM -0500, Sasha Levin wrote:
A variant of a Broadcom's SST100 board.
Is that some platform which people will use and run linux on and thus
would make sense to have an EDAC driver for or is this som
On Wed, Jan 23, 2019 at 01:50:07PM -0500, Sasha Levin wrote:
> A variant of a Broadcom's SST100 board.
Is that some platform which people will use and run linux on and thus
would make sense to have an EDAC driver for or is this something
devel-only toy thing?
Searching a bit doesn't tell me a who
On Mon, Jan 21, 2019 at 01:35:47PM +0100, Borislav Petkov wrote:
On Fri, Jan 18, 2019 at 11:23:24AM -0500, Sasha Levin wrote:
From: Rui Zhao
New driver supports DRAM error detection and correction on DMC520
controller.
That's this thing, right?
https://developer.arm.com/products/system-ip/m
On Wed, Jan 23, 2019 at 06:36:23PM +, James Morse wrote:
> > Would like to know what's the impact if this error happens, and how to fit
> > it
> > with current reporting in EDAC core.
>
> At a guess the interrupt triggers when link_err_count increases. (link_err has
> an overflow bit, so the
Hi Rui,
On 23/01/2019 00:42, Rui Zhao wrote:
> On Monday, January 21, 2019 9:09 AM, James Morse wrote:
>> It would be good if we can make this generic, so it works on all platforms
>> with
>> a DMC520, possibly along with other components. (e.g. the a15 L2 driver
>> posted
>> recently).
>>
>> Th
Hi Sasha, Rui,
On 18/01/2019 16:23, Sasha Levin wrote:
> From: Rui Zhao
> New driver supports DRAM error detection and correction on DMC520
> controller.
> Validated on actual hardware: DRAM errors showed up once the DDR core
> voltage was lowered down by 200+mV using test tool.
That's quite co
On Fri, Jan 18, 2019 at 11:23:24AM -0500, Sasha Levin wrote:
> From: Rui Zhao
>
> New driver supports DRAM error detection and correction on DMC520
> controller.
That's this thing, right?
https://developer.arm.com/products/system-ip/memory-controllers/corelink-dmc-520
> Validated on actual har
From: Rui Zhao
New driver supports DRAM error detection and correction on DMC520
controller.
Validated on actual hardware: DRAM errors showed up once the DDR core
voltage was lowered down by 200+mV using test tool.
Signed-off-by: Rui Zhao
[sl: minor nits in commit message and code, added maint
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