On 5/25/2016 2:33 PM, Bjorn Helgaas wrote:
> It looks like the code enforces this by clearing bits in
> link->aspm_capable (effectively pretending L0s or L1 are unsupported)
> if the latency is too high.
Yes, this is what I was referring to. I think what Linux does is
the right thing.
--
Sinan K
On Wed, May 25, 2016 at 02:19:01PM -0400, Sinan Kaya wrote:
> On 5/25/2016 1:50 PM, Bjorn Helgaas wrote:
> >> > You are saying that it is OK to enable L0s on just one side of the
> >> > link as long as both sides support L0s.
> > I'm not sure what you mean by the link parameters not being
> > comp
On 5/25/2016 1:50 PM, Bjorn Helgaas wrote:
>> > You are saying that it is OK to enable L0s on just one side of the
>> > link as long as both sides support L0s.
> I'm not sure what you mean by the link parameters not being
> compatible, but I think it is legal to enable L0s on only one
> direction.
On Wed, May 25, 2016 at 01:21:12PM -0400, Sinan Kaya wrote:
> Hi Bjorn,
>
> OK. I see that we are dealing with two different questions.
>
> > I thought you were talking about booting with
> > "pcie_aspm.policy=powersave", where pcie_aspm_set_policy() sets
> > aspm_policy = POLICY_POWERSAVE, then
Hi Bjorn,
OK. I see that we are dealing with two different questions.
> I thought you were talking about booting with
> "pcie_aspm.policy=powersave", where pcie_aspm_set_policy() sets
> aspm_policy = POLICY_POWERSAVE, then configures each link with
> ASPM_STATE_ALL. But pcie_config_aspm_link() d
On Tue, May 24, 2016 at 06:29:44AM +, Ocean HY1 He wrote:
> In pcie_config_aspm_link(), when convert ASPM state to
> upstream/downstream ASPM register state, the upstream variable and
> dwsream variable are reversed. This causes PCI/E link enter ASPM L0s
> even it should be disabled and PCI/E e
On Tue, May 24, 2016 at 10:42:31AM -0400, Sinan Kaya wrote:
> On 5/24/2016 7:53 AM, Bjorn Helgaas wrote:
> > On Tue, May 24, 2016 at 06:29:44AM +, Ocean HY1 He wrote:
> >> > In pcie_config_aspm_link(), when convert ASPM state to
> >> > upstream/downstream ASPM register state, the upstream varia
da Chumbalkar
Subject: Re: [PATCH] PCI/ASPM: fix reverse ASPM L0s assignment of upstream and
downstream
Hi Ocean,
On Tue, May 24, 2016 at 06:29:44AM +, Ocean HY1 He wrote:
> In pcie_config_aspm_link(), when convert ASPM state to
> upstream/downstream ASPM register state, the upstream
On 5/24/2016 7:53 AM, Bjorn Helgaas wrote:
> On Tue, May 24, 2016 at 06:29:44AM +, Ocean HY1 He wrote:
>> > In pcie_config_aspm_link(), when convert ASPM state to
>> > upstream/downstream ASPM register state, the upstream variable and
>> > dwsream variable are reversed. This causes PCI/E link e
Hi Ocean,
On Tue, May 24, 2016 at 06:29:44AM +, Ocean HY1 He wrote:
> In pcie_config_aspm_link(), when convert ASPM state to
> upstream/downstream ASPM register state, the upstream variable and
> dwsream variable are reversed. This causes PCI/E link enter ASPM L0s
> even it should be disabled
In pcie_config_aspm_link(), when convert ASPM state to
upstream/downstream ASPM register state, the upstream variable and
dwsream variable are reversed. This causes PCI/E link enter ASPM L0s
even it should be disabled and PCI/E endpoint may reset randomly.
Signed-off-by: Ocean He
---
drivers/pci
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