On Wed, 2005-02-09 at 15:06 -0800, Andrew Morton wrote:
> Paul Mackerras <[EMAIL PROTECTED]> wrote:
> >
> > POWER5 machines have a per-hardware-thread register which counts at a
> > rate which is proportional to the percentage of cycles on which the
> > cpu dispatches an instruction for this
Paul Mackerras <[EMAIL PROTECTED]> wrote:
>
> POWER5 machines have a per-hardware-thread register which counts at a
> rate which is proportional to the percentage of cycles on which the
> cpu dispatches an instruction for this thread (if the thread gets all
> the dispatch cycles it counts at the
POWER5 machines have a per-hardware-thread register which counts at a
rate which is proportional to the percentage of cycles on which the
cpu dispatches an instruction for this thread (if the thread gets all
the dispatch cycles it counts at the same rate as the timebase
register). This register
POWER5 machines have a per-hardware-thread register which counts at a
rate which is proportional to the percentage of cycles on which the
cpu dispatches an instruction for this thread (if the thread gets all
the dispatch cycles it counts at the same rate as the timebase
register). This register
Paul Mackerras [EMAIL PROTECTED] wrote:
POWER5 machines have a per-hardware-thread register which counts at a
rate which is proportional to the percentage of cycles on which the
cpu dispatches an instruction for this thread (if the thread gets all
the dispatch cycles it counts at the same
On Wed, 2005-02-09 at 15:06 -0800, Andrew Morton wrote:
Paul Mackerras [EMAIL PROTECTED] wrote:
POWER5 machines have a per-hardware-thread register which counts at a
rate which is proportional to the percentage of cycles on which the
cpu dispatches an instruction for this thread (if the
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