Quoting Dinh Nguyen (2019-08-14 08:30:14)
> Checking bypass_reg is incorrect for calculating the cnt_clk rates.
> Instead we should be checking that there is a proper hardware register
> that holds the clock divider.
>
> Cc: sta...@vger.kernel.org
> Signed-off-by: Dinh Nguyen
> ---
Applied to cl
Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.
Cc: sta...@vger.kernel.org
Signed-off-by: Dinh Nguyen
---
drivers/clk/socfpga/clk-periph-s10.c | 2 +-
1 file changed, 1 insert
2 matches
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