Re: [PATCH] i2c: tegra: add support for Tegra114 SoC

2013-01-23 Thread Wolfram Sang
On Sat, Jan 05, 2013 at 05:34:46PM +0530, Laxman Dewangan wrote: > NVIDIA's Tegra114 has following enhanced feature in i2c controller: > - Enable/disable control for per packet transfer complete interrupt. > Earlier SoCs could not disable this. > - Single clock source for standard/fast and HS

Re: [PATCH] i2c: tegra: add support for Tegra114 SoC

2013-01-23 Thread Wolfram Sang
On Sat, Jan 05, 2013 at 05:34:46PM +0530, Laxman Dewangan wrote: NVIDIA's Tegra114 has following enhanced feature in i2c controller: - Enable/disable control for per packet transfer complete interrupt. Earlier SoCs could not disable this. - Single clock source for standard/fast and HS mode

Re: [PATCH] i2c: tegra: add support for Tegra114 SoC

2013-01-07 Thread Stephen Warren
On 01/05/2013 05:04 AM, Laxman Dewangan wrote: > NVIDIA's Tegra114 has following enhanced feature in i2c controller: > - Enable/disable control for per packet transfer complete interrupt. > Earlier SoCs could not disable this. > - Single clock source for standard/fast and HS mode clock speed. >

Re: [PATCH] i2c: tegra: add support for Tegra114 SoC

2013-01-07 Thread Stephen Warren
On 01/05/2013 05:04 AM, Laxman Dewangan wrote: NVIDIA's Tegra114 has following enhanced feature in i2c controller: - Enable/disable control for per packet transfer complete interrupt. Earlier SoCs could not disable this. - Single clock source for standard/fast and HS mode clock speed. The

[PATCH] i2c: tegra: add support for Tegra114 SoC

2013-01-05 Thread Laxman Dewangan
NVIDIA's Tegra114 has following enhanced feature in i2c controller: - Enable/disable control for per packet transfer complete interrupt. Earlier SoCs could not disable this. - Single clock source for standard/fast and HS mode clock speed. The clock divisor for fast/standard mode is added into

[PATCH] i2c: tegra: add support for Tegra114 SoC

2013-01-05 Thread Laxman Dewangan
NVIDIA's Tegra114 has following enhanced feature in i2c controller: - Enable/disable control for per packet transfer complete interrupt. Earlier SoCs could not disable this. - Single clock source for standard/fast and HS mode clock speed. The clock divisor for fast/standard mode is added into