On Sat, Jan 05, 2013 at 05:34:46PM +0530, Laxman Dewangan wrote:
> NVIDIA's Tegra114 has following enhanced feature in i2c controller:
> - Enable/disable control for per packet transfer complete interrupt.
> Earlier SoCs could not disable this.
> - Single clock source for standard/fast and HS
On Sat, Jan 05, 2013 at 05:34:46PM +0530, Laxman Dewangan wrote:
NVIDIA's Tegra114 has following enhanced feature in i2c controller:
- Enable/disable control for per packet transfer complete interrupt.
Earlier SoCs could not disable this.
- Single clock source for standard/fast and HS mode
On 01/05/2013 05:04 AM, Laxman Dewangan wrote:
> NVIDIA's Tegra114 has following enhanced feature in i2c controller:
> - Enable/disable control for per packet transfer complete interrupt.
> Earlier SoCs could not disable this.
> - Single clock source for standard/fast and HS mode clock speed.
>
On 01/05/2013 05:04 AM, Laxman Dewangan wrote:
NVIDIA's Tegra114 has following enhanced feature in i2c controller:
- Enable/disable control for per packet transfer complete interrupt.
Earlier SoCs could not disable this.
- Single clock source for standard/fast and HS mode clock speed.
The
NVIDIA's Tegra114 has following enhanced feature in i2c controller:
- Enable/disable control for per packet transfer complete interrupt.
Earlier SoCs could not disable this.
- Single clock source for standard/fast and HS mode clock speed.
The clock divisor for fast/standard mode is added into
NVIDIA's Tegra114 has following enhanced feature in i2c controller:
- Enable/disable control for per packet transfer complete interrupt.
Earlier SoCs could not disable this.
- Single clock source for standard/fast and HS mode clock speed.
The clock divisor for fast/standard mode is added into
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