>
>>> +static int iadc_poll_wait_eoc(struct iadc_chip *iadc, int interval_us)
>>> +{
>>> + int ret, count, retry;
>>> + u8 sta1;
>>> +
>>> + retry = interval_us / IADC_CONV_TIME_MIN_US;
>>> +
>>> + for (count = 0; count < retry; count++) {
>>> + ret = iadc_read(iadc, IADC_STATUS
Hi,
On Sun, 2014-09-21 at 15:04 +0100, Jonathan Cameron wrote:
> On 18/09/14 14:15, Ivan T. Ivanov wrote:
> > +config QCOM_SPMI_IADC
> > + tristate "Qualcomm SPMI PMIC current ADC"
> > + select REGMAP_SPMI
> > + depends on IIO
> > + help
> > + This is the IIO Current ADC driver fo
On 18/09/14 14:15, Ivan T. Ivanov wrote:
> The current ADC is peripheral of Qualcomm SPMI PMIC chips. It has
> 16 bits resolution and register space inside PMIC accessible across
> SPMI bus.
>
> The driver registers itself through IIO interface.
>
> Signed-off-by: Ivan T. Ivanov
A few comments fro
Hi Kiran,
On Fri, 2014-09-19 at 15:49 +0530, Kiran Padwal wrote:
> Hi Ivan,
>
> On Thursday 18 September 2014 06:45 PM, Ivan T. Ivanov wrote:
> > The current ADC is peripheral of Qualcomm SPMI PMIC chips. It has
> > 16 bits resolution and register space inside PMIC accessible across
> > SPMI bus
Hi Ivan,
On Thursday 18 September 2014 06:45 PM, Ivan T. Ivanov wrote:
> The current ADC is peripheral of Qualcomm SPMI PMIC chips. It has
> 16 bits resolution and register space inside PMIC accessible across
> SPMI bus.
>
> The driver registers itself through IIO interface.
>
> Signed-off-by: I
The current ADC is peripheral of Qualcomm SPMI PMIC chips. It has
16 bits resolution and register space inside PMIC accessible across
SPMI bus.
The driver registers itself through IIO interface.
Signed-off-by: Ivan T. Ivanov
---
.../devicetree/bindings/iio/adc/qcom,spmi-iadc.txt | 61 ++
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