arm-ker...@lists.infradead.org'
> ; Linuxarm ;
> xuwei (O)
> Subject: 答复: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
>
> Hi Ard and all,
>
> The issue is root caused, it is introduced by BIOS new feature implemented.
> With old BIOS，we use static M
20年12月15日 15:49
收件人: Shameerali Kolothum Thodi ; Ard
Biesheuvel
抄送: Marc Zyngier ; eric.au...@redhat.com;
linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Linuxarm
; xuwei (O)
主题: 答复: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
Sorry response late.
Hi Sh
Linuxarm
> ; xuwei (O)
> Subject: 答复: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
>
> Sorry response late.
> Hi Shameer & Ard,
>
> Could you let me know which firmware you are using? If the difference is Madt
> table vGIC your pointed , they are the same.
发送时间: 2020年12月2日 16:23
收件人: Ard Biesheuvel
抄送: Marc Zyngier ; eric.au...@redhat.com;
linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; Linuxarm
; wanghuiqiang ; xuwei (O)
主题: RE: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
[+]
> -Original Message-
> Subject: Re: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
>
...
>
> Any clue why production D06 firmware deviates from the D06 port that
> exists in Tianocore's edk2-platforms repository? Because that version
> does not have this bug, and I wonde
g; linux-arm-ker...@lists.infradead.org;
> > eric.au...@redhat.com; Linuxarm
> > Subject: Re: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
> >
> > Hi Shameer,
> >
> > On 2020-11-30 13:55, Shameerali Kolothum Thodi wrote:
> > > Hi Marc,
>
ber 2020 12:28
> >> To: Shameerali Kolothum Thodi
> >> Cc: linux-kernel@vger.kernel.org;
> >> linux-arm-ker...@lists.infradead.org;
> >> eric.au...@redhat.com; Linuxarm
> >> Subject: Re: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy
> >>
...@redhat.com; Linuxarm
Subject: Re: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy
support
Hi Shameer,
On 2020-11-30 10:26, Shameer Kolothum wrote:
> At present, the support for GICv2 backward compatibility on GICv3/v4
> hardware is determined based on whether DT/ACPI provides a
PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
>
> Hi Shameer,
>
> On 2020-11-30 10:26, Shameer Kolothum wrote:
> > At present, the support for GICv2 backward compatibility on GICv3/v4
> > hardware is determined based on whether DT/ACPI provides a memory
>
Subject: Re: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy
support
Hi Shameer,
On 2020/11/30 18:26, Shameer Kolothum wrote:
> At present, the support for GICv2 backward compatibility on GICv3/v4
> hardware is determined based on whether DT/ACPI provides a memory
> mapped phys bas
Hi Shameer,
On 2020-11-30 10:26, Shameer Kolothum wrote:
At present, the support for GICv2 backward compatibility on GICv3/v4
hardware is determined based on whether DT/ACPI provides a memory
mapped phys base address for GIC virtual CPU interface register(GICV).
This creates a problem that a Qem
H] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
>
> Hi Shameer,
>
> On 2020/11/30 18:26, Shameer Kolothum wrote:
> > At present, the support for GICv2 backward compatibility on GICv3/v4
> > hardware is determined based on whether DT/ACPI provides a memory
> >
Hi Shameer,
On 2020/11/30 18:26, Shameer Kolothum wrote:
At present, the support for GICv2 backward compatibility on GICv3/v4
hardware is determined based on whether DT/ACPI provides a memory
mapped phys base address for GIC virtual CPU interface register(GICV).
This creates a problem that a Qem
At present, the support for GICv2 backward compatibility on GICv3/v4
hardware is determined based on whether DT/ACPI provides a memory
mapped phys base address for GIC virtual CPU interface register(GICV).
This creates a problem that a Qemu guest boot with default GIC(GICv2)
hangs when firmware fal
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