On Wed, Mar 06, 2013 at 02:05:52PM +0100, Thomas Gleixner wrote:
> On Wed, 6 Mar 2013, Simon Horman wrote:
>
> > On Wed, Mar 06, 2013 at 11:01:14AM +0100, Thomas Gleixner wrote:
> > > On Wed, 6 Mar 2013, Simon Horman wrote:
> > > > On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> > >
On Wed, 6 Mar 2013, Simon Horman wrote:
> On Wed, Mar 06, 2013 at 11:01:14AM +0100, Thomas Gleixner wrote:
> > On Wed, 6 Mar 2013, Simon Horman wrote:
> > > On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> > > > The SoCs using this driver are currently mainly used
> > > > together wi
On Wed, Mar 06, 2013 at 11:01:14AM +0100, Thomas Gleixner wrote:
> On Wed, 6 Mar 2013, Simon Horman wrote:
> > On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> > > The SoCs using this driver are currently mainly used
> > > together with regular platform devices so this driver
> > > al
On Wed, 6 Mar 2013, Simon Horman wrote:
> On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> > The SoCs using this driver are currently mainly used
> > together with regular platform devices so this driver
> > allows configuration via platform data to support things
> > like static inte
On Wed, Feb 27, 2013 at 7:28 PM, Paul Mundt wrote:
> On Wed, Feb 27, 2013 at 06:52:51PM +0900, Magnus Damm wrote:
>> As you know, the INTC code that you are referring to is a full
>> interrupt controller designed to work directly with CPU cores like SH
>> and ARM. Newer ARM cores like Cortex-A9 al
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> From: Magnus Damm
>
> This patch adds a driver for external IRQ pins connected
> to the INTC block on recent SoCs from Renesas.
>
> The INTC hardware block usually contains a rather wide
> range of features ranging from external IRQ
On Wed, Feb 27, 2013 at 06:52:51PM +0900, Magnus Damm wrote:
> As you know, the INTC code that you are referring to is a full
> interrupt controller designed to work directly with CPU cores like SH
> and ARM. Newer ARM cores like Cortex-A9 all include the GIC both for
> IPI purpose in case of SMP a
On Wed, Feb 27, 2013 at 5:52 PM, Paul Mundt wrote:
> On Wed, Feb 27, 2013 at 05:35:51PM +0900, Magnus Damm wrote:
>> On Wed, Feb 27, 2013 at 5:23 PM, Paul Mundt wrote:
>> > So how exactly does this interact with the existing sh_intc code? Or is
>> > there some reason why you have opted to bypass
On Wed, Feb 27, 2013 at 05:35:51PM +0900, Magnus Damm wrote:
> On Wed, Feb 27, 2013 at 5:23 PM, Paul Mundt wrote:
> > So how exactly does this interact with the existing sh_intc code? Or is
> > there some reason why you have opted to bypass it in order to implement a
> > simplified reduced-functio
On Wed, Feb 27, 2013 at 5:23 PM, Paul Mundt wrote:
> On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> This patch adds a driver for external IRQ pins connected
>> to the INTC block on recent SoCs from Renesas.
>>
> So how exactly does this interact with the e
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> From: Magnus Damm
>
> This patch adds a driver for external IRQ pins connected
> to the INTC block on recent SoCs from Renesas.
>
So how exactly does this interact with the existing sh_intc code? Or is
there some reason why you have
On Tue, 19 Feb 2013, Magnus Damm wrote:
> On Tue, Feb 19, 2013 at 7:11 PM, Thomas Gleixner wrote:
> >> +static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
> >
> > Shouldn't the lock be part of struct intc_irqpin_priv ?
>
> Good idea, but I need to lock access to the SENSE
Hi Thomas,
Thanks for your help with the review!
On Tue, Feb 19, 2013 at 7:11 PM, Thomas Gleixner wrote:
> Magnus,
>
> On Mon, 18 Feb 2013, Magnus Damm wrote:
>
>> +static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
>> + int reg)
>>
Hi Morimoto-san,
On Tue, Feb 19, 2013 at 10:04 AM, Kuninori Morimoto
wrote:
>
> Hi Magnus
>
> Thank you for this patch.
> Small comment from me :)
Sure, thanks!
>> +struct intc_irqpin_priv {
>> + struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
>> + struct intc_irqpin_irq irq[INTC_IR
On Tue, Feb 19, 2013 at 10:03 AM, Simon Horman wrote:
> On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
>> From: Magnus Damm
>>
>> This patch adds a driver for external IRQ pins connected
>> to the INTC block on recent SoCs from Renesas.
>>
>> The INTC hardware block usually contains
Magnus,
On Mon, 18 Feb 2013, Magnus Damm wrote:
> +static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
> + int reg)
> +{
> + struct intc_irqpin_iomem *i = &p->iomem[reg];
Newline between variable and code please.
> + return i
Hi Magnus
Thank you for this patch.
Small comment from me :)
> +struct intc_irqpin_priv {
> + struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
> + struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
> + struct renesas_intc_irqpin_config config;
> + unsigned int number_of_irqs;
> +
On Mon, Feb 18, 2013 at 11:28:34PM +0900, Magnus Damm wrote:
> From: Magnus Damm
>
> This patch adds a driver for external IRQ pins connected
> to the INTC block on recent SoCs from Renesas.
>
> The INTC hardware block usually contains a rather wide
> range of features ranging from external IRQ
From: Magnus Damm
This patch adds a driver for external IRQ pins connected
to the INTC block on recent SoCs from Renesas.
The INTC hardware block usually contains a rather wide
range of features ranging from external IRQ pin handling
to legacy interrupt controller support. On older SoCs
the INTC
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