On Tue, Oct 22, 2013 at 06:28:13PM +0200, Sebastian Andrzej Siewior wrote:
> On 10/22/2013 05:48 PM, Lee Jones wrote:
> > On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> >
> >> On 08/07/2013 10:40 AM, Lee Jones wrote:
> >>> On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
> >>>
>
On Tue, Oct 22, 2013 at 06:28:13PM +0200, Sebastian Andrzej Siewior wrote:
On 10/22/2013 05:48 PM, Lee Jones wrote:
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
On 08/07/2013 10:40 AM, Lee Jones wrote:
On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
Reg_cache variable is used
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> On 10/22/2013 07:06 PM, Lee Jones wrote:
> > Hmm.. I'm starting to see what you mean.
> >
> > So what's the point of the read before write then?
> >
> > Why don't you use the cache all of the time?
>
> I'm waiting for Zabair for this. The
On 10/22/2013 07:06 PM, Lee Jones wrote:
> Hmm.. I'm starting to see what you mean.
>
> So what's the point of the read before write then?
>
> Why don't you use the cache all of the time?
I'm waiting for Zabair for this. The last thing he said is that he is
going to have a wedding which might
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> On 10/22/2013 06:05 PM, Lee Jones wrote:
> >> I added reg_se_cache to cache the content of REG_SE once and
> >> synchronize it among TSC & ADC access. REG_SE is set to 0 by the HW
> >> after "work" has been done. So you need to know the old
On 10/22/2013 06:05 PM, Lee Jones wrote:
>> I added reg_se_cache to cache the content of REG_SE once and
>> synchronize it among TSC & ADC access. REG_SE is set to 0 by the HW
>> after "work" has been done. So you need to know the old value or TSC may
>> disable ADC and the other way around.
>
>
On 10/22/2013 05:48 PM, Lee Jones wrote:
> On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
>
>> On 08/07/2013 10:40 AM, Lee Jones wrote:
>>> On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
>>>
Reg_cache variable is used to lock step enable register
from being accessed and written by
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> On 08/07/2013 10:40 AM, Lee Jones wrote:
> > On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
> >
> >> Reg_cache variable is used to lock step enable register
> >> from being accessed and written by both TSC and ADC
> >> at the same time.
> >>
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> On 08/07/2013 10:40 AM, Lee Jones wrote:
> > On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
> >
> >> Reg_cache variable is used to lock step enable register
> >> from being accessed and written by both TSC and ADC
> >> at the same time.
> >>
On 08/07/2013 10:40 AM, Lee Jones wrote:
> On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
>
>> Reg_cache variable is used to lock step enable register
>> from being accessed and written by both TSC and ADC
>> at the same time.
>> However, it isn't updated anywhere in the code at all.
>>
>> If both
On 08/07/2013 10:40 AM, Lee Jones wrote:
On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
Reg_cache variable is used to lock step enable register
from being accessed and written by both TSC and ADC
at the same time.
However, it isn't updated anywhere in the code at all.
If both TSC and ADC
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
On 08/07/2013 10:40 AM, Lee Jones wrote:
On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
Reg_cache variable is used to lock step enable register
from being accessed and written by both TSC and ADC
at the same time.
However, it isn't
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
On 08/07/2013 10:40 AM, Lee Jones wrote:
On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
Reg_cache variable is used to lock step enable register
from being accessed and written by both TSC and ADC
at the same time.
However, it isn't
On 10/22/2013 05:48 PM, Lee Jones wrote:
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
On 08/07/2013 10:40 AM, Lee Jones wrote:
On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
Reg_cache variable is used to lock step enable register
from being accessed and written by both TSC and ADC
On 10/22/2013 06:05 PM, Lee Jones wrote:
I added reg_se_cache to cache the content of REG_SE once and
synchronize it among TSC ADC access. REG_SE is set to 0 by the HW
after work has been done. So you need to know the old value or TSC may
disable ADC and the other way around.
Yep, it's
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
On 10/22/2013 06:05 PM, Lee Jones wrote:
I added reg_se_cache to cache the content of REG_SE once and
synchronize it among TSC ADC access. REG_SE is set to 0 by the HW
after work has been done. So you need to know the old value or TSC
On 10/22/2013 07:06 PM, Lee Jones wrote:
Hmm.. I'm starting to see what you mean.
So what's the point of the read before write then?
Why don't you use the cache all of the time?
I'm waiting for Zabair for this. The last thing he said is that he is
going to have a wedding which might
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
On 10/22/2013 07:06 PM, Lee Jones wrote:
Hmm.. I'm starting to see what you mean.
So what's the point of the read before write then?
Why don't you use the cache all of the time?
I'm waiting for Zabair for this. The last thing
On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
> Reg_cache variable is used to lock step enable register
> from being accessed and written by both TSC and ADC
> at the same time.
> However, it isn't updated anywhere in the code at all.
>
> If both TSC and ADC are used, eventually 1 is always
>
On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
Reg_cache variable is used to lock step enable register
from being accessed and written by both TSC and ADC
at the same time.
However, it isn't updated anywhere in the code at all.
If both TSC and ADC are used, eventually 1 is always
Reg_cache variable is used to lock step enable register
from being accessed and written by both TSC and ADC
at the same time.
However, it isn't updated anywhere in the code at all.
If both TSC and ADC are used, eventually 1 is always
written enabling all 16 steps uselessly causing a mess.
Reg_cache variable is used to lock step enable register
from being accessed and written by both TSC and ADC
at the same time.
However, it isn't updated anywhere in the code at all.
If both TSC and ADC are used, eventually 1 is always
written enabling all 16 steps uselessly causing a mess.
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