On Thu, May 15, 2014 at 4:32 PM, Andi Kleen wrote:
> On Thu, May 15, 2014 at 01:53:37PM +0200, Stephane Eranian wrote:
>>
>> This patches fixes a bug in precise_store_data_hsw() whereby
>> it would set the data source memory level to the wrong value.
>>
>> As per the the SDM Vol 3b Table 18-41 (L
On Thu, May 15, 2014 at 01:53:37PM +0200, Stephane Eranian wrote:
>
> This patches fixes a bug in precise_store_data_hsw() whereby
> it would set the data source memory level to the wrong value.
>
> As per the the SDM Vol 3b Table 18-41 (Layout of Data Linear
> Address Information in PEBS Record
This patches fixes a bug in precise_store_data_hsw() whereby
it would set the data source memory level to the wrong value.
As per the the SDM Vol 3b Table 18-41 (Layout of Data Linear
Address Information in PEBS Record), when status bit 0 is set
this is a L1 hit, otherwise this is a L1 miss.
T
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