Re: [PATCH] riscv: kbuild: drop CONFIG_RISCV_ISA_C

2019-08-30 Thread Paul Walmsley
Hi Charles, On Tue, 13 Aug 2019, Charles Papon wrote: > > Because it it the unix platform baseline as stated in the patch. > I know that, but i'm looking for arguments why RVC could't be kept as > an option, especialy it is only an optimisation option without > behavioral/code changes. > > That

Re: [PATCH] riscv: kbuild: drop CONFIG_RISCV_ISA_C

2019-08-12 Thread Christoph Hellwig
On Tue, Aug 13, 2019 at 12:18:22AM +0200, Charles Papon wrote: > > Because it it the unix platform baseline as stated in the patch. > I know that, but i'm looking for arguments why RVC could't be kept as > an option, especialy it is only an optimisation option without > behavioral/code changes. >

Re: [PATCH] riscv: kbuild: drop CONFIG_RISCV_ISA_C

2019-08-12 Thread Charles Papon
> Because it it the unix platform baseline as stated in the patch. I know that, but i'm looking for arguments why RVC could't be kept as an option, especialy it is only an optimisation option without behavioral/code changes. That baseline make sense for heavy linux distributions, where you expect

Re: [PATCH] riscv: kbuild: drop CONFIG_RISCV_ISA_C

2019-08-12 Thread Darius Rad
On 8/12/19 11:03 AM, Christoph Hellwig wrote: On Thu, Aug 08, 2019 at 02:18:53PM +0200, Charles Papon wrote: Please do not drop it. Compressed instruction extension has some specific overhead in small RISC-V FPGA softcore, especialy in the ones which can't implement the register file read in a

Re: [PATCH] riscv: kbuild: drop CONFIG_RISCV_ISA_C

2019-08-12 Thread Christoph Hellwig
On Thu, Aug 08, 2019 at 02:18:53PM +0200, Charles Papon wrote: > Please do not drop it. > > Compressed instruction extension has some specific overhead in small > RISC-V FPGA softcore, especialy in the ones which can't implement the > register file read in a asynchronous manner because of the FPGA

Re: [PATCH] riscv: kbuild: drop CONFIG_RISCV_ISA_C

2019-08-08 Thread Charles Papon
Please do not drop it. Compressed instruction extension has some specific overhead in small RISC-V FPGA softcore, especialy in the ones which can't implement the register file read in a asynchronous manner because of the FPGA technology. What are reasons to enforce RVC ? On Wed, Aug 7, 2019 at 2:

Re: [PATCH] riscv: kbuild: drop CONFIG_RISCV_ISA_C

2019-08-07 Thread Bin Meng
On Wed, Aug 7, 2019 at 10:30 AM Paul Walmsley wrote: > > > The baseline ISA support requirement for the RISC-V Linux kernel > mandates compressed instructions, so it doesn't make sense for > compressed instruction support to be configurable. > > Signed-off-by: Paul Walmsley > Cc: Atish Patra > >

Re: [PATCH] riscv: kbuild: drop CONFIG_RISCV_ISA_C

2019-08-06 Thread Christoph Hellwig
On Tue, Aug 06, 2019 at 07:30:24PM -0700, Paul Walmsley wrote: > > The baseline ISA support requirement for the RISC-V Linux kernel > mandates compressed instructions, so it doesn't make sense for > compressed instruction support to be configurable. Looks good, Reviewed-by: Christoph Hellwig

[PATCH] riscv: kbuild: drop CONFIG_RISCV_ISA_C

2019-08-06 Thread Paul Walmsley
The baseline ISA support requirement for the RISC-V Linux kernel mandates compressed instructions, so it doesn't make sense for compressed instruction support to be configurable. Signed-off-by: Paul Walmsley Cc: Atish Patra --- arch/riscv/Kconfig | 10 -- arch/riscv/Makefile | 2 +-