Re: [PATCH 0/2] clk: si5351: Multisynth 6-7 fixes

2015-05-16 Thread Sergej Sawazki
On 15.05.2015 at 11:25 Sebastian Hesselbarth wrote: Sergej Sawazki (2): clk: si5351: fix .round_rate for multisynth 6-7 clk: si5351: fix .recalc_rate for multisynth 6-7 Applied both patches to clk-next. Sergei, next time please _always_ keep the version numbering on your patches, IIRC

Re: [PATCH 0/2] clk: si5351: Multisynth 6-7 fixes

2015-05-15 Thread Sebastian Hesselbarth
On 13.05.2015 01:38, Michael Turquette wrote: Quoting Sergej Sawazki (2015-05-11 01:44:19) The second synthesis stage in the Si5351 clock generator consists of six *fractional* multisynth dividers (MS0 .. MS5) and two *even-integer* dividers (MS6 and MS7). The current si5351 driver implementatio

Re: [PATCH 0/2] clk: si5351: Multisynth 6-7 fixes

2015-05-12 Thread Michael Turquette
Quoting Sergej Sawazki (2015-05-11 01:44:19) > The second synthesis stage in the Si5351 clock generator consists of six > *fractional* multisynth dividers (MS0 .. MS5) and two *even-integer* > dividers (MS6 and MS7). The current si5351 driver implementation does > not handle MS6 and MS7 correctly,

[PATCH 0/2] clk: si5351: Multisynth 6-7 fixes

2015-05-11 Thread Sergej Sawazki
The second synthesis stage in the Si5351 clock generator consists of six *fractional* multisynth dividers (MS0 .. MS5) and two *even-integer* dividers (MS6 and MS7). The current si5351 driver implementation does not handle MS6 and MS7 correctly, this leads to wrong rates on output 6 and 7. This p