On Fri, Sep 29, 2017 at 10:39:28AM -0700, Mike Travis wrote:
> >That's where it comes from. But normal systems really _should_ have it
> >at 0 and its a useful sanity check IMO. We really want to know when the
> >BIOS does a funny behind our backs.
> >
>
> How about a more generic flag, such as
On Fri, Sep 29, 2017 at 10:39:28AM -0700, Mike Travis wrote:
> >That's where it comes from. But normal systems really _should_ have it
> >at 0 and its a useful sanity check IMO. We really want to know when the
> >BIOS does a funny behind our backs.
> >
>
> How about a more generic flag, such as
On 9/29/2017 9:23 AM, Peter Zijlstra wrote:
On Fri, Sep 29, 2017 at 08:19:22AM -0700, Mike Travis wrote:
So I would still like to get clarification on how ART works (or likely
doesn't) on your systems. I think for now its fairly prudent to kill
detect_art() on UV.
I tested with both
On 9/29/2017 9:23 AM, Peter Zijlstra wrote:
On Fri, Sep 29, 2017 at 08:19:22AM -0700, Mike Travis wrote:
So I would still like to get clarification on how ART works (or likely
doesn't) on your systems. I think for now its fairly prudent to kill
detect_art() on UV.
I tested with both
On Fri, Sep 29, 2017 at 08:19:22AM -0700, Mike Travis wrote:
> > So I would still like to get clarification on how ART works (or likely
> > doesn't) on your systems. I think for now its fairly prudent to kill
> > detect_art() on UV.
>
> I tested with both detect_art enabled and disabled and
On Fri, Sep 29, 2017 at 08:19:22AM -0700, Mike Travis wrote:
> > So I would still like to get clarification on how ART works (or likely
> > doesn't) on your systems. I think for now its fairly prudent to kill
> > detect_art() on UV.
>
> I tested with both detect_art enabled and disabled and
On 9/29/2017 1:46 AM, Peter Zijlstra wrote:
On Thu, Sep 28, 2017 at 01:03:39PM -0500, mike.tra...@hpe.com wrote:
The UV BIOS goes to considerable effort to get the TSC synchronization
accurate across the entire system. Included in that are multiple chassis
that can have 32+ sockets. The
On 9/29/2017 1:46 AM, Peter Zijlstra wrote:
On Thu, Sep 28, 2017 at 01:03:39PM -0500, mike.tra...@hpe.com wrote:
The UV BIOS goes to considerable effort to get the TSC synchronization
accurate across the entire system. Included in that are multiple chassis
that can have 32+ sockets. The
On Thu, Sep 28, 2017 at 01:03:39PM -0500, mike.tra...@hpe.com wrote:
>
> The UV BIOS goes to considerable effort to get the TSC synchronization
> accurate across the entire system. Included in that are multiple chassis
> that can have 32+ sockets. The architecture does support an external
>
On Thu, Sep 28, 2017 at 01:03:39PM -0500, mike.tra...@hpe.com wrote:
>
> The UV BIOS goes to considerable effort to get the TSC synchronization
> accurate across the entire system. Included in that are multiple chassis
> that can have 32+ sockets. The architecture does support an external
>
The UV BIOS goes to considerable effort to get the TSC synchronization
accurate across the entire system. Included in that are multiple chassis
that can have 32+ sockets. The architecture does support an external
high resolution clock to aid in maintaining this synchronization.
The resulting
The UV BIOS goes to considerable effort to get the TSC synchronization
accurate across the entire system. Included in that are multiple chassis
that can have 32+ sockets. The architecture does support an external
high resolution clock to aid in maintaining this synchronization.
The resulting
12 matches
Mail list logo
