On Fri, Jan 28, 2005 at 08:53:47AM -0600, [EMAIL PROTECTED] wrote:
>
> The IBM Citrine chipset has a feature that if PCI config register
> 0xA0 is read while DMAs are being performed to it, there is the possiblity
> that the parity will be wrong on the PCI bus, causing a parity error and
> a maste
The IBM Citrine chipset has a feature that if PCI config register
0xA0 is read while DMAs are being performed to it, there is the possiblity
that the parity will be wrong on the PCI bus, causing a parity error and
a master abort. On this chipset, this register is simply a debug register
for the ch
2 matches
Mail list logo
